Icarus Verilog
Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
- Sources inherited from project openSUSE:Backports:SLE-15-SP4
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osc -A https://api.opensuse.org checkout openSUSE:Leap:15.4:Update/iverilog && cd $_ - Create Badge
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Source Files
| Filename | Size | Changed |
|---|---|---|
| iverilog.changes | 0000003761 3.67 KB | |
| iverilog.spec | 0000002241 2.19 KB | |
| verilog-10.1.tar.gz | 0001685176 1.61 MB |
Latest Revision
Wolfgang Engel (bigironman)
committed
(revision 1)
osc copypac from project:openSUSE:Backports:SLE-15-SP3 package:iverilog revision:1
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