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SUSE:SLE-12-SP1:GA
xen.1317
5604f2e6-vt-d-fix-IM-bit-mask-and-unmask-of-FEC...
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File 5604f2e6-vt-d-fix-IM-bit-mask-and-unmask-of-FECTL_REG.patch of Package xen.1317
# Commit 86f3ff9fc4cc3cb69b96c1de74bcc51f738fe2b9 # Date 2015-09-25 09:08:22 +0200 # Author Quan Xu <quan.xu@intel.com> # Committer Jan Beulich <jbeulich@suse.com> vt-d: fix IM bit mask and unmask of Fault Event Control Register Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved', software cannot write 0 to it unconditionally. Software must preserve the value read for writes. Signed-off-by: Quan Xu <quan.xu@intel.com> Acked-by: Yang Zhang <yang.z.zhang@intel.com> # Commit 26b300bd727ef00a8f60329212a83c3b027a48f7 # Date 2015-09-25 18:03:04 +0200 # Author Quan Xu <quan.xu@intel.com> # Committer Jan Beulich <jbeulich@suse.com> vt-d: fix IM bit unmask of Fault Event Control Register in init_vtd_hw() Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved', software cannot write 0 to it unconditionally. Software must preserve the value read for writes. Suggested-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Quan Xu <quan.xu@intel.com> --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -992,10 +992,13 @@ static void dma_msi_unmask(struct irq_de { struct iommu *iommu = desc->action->dev_id; unsigned long flags; + u32 sts; /* unmask it */ spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, 0); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts &= ~DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); iommu->msi.msi_attrib.host_masked = 0; } @@ -1004,10 +1007,13 @@ static void dma_msi_mask(struct irq_desc { unsigned long flags; struct iommu *iommu = desc->action->dev_id; + u32 sts; /* mask it */ spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, DMA_FECTL_IM); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts |= DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); iommu->msi.msi_attrib.host_masked = 1; } @@ -2055,6 +2061,7 @@ static int init_vtd_hw(void) struct iommu_flush *flush = NULL; int ret; unsigned long flags; + u32 sts; /* * Basic VT-d HW init: set VT-d interrupt, clear VT-d faults. @@ -2068,7 +2075,9 @@ static int init_vtd_hw(void) clear_fault_bits(iommu); spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, 0); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts &= ~DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); }
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