File verilator.spec of Package verilator

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File verilator.spec of Package verilator

#
# spec file for package verilator
#
# Copyright (c) 2014 SUSE LINUX Products GmbH, Nuernberg, Germany.
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
# upon. The license for this file, and modifications and additions to the
# file, is the same license as for the pristine package itself (unless the
# license for the pristine package is not an Open Source License, in which
# case the license is the MIT License). An "Open Source License" is a
# license that conforms to the Open Source Definition (Version 1.9)
# published by the Open Source Initiative.

# Please submit bugfixes or comments via http://bugs.opensuse.org/
#

Name:           verilator
Version:        3.862
Release:        0
Summary:        A fast simulator for synthesizable Verilog
License:        Artistic-2.0 or LGPL-3.0
Group:          Productivity/Scientific/Electronics
URL:            http://www.veripool.org/projects/verilator/wiki/Intro
Source0:        http://www.veripool.org/ftp/%{name}-%{version}.tgz
Source1:        verilator-rpmlintrc
BuildRequires:  bison
BuildRequires:  flex
BuildRequires:  gcc-c++
BuildRequires:  gdb
BuildRequires:  perl
BuildRequires:  perl-SystemPerl-devel
BuildRoot:      %{_tmppath}/%{name}-%{version}-build

%description
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.

%package        doc
Summary:        Documentation for verilator in HTML format
Group:          Documentation/HTML
Requires:       %{name} = %{version}
BuildArch:      noarch

%description    doc
Verilator is the fastest free Verilog HDL simulator.

This package contains documentation for verilator in HTML format.

%package        doc-pdf
Summary:        Documentation for verilator in PDF format
Group:          Documentation/Other
Requires:       %{name} = %{version}
BuildArch:      noarch

%description    doc-pdf
Verilator is the fastest free Verilog HDL simulator.

This package contains documentation for verilator in PDF format.

%package        examples
Summary:        Examples for verilator
Group:          Documentation/Other
Requires:       %{name} = %{version}
BuildArch:      noarch

%description    examples
Verilator is the fastest free Verilog HDL simulator.

This package contains examples of using verilator.

%prep
%setup -q

%build
%configure --enable-envdef
make %{?_smp_mflags} SYSTEMPERL_INCLUDE=%{_includedir}/perl-SystemPerl

%install
%make_install

# install documentation
install -d %{buildroot}%{_docdir}/%{name}/
install -Dm644 *.html %{buildroot}%{_docdir}/%{name}/
install -Dm644 *.pdf %{buildroot}%{_docdir}/%{name}/

# install examples
mv %{buildroot}%{_datadir}/verilator/examples %{buildroot}%{_docdir}/%{name}/examples

%check
make test

%files
%defattr(-,root,root)
%doc Artistic COPYING.LESSER Changes README
%exclude %{_docdir}/%{name}/*.html
%exclude %{_docdir}/%{name}/*.pdf
%exclude %{_docdir}/%{name}/examples/
%{_bindir}/verilator
%{_bindir}/verilator_bin
%{_bindir}/verilator_bin_dbg
%{_bindir}/verilator_profcfunc
%{_datadir}/verilator/
%{_mandir}/man1/verilator.1.gz

%files doc
%defattr(-,root,root)
%{_docdir}/%{name}/*.html

%files doc-pdf
%defattr(-,root,root)
%{_docdir}/%{name}/*.pdf

%files examples
%defattr(-,root,root)
%doc %{_docdir}/%{name}/examples/

%changelog

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