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qemu-testsuite.19805
0134-i386-Add-CPUID-bit-and-feature-word.patch
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File 0134-i386-Add-CPUID-bit-and-feature-word.patch of Package qemu-testsuite.19805
From: Robert Hoo <robert.hu@linux.intel.com> Date: Thu, 5 Jul 2018 17:09:55 +0800 Subject: i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> (cherry picked from commit 3fc7c73139d2d38ae80c3b0bc963b1ac1555924c) [BR: BSC#1134880, FATE#327763] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target/i386/cpu.c | 3 ++- target/i386/cpu.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 281b101a113f77563d6f8bf70f3c..c01bdbdd96357c0254288a4ed49f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -485,12 +485,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, "ssbd", + NULL, "arch-capabilities", NULL, "ssbd", }, .cpuid_eax = 7, .cpuid_needs_ecx = true, .cpuid_ecx = 0, .cpuid_reg = R_EDX, .tcg_features = TCG_7_0_EDX_FEATURES, + .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES, }, [FEAT_8000_0007_EDX] = { .feat_names = { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0410642dab0f2086ec4fe8352efe..78f6dbc026a3419e549467c99d9b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -655,6 +655,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_MD_CLEAR (1U << 10) /* Microarchitectural Data Clear */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
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