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DISCONTINUED:openSUSE:11.1
cross-s390x-gcc-icecream-backend
ibm304071-z10-7
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File ibm304071-z10-7 of Package cross-s390x-gcc-icecream-backend
Index: gcc/config/s390/2097.md =================================================================== *** /dev/null 1970-01-01 00:00:00.000000000 +0000 --- gcc/config/s390/2097.md 2008-08-15 09:09:26.000000000 +0200 *************** *** 0 **** --- 1,764 ---- + ;; Scheduling description for z10 (cpu 2097). + ;; Copyright (C) 2008 Free Software Foundation, Inc. + ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com). + + + ; General naming conventions used in this file: + ; - The two pipelines are called S and T, respectively. + ; - A name ending "_S" or "_T" indicates that something happens in + ; (or belongs to) this pipeline. + ; - A name ending "_ANY" indicates that something happens in (or belongs + ; to) either of the two pipelines. + ; - A name ending "_BOTH" indicates that something happens in (or belongs + ; to) both pipelines. + + + ;; Automaton and components. + + (define_automaton "z10_cpu") + + (define_cpu_unit "z10_e1_S, z10_e1_T" "z10_cpu") + (define_reservation "z10_e1_ANY" "(z10_e1_S | z10_e1_T)") + (define_reservation "z10_e1_BOTH" "(z10_e1_S + z10_e1_T)") + + + ; Both pipelines can execute a branch instruction, and branch + ; instructions can be grouped with all other groupable instructions + ; but not with a second branch instruction. + + (define_cpu_unit "z10_branch_ANY" "z10_cpu") + + (define_insn_reservation "z10_branch" 4 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "branch")) + "z10_branch_ANY + z10_e1_ANY, z10_Gate_ANY") + + + ; Z10 operand and result forwarding. + + ; Instructions marked with the attributes as z10_fwd or z10_fr can + ; forward a value they load from one of their operants into a register + ; if the instruction in the second pipeline reads the same register. + ; The second operation must be superscalar. Instructions marked as + ; z10_rec or z10_fr can receive a value they read from a register is + ; this register gets updated by an instruction in the first pipeline. + ; The first instruction must be superscalar. + + + ; Forwarding from z10_fwd and z10_fr to z10_super. + + (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \ + z10_load_fwd, z10_load_fwd_A3, \ + z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \ + z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \ + z10_other_fwd_E1, z10_lr_fr, z10_lr_fr_E1, \ + z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \ + z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \ + z10_int_fr_A3" + "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \ + z10_int_super, z10_int_super_E1, \ + z10_lr, z10_store_super") + + + ; Forwarding from z10_super to frz10_ and z10_rec. + + (define_bypass 0 "z10_other_super, z10_other_super_E1, z10_other_super_c_E1, \ + z10_int_super, z10_int_super_E1, \ + z10_larl_super_E1, z10_larl_super, \ + z10_store_super" + "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ + z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ + z10_other_fr_E1, z10_store_rec") + + + ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr. + + (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \ + z10_load_fwd, z10_load_fwd_A3, \ + z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \ + z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \ + z10_other_fwd_E1, \ + z10_lr_fr, z10_lr_fr_E1, \ + z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \ + z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \ + z10_int_fr_A3" + "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ + z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ + z10_other_fr_E1, z10_store_rec") + + + ; + ; Simple insns + ; + + ; Here is the cycle diagram for FXU-executed instructions: + ; ... A1 A2 A3 E1 P1 P2 P3 R0 ... + ; ^ ^ ^ + ; | | updated GPR is available + ; | write to GPR + ; instruction reads GPR during this cycle + + + ; Variants of z10_int follow. + + (define_insn_reservation "z10_int" 6 + (and (and (eq_attr "cpu" "z10") + (eq_attr "type" "integer")) + (and (eq_attr "atype" "reg") + (and (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c")) + (and (and (and (and (eq_attr "z10prop" "!z10_super_E1") + (eq_attr "z10prop" "!z10_super_c_E1")) + (eq_attr "z10prop" "!z10_fwd")) + (and (eq_attr "z10prop" "!z10_fwd_A1") + (eq_attr "z10prop" "!z10_fwd_A3"))) + (and (and (eq_attr "z10prop" "!z10_fwd_E1") + (eq_attr "z10prop" "!z10_fr")) + (and (eq_attr "z10prop" "!z10_fr_E1") + (eq_attr "z10prop" "!z10_fr_A3"))))))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (ior (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c"))))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_super_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (ior (eq_attr "z10prop" "z10_super_E1") + (eq_attr "z10prop" "z10_super_c_E1"))))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fwd_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd_A1")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd_A3")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fwd_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fr")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fr_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fr_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_int_fr_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fr_A3")))) + "z10_e1_ANY, z10_Gate_ANY") + + ; END of z10_int variants + + + (define_insn_reservation "z10_agen" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (eq_attr "atype" "agen"))) + "z10_e1_ANY, z10_Gate_ANY") + + + (define_insn_reservation "z10_lr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "lr") + (and (eq_attr "z10prop" "!z10_fr") + (eq_attr "z10prop" "!z10_fr_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_lr_fr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "lr") + (eq_attr "z10prop" "z10_fr"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + (define_insn_reservation "z10_lr_fr_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "lr") + (eq_attr "z10prop" "z10_fr_E1"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + + (define_insn_reservation "z10_la" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "la") + (and (eq_attr "z10prop" "!z10_fwd") + (eq_attr "z10prop" "!z10_fwd_A1")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_la_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "la") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + (define_insn_reservation "z10_la_fwd_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "la") + (eq_attr "z10prop" "z10_fwd_A1"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + + ; larl-type instructions + + (define_insn_reservation "z10_larl" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (and (eq_attr "z10prop" "!z10_super_A1") + (and (eq_attr "z10prop" "!z10_fwd") + (and (eq_attr "z10prop" "!z10_fwd_A3") + (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c")) + (and (eq_attr "z10prop" "!z10_super_E1") + (eq_attr "z10prop" "!z10_super_c_E1"))))))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_larl_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (and (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_larl_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_larl_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (eq_attr "z10prop" "z10_fwd_A3"))) + "z10_e1_ANY, z10_Gate_ANY") + + + (define_insn_reservation "z10_larl_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (eq_attr "z10prop" "z10_super_A1"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + (define_insn_reservation "z10_larl_super_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (ior (eq_attr "z10prop" "z10_super_E1") + (eq_attr "z10prop" "z10_super_c_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + + (define_insn_reservation "z10_load" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "load") + (and (eq_attr "z10prop" "!z10_fwd") + (eq_attr "z10prop" "!z10_fwd_A3")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_load_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "load") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + (define_insn_reservation "z10_load_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "load") + (eq_attr "z10prop" "z10_fwd_A3"))) + "z10_e1_ANY, z10_Gate_ANY") + ; "z10_e1_ANY") + + (define_insn_reservation "z10_store" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "store") + (and (eq_attr "z10prop" "!z10_rec") + (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c"))))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_store_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "store") + (ior (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c")))) + "z10_e1_ANY, z10_Gate_ANY") + + (define_insn_reservation "z10_store_rec" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "store") + (eq_attr "z10prop" "z10_rec"))) + "z10_e1_ANY, z10_Gate_ANY") + + ; The default_latency is chosen to drain off the pipeline. + (define_insn_reservation "z10_call" 14 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "jsr")) + "z10_e1_BOTH*4, z10_Gate_BOTH") + + ; The default latency is for worst case. CS and CSG take one + ; cycle only (i.e. latency would be 6). + (define_insn_reservation "z10_sem" 9 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "sem")) + "z10_e1_BOTH*5, z10_Gate_ANY") + + (define_insn_reservation "z10_cs" 6 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "cs")) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_vs" 6 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "vs")) + "z10_e1_BOTH*4, z10_Gate_BOTH") + + ; Load and store multiple. Actual number of cycles + ; in unknown at compile.time. + (define_insn_reservation "z10_stm" 10 + (and (eq_attr "cpu" "z10") + (ior (eq_attr "type" "stm") + (eq_attr "type" "lm"))) + "z10_e1_BOTH*4, z10_Gate_BOTH") + + + ; Subsets of z10_other follow. + + (define_insn_reservation "z10_other" 6 + (and (and (eq_attr "cpu" "z10") + (eq_attr "type" "other")) + (and (and (eq_attr "z10prop" "!z10_fwd") + (eq_attr "z10prop" "!z10_fwd_A1")) + (and (and (and (eq_attr "z10prop" "!z10_fr_A3") + (eq_attr "z10prop" "!z10_fwd_A3")) + (and (eq_attr "z10prop" "!z10_fr") + (eq_attr "z10prop" "!z10_fr_E1"))) + (and (and (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c")) + (eq_attr "z10prop" "!z10_super_c_E1")) + (and (eq_attr "z10prop" "!z10_super_E1") + (eq_attr "z10prop" "!z10_fwd_E1")))))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fr_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fr_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_super_c_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_super_c_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_super_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_super_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fwd_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd_A3"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fwd_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd_A1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fr"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_fr_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fr_A3"))) + "z10_e1_BOTH, z10_Gate_BOTH") + + (define_insn_reservation "z10_other_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (ior (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c")))) + "z10_e1_BOTH, z10_Gate_BOTH") + + ; END of z10_other subsets. + + + ; + ; Floating point insns + ; + + ; Z10 executes the following integer operations in the BFU pipeline. + + (define_insn_reservation "z10_mul_sidi" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "imulsi,imuldi,imulhi")) + "z10_e1_BOTH, z10_Gate_FP") + + ; Some variants take fewer cycles, but that is not relevant here. + (define_insn_reservation "z10_div" 162 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "idiv")) + "z10_e1_BOTH*4, z10_Gate_FP") + + + ; BFP multiplication and general instructions + + (define_insn_reservation "z10_fsimpdf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpdf,fmuldf")) + "z10_e1_BOTH, z10_Gate_FP") + ; Wg "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_fsimpsf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpsf,fmulsf")) + "z10_e1_BOTH, z10_Gate_FP") + ; Wg "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_fmultf" 52 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fmultf")) + "z10_e1_BOTH*4, z10_Gate_FP") + ; Wg "z10_e1_T*4, z10_Gate_FP") + + (define_insn_reservation "z10_fsimptf" 14 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimptf")) + "z10_e1_BOTH*2, z10_Gate_FP") + ; Wg "z10_e1_T*2, z10_Gate_FP") + + + ; BFP division + + (define_insn_reservation "z10_fdivtf" 113 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivtf")) + "z10_e1_T*4, z10_Gate_FP") + + (define_insn_reservation "z10_fdivdf" 41 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivdf")) + "z10_e1_T*4, z10_Gate_FP") + + (define_insn_reservation "z10_fdivsf" 34 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivsf")) + "z10_e1_T*4, z10_Gate_FP") + + + ; BFP sqrt + + (define_insn_reservation "z10_fsqrtsf" 41 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsqrtsf")) + "z10_e1_T*4, z10_Gate_FP") + + (define_insn_reservation "z10_fsqrtdf" 54 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsqrtdf")) + "z10_e1_T*4, z10_Gate_FP") + + (define_insn_reservation "z10_fsqrtf" 122 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsqrttf")) + "z10_e1_T*4, z10_Gate_FP") + + + ; BFP load and store + + (define_insn_reservation "z10_floadtf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floadtf")) + "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_floaddf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floaddf")) + "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_floadsf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floadsf")) + "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_fstoredf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fstoredf,fstoredd")) + "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_fstoresf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fstoresf,fstoresd")) + "z10_e1_T, z10_Gate_FP") + + + ; BFP truncate + (define_insn_reservation "z10_ftrunctf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftrunctf")) + "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_ftruncdf" 16 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftruncdf")) + "z10_e1_T, z10_Gate_FP") + + + ; Conversion between BFP and int. + (define_insn_reservation "z10_ftoi" 13 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftoi")) + "z10_e1_T, z10_Gate_FP") + + (define_insn_reservation "z10_itoftf" 14 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itoftf")) + "z10_e1_T*2, z10_Gate_FP") + + (define_insn_reservation "z10_itofsfdf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itofdf,itofsf")) + "z10_e1_T, z10_Gate_FP") + + + + ; BFP-related bypasses. There is no bypass for extended mode. + (define_bypass 1 "z10_fsimpdf" "z10_fstoredf") + (define_bypass 1 "z10_fsimpsf" "z10_fstoresf") + (define_bypass 1 "z10_floaddf" "z10_fsimpdf, z10_fstoredf, z10_floaddf") + (define_bypass 1 "z10_floadsf" "z10_fsimpsf, z10_fstoresf, z10_floadsf") + + + ; + ; insn_reservations for DFP instructions. + ; + + ; Exact number of cycles is not known at compile-time. + (define_insn_reservation "z10_fdivddtd" 40 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivdd,fdivtd")) + "z10_e1_BOTH,z10_Gate_DFU") + + (define_insn_reservation "z10_ftruncsd" 38 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftruncsd")) + "z10_e1_BOTH*4,z10_Gate_DFU") + + (define_insn_reservation "z10_ftruncdd" 340 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftruncsd")) + "z10_e1_BOTH*4,z10_Gate_DFU") + + (define_insn_reservation "z10_floaddd" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floaddd")) + "z10_e1_BOTH,z10_Gate_DFU") + + (define_insn_reservation "z10_floadsd" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floadsd")) + "z10_e1_BOTH,z10_Gate_DFU") + + ; Exact number of cycles is not known at compile-time. + (define_insn_reservation "z10_fmulddtd" 35 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fmuldd,fmultd")) + "z10_e1_BOTH,z10_Gate_DFU") + + (define_insn_reservation "z10_fsimpdd" 17 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpdd")) + "z10_e1_BOTH,z10_Gate_DFU") + + (define_insn_reservation "z10_fsimpsd" 17 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpsd")) + "z10_e1_BOTH,z10_Gate_DFU") + + (define_insn_reservation "z10_fsimptd" 18 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimptd")) + "z10_e1_BOTH,z10_Gate_DFU") + + (define_insn_reservation "z10_itofdd" 36 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itofdd")) + "z10_e1_BOTH*3,z10_Gate_DFU") + + (define_insn_reservation "z10_itoftd" 49 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itoftd")) + "z10_e1_BOTH*3,z10_Gate_DFU") + + ; Exact number of cycles is not known at compile-time. + (define_insn_reservation "z10_ftoidfp" 30 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftoidfp")) + "z10_e1_BOTH*3,z10_Gate_DFU") + + + ; + ; Address-related bypasses + ; + + ; Here is the cycle diagram for Address-related bypasses: + ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ... + ; ^ ^ ^ ^ ^ + ; | | | | E1-type bypasses provide the new addr AFTER this cycle + ; | | | A3-type bypasses provide the new addr AFTER this cycle + ; | | A1-type bypasses provide the new addr AFTER this cycle + ; | AGI resolution, actual USE of address is DURING this cycle + ; AGI detection + + (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \ + z10_int_fwd_A1" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + + + (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \ + z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + + (define_bypass 6 "z10_other_fr_E1, z10_other_super_c_E1, z10_other_super_E1, \ + z10_other_fwd_E1, \ + z10_lr_fr_E1, z10_larl_super_E1, \ + z10_int_super_E1, z10_int_fwd_E1, z10_int_fr_E1" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + + + + ; + ; Try to avoid transitions between DFU-, BFU- and FXU-executed instructions as there is a + ; dispatch delay required. + ; + + + ; Declaration for some pseudo-pipeline stages that reflect the + ; dispatch gap when issueing an INT/FXU/BFU-executed instruction after + ; an instruction executed by a different unit has been executed. The + ; approach is that we pretend a pipelined execution of BFU operations + ; with as many stages as the gap is long and request that none of + ; these stages is busy when issueing a FXU- or DFU-executed + ; instruction. Similar for FXU- and DFU-executed instructions. + + ; Declaration for FPU stages. + (define_cpu_unit "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, \ + z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, z10_f12" "z10_cpu") + (define_reservation "z10_FP_PP" "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, \ + z10_f5, z10_f6, z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, \ + z10_f12") + + ; Declaration for FXU stages. + (define_cpu_unit "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6" "z10_cpu") + (define_cpu_unit "z10_T1, z10_T2, z10_T3, z10_T4, z10_T5, z10_T6" "z10_cpu") + (define_reservation "z10_INT_PP" "z10_S1 | z10_T1, z10_S2 | z10_T2, z10_S3 \ + | z10_T3, z10_S4 | z10_T4, z10_S5 | \ + z10_T5, z10_S6 | z10_T6") + + ; Declaration for DFU stages. + (define_cpu_unit "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6" + "z10_cpu") + (define_reservation "z10_DFU_PP" "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, \ + z10_d5, z10_d6") + + + ; Pseudo-units representing whether the respective unit is available + ; in the sense that using it does not cause a dispatch delay. + + (define_cpu_unit "z10_S_avail, z10_T_avail, z10_FP_avail, z10_DFU_avail" + "z10_cpu") + + (absence_set "z10_FP_avail" + "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \ + z10_T5, z10_T6, \ + z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6") + + (absence_set "z10_S_avail,z10_T_avail" + "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \ + z10_f8, z10_f9, z10_f10, z10_f11, z10_f12, \ + z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6") + + (absence_set "z10_DFU_avail" + "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \ + z10_T5, z10_T6, \ + z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \ + z10_f8, z10_f9, z10_f10, z10_f11, z10_f12") + + + ; Pseudo-units to be used in insn_reservations. + + (define_reservation "z10_Gate_ANY" "((z10_S_avail | z10_T_avail), z10_INT_PP)") + (define_reservation "z10_Gate_BOTH" "((z10_S_avail + z10_T_avail), z10_INT_PP)") + + (define_reservation "z10_Gate_FP" "z10_FP_avail, z10_FP_PP") + + (define_reservation "z10_Gate_DFU" "z10_DFU_avail, z10_DFU_PP") Index: gcc/config/s390/s390.md =================================================================== *** gcc/config/s390/s390.md.orig 2008-08-15 09:08:50.000000000 +0200 --- gcc/config/s390/s390.md 2008-08-15 09:09:26.000000000 +0200 *************** *** 202,209 **** branch,jsr,fsimptf,fsimpdf,fsimpsf, floadtf,floaddf,floadsf,fstoredf,fstoresf, fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, ! ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf, ! ftrunctf,ftruncdf,other" (cond [(eq_attr "op_type" "NN") (const_string "other") (eq_attr "op_type" "SS") (const_string "cs")] (const_string "integer"))) --- 202,213 ---- branch,jsr,fsimptf,fsimpdf,fsimpsf, floadtf,floaddf,floadsf,fstoredf,fstoresf, fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, ! ftoi,fsqrttf,fsqrtdf,fsqrtsf, ! ftrunctf,ftruncdf, ftruncsd, ftruncdd, ! itoftf, itofdf, itofsf, itofdd, itoftd, ! fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, ! fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, ! ftoidfp, other" (cond [(eq_attr "op_type" "NN") (const_string "other") (eq_attr "op_type" "SS") (const_string "cs")] (const_string "integer"))) *************** *** 217,222 **** --- 221,251 ---- (const_string "reg") (const_string "agen"))) + ;; Properties concerning Z10 execution grouping and value forwarding. + ;; z10_super: instruction is superscalar. + ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. + ;; z10_fwd: The instruction reads the value of an operand and stores it into a + ;; target register. It can forward this value to a second instruction that reads + ;; the same register if that second instruction is issued in the same group. + ;; z10_rec: The instruction is in the T pipeline and reads a register. If the + ;; instruction in the S pipe writes to the register, then the T instruction + ;; can immediately read the new value. + ;; z10_fr: union of Z10_fwd and z10_rec. + ;; z10_c: second operand of instruction is a register and read with complemented bits. + ;; z10_cobra: its a compare and branch instruction + ;; + ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. + + + (define_attr "z10prop" "none, + z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, + z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, + z10_rec, + z10_fr, z10_fr_A3, z10_fr_E1, + z10_c, z10_cobra" + (const_string "none")) + + ;; Length in bytes. (define_attr "length" "" *************** *** 272,277 **** --- 301,309 ---- ;; Pipeline description for z990, z9-109 and z9-ec. (include "2084.md") + ;; Pipeline description for z10 + (include "2097.md") + ;; Predicates (include "predicates.md") *************** *** 388,399 **** ;; modes and to an empty string for bfp modes. (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) - ;; Although it is imprecise for z9-ec we handle all dfp instructions like - ;; bfp regarding the pipeline description. - (define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf") - (TD "tf") (DD "df") (SD "sf")]) - - ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode ;; and "0" in SImode. This allows to combine instructions of which the 31bit ;; version only operates on one register. --- 420,425 ---- *************** *** 403,415 **** ;; version only operates on one register. The DImode version needs an additional ;; register for the assembler output. (define_mode_attr 1 [(DI "%1,") (SI "")]) ! ! ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in ;; 'ashift' and "srdl" in 'lshiftrt'. (define_code_attr lr [(ashift "l") (lshiftrt "r")]) ;; In SHIFT templates, this attribute holds the correct standard name for the ! ;; pattern itself and the corresponding function calls. (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) ;; This attribute handles differences in the instruction 'type' and will result --- 429,441 ---- ;; version only operates on one register. The DImode version needs an additional ;; register for the assembler output. (define_mode_attr 1 [(DI "%1,") (SI "")]) ! ! ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in ;; 'ashift' and "srdl" in 'lshiftrt'. (define_code_attr lr [(ashift "l") (lshiftrt "r")]) ;; In SHIFT templates, this attribute holds the correct standard name for the ! ;; pattern itself and the corresponding function calls. (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) ;; This attribute handles differences in the instruction 'type' and will result *************** *** 499,505 **** "@ tm\t%S0,%b1 tmy\t%S0,%b1" ! [(set_attr "op_type" "SI,SIY")]) (define_insn "*tmdi_reg" [(set (reg CC_REGNUM) --- 525,532 ---- "@ tm\t%S0,%b1 tmy\t%S0,%b1" ! [(set_attr "op_type" "SI,SIY") ! (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*tmdi_reg" [(set (reg CC_REGNUM) *************** *** 515,521 **** tmhl\t%0,%i1 tmlh\t%0,%i1 tmll\t%0,%i1" ! [(set_attr "op_type" "RI")]) (define_insn "*tmsi_reg" [(set (reg CC_REGNUM) --- 542,549 ---- tmhl\t%0,%i1 tmlh\t%0,%i1 tmll\t%0,%i1" ! [(set_attr "op_type" "RI") ! (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) (define_insn "*tmsi_reg" [(set (reg CC_REGNUM) *************** *** 558,564 **** "ltgfr\t%2,%0 ltgf\t%2,%0" [(set_attr "op_type" "RRE,RXY") ! (set_attr "cpu_facility" "*,z10")]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_extimm" --- 586,593 ---- "ltgfr\t%2,%0 ltgf\t%2,%0" [(set_attr "op_type" "RRE,RXY") ! (set_attr "cpu_facility" "*,z10") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_extimm" *************** *** 571,577 **** "@ lt<g>r\t%2,%0 lt<g>\t%2,%0" ! [(set_attr "op_type" "RR<E>,RXY")]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_cconly_extimm" --- 600,607 ---- "@ lt<g>r\t%2,%0 lt<g>\t%2,%0" ! [(set_attr "op_type" "RR<E>,RXY") ! (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_cconly_extimm" *************** *** 583,589 **** "@ lt<g>r\t%0,%0 lt<g>\t%2,%0" ! [(set_attr "op_type" "RR<E>,RXY")]) (define_insn "*tstdi" [(set (reg CC_REGNUM) --- 613,620 ---- "@ lt<g>r\t%0,%0 lt<g>\t%2,%0" ! [(set_attr "op_type" "RR<E>,RXY") ! (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")]) (define_insn "*tstdi" [(set (reg CC_REGNUM) *************** *** 593,599 **** (match_dup 0))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" "ltgr\t%2,%0" ! [(set_attr "op_type" "RRE")]) (define_insn "*tstsi" [(set (reg CC_REGNUM) --- 624,631 ---- (match_dup 0))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" "ltgr\t%2,%0" ! [(set_attr "op_type" "RRE") ! (set_attr "z10prop" "z10_fr_E1")]) (define_insn "*tstsi" [(set (reg CC_REGNUM) *************** *** 606,612 **** ltr\t%2,%0 icm\t%2,15,%S0 icmy\t%2,15,%S0" ! [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly" [(set (reg CC_REGNUM) --- 638,645 ---- ltr\t%2,%0 icm\t%2,15,%S0 icmy\t%2,15,%S0" ! [(set_attr "op_type" "RR,RS,RSY") ! (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (define_insn "*tstsi_cconly" [(set (reg CC_REGNUM) *************** *** 618,624 **** ltr\t%0,%0 icm\t%2,15,%S0 icmy\t%2,15,%S0" ! [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstdi_cconly_31" [(set (reg CC_REGNUM) --- 651,658 ---- ltr\t%0,%0 icm\t%2,15,%S0 icmy\t%2,15,%S0" ! [(set_attr "op_type" "RR,RS,RSY") ! (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (define_insn "*tstdi_cconly_31" [(set (reg CC_REGNUM) *************** *** 636,642 **** (match_operand:GPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" "lt<g>r\t%0,%0" ! [(set_attr "op_type" "RR<E>")]) ; tst(hi|qi) instruction pattern(s). --- 670,677 ---- (match_operand:GPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" "lt<g>r\t%0,%0" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_fr_E1")]) ; tst(hi|qi) instruction pattern(s). *************** *** 651,657 **** icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0 tml\t%0,<max_uint>" ! [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tsthiCCT_cconly" [(set (reg CC_REGNUM) --- 686,693 ---- icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0 tml\t%0,<max_uint>" ! [(set_attr "op_type" "RS,RSY,RI") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (define_insn "*tsthiCCT_cconly" [(set (reg CC_REGNUM) *************** *** 663,669 **** icm\t%2,3,%S0 icmy\t%2,3,%S0 tml\t%0,65535" ! [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tstqiCCT_cconly" [(set (reg CC_REGNUM) --- 699,706 ---- icm\t%2,3,%S0 icmy\t%2,3,%S0 tml\t%0,65535" ! [(set_attr "op_type" "RS,RSY,RI") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (define_insn "*tstqiCCT_cconly" [(set (reg CC_REGNUM) *************** *** 674,680 **** cli\t%S0,0 cliy\t%S0,0 tml\t%0,255" ! [(set_attr "op_type" "SI,SIY,RI")]) (define_insn "*tst<mode>" [(set (reg CC_REGNUM) --- 711,718 ---- cli\t%S0,0 cliy\t%S0,0 tml\t%0,255" ! [(set_attr "op_type" "SI,SIY,RI") ! (set_attr "z10prop" "z10_super,z10_super,*")]) (define_insn "*tst<mode>" [(set (reg CC_REGNUM) *************** *** 686,692 **** "@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0" ! [(set_attr "op_type" "RS,RSY")]) (define_insn "*tst<mode>_cconly" [(set (reg CC_REGNUM) --- 724,731 ---- "@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0" ! [(set_attr "op_type" "RS,RSY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*tst<mode>_cconly" [(set (reg CC_REGNUM) *************** *** 697,703 **** "@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0" ! [(set_attr "op_type" "RS,RSY")]) ; Compare (equality) instructions --- 736,743 ---- "@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0" ! [(set_attr "op_type" "RS,RSY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; Compare (equality) instructions *************** *** 713,719 **** cgfi\t%0,%1 cg\t%0,%1 #" ! [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")]) (define_insn "*cmpsi_cct" [(set (reg CC_REGNUM) --- 753,760 ---- cgfi\t%0,%1 cg\t%0,%1 #" ! [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") ! (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) (define_insn "*cmpsi_cct" [(set (reg CC_REGNUM) *************** *** 727,734 **** c\t%0,%1 cy\t%0,%1 #" ! [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")]) ! ; Compare (signed) instructions --- 768,775 ---- c\t%0,%1 cy\t%0,%1 #" ! [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") ! (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")]) ; Compare (signed) instructions *************** *** 743,751 **** cgf\t%0,%1 cgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") ! (set_attr "cpu_facility" "*,*,z10") (set_attr "type" "*,*,larl")]) (define_insn "*cmpsi_ccs_sign" [(set (reg CC_REGNUM) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) --- 784,794 ---- cgf\t%0,%1 cgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") ! (set_attr "z10prop" "z10_c,*,*") (set_attr "type" "*,*,larl")]) + + (define_insn "*cmpsi_ccs_sign" [(set (reg CC_REGNUM) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) *************** *** 796,802 **** c<g>rl\t%0,%1" [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") ! (set_attr "type" "*,*,*,*,*,*,larl")]) ; Compare (unsigned) instructions --- 839,846 ---- c<g>rl\t%0,%1" [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") ! (set_attr "type" "*,*,*,*,*,*,larl") ! (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) ; Compare (unsigned) instructions *************** *** 820,826 **** "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" "cl<g>hrl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl")]) (define_insn "*cmpdi_ccu_zero" [(set (reg CC_REGNUM) --- 864,871 ---- "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" "cl<g>hrl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl") ! (set_attr "z10prop" "z10_super")]) (define_insn "*cmpdi_ccu_zero" [(set (reg CC_REGNUM) *************** *** 834,840 **** clgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "cpu_facility" "*,*,z10") ! (set_attr "type" "*,*,larl")]) (define_insn "*cmpdi_ccu" [(set (reg CC_REGNUM) --- 879,886 ---- clgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "cpu_facility" "*,*,z10") ! (set_attr "type" "*,*,larl") ! (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) (define_insn "*cmpdi_ccu" [(set (reg CC_REGNUM) *************** *** 853,859 **** #" [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") ! (set_attr "type" "*,*,larl,*,*,*,*")]) (define_insn "*cmpsi_ccu" [(set (reg CC_REGNUM) --- 899,906 ---- #" [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") ! (set_attr "type" "*,*,larl,*,*,*,*") ! (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) (define_insn "*cmpsi_ccu" [(set (reg CC_REGNUM) *************** *** 871,877 **** #" [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") ! (set_attr "type" "*,*,larl,*,*,*,*,*")]) (define_insn "*cmphi_ccu" [(set (reg CC_REGNUM) --- 918,925 ---- #" [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") ! (set_attr "type" "*,*,larl,*,*,*,*,*") ! (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) (define_insn "*cmphi_ccu" [(set (reg CC_REGNUM) *************** *** 886,892 **** # #" [(set_attr "op_type" "RS,RSY,SIL,SS,SS") ! (set_attr "cpu_facility" "*,*,z10,*,*")]) (define_insn "*cmpqi_ccu" [(set (reg CC_REGNUM) --- 934,941 ---- # #" [(set_attr "op_type" "RS,RSY,SIL,SS,SS") ! (set_attr "cpu_facility" "*,*,z10,*,*") ! (set_attr "z10prop" "*,*,z10_super,*,*")]) (define_insn "*cmpqi_ccu" [(set (reg CC_REGNUM) *************** *** 901,907 **** cliy\t%S0,%b1 # #" ! [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) ; Block compare (CLC) instruction patterns. --- 950,957 ---- cliy\t%S0,%b1 # #" ! [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") ! (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) ; Block compare (CLC) instruction patterns. *************** *** 948,954 **** "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" "lt<xde><bt>r\t%0,%0" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<bfp>")]) ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr (define_insn "*cmp<mode>_ccs" --- 998,1004 ---- "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" "lt<xde><bt>r\t%0,%0" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<mode>")]) ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr (define_insn "*cmp<mode>_ccs" *************** *** 960,971 **** c<xde><bt>r\t%0,%1 c<xde>b\t%0,%1" [(set_attr "op_type" "RRE,RXE") ! (set_attr "type" "fsimp<bfp>")]) ; Compare and Branch instructions ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr (define_insn "*cmp_and_br_signed_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_signed_integer_comparison" --- 1010,1023 ---- c<xde><bt>r\t%0,%1 c<xde>b\t%0,%1" [(set_attr "op_type" "RRE,RXE") ! (set_attr "type" "fsimp<mode>")]) ; Compare and Branch instructions ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr + ; The following instructions do a complementary access of their second + ; operand (z01 only): crj_c, cgrjc, cr, cgr (define_insn "*cmp_and_br_signed_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_signed_integer_comparison" *************** *** 985,996 **** --- 1037,1051 ---- } [(set_attr "op_type" "RIE") (set_attr "type" "branch") + (set_attr "z10prop" "z10_cobra,z10_super") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg ; 10 byte for cgr/jg ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr + ; The following instructions do a complementary access of their second + ; operand (z10 only): clrj, clgrj, clr, clgr (define_insn "*cmp_and_br_unsigned_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" *************** *** 1010,1015 **** --- 1065,1071 ---- } [(set_attr "op_type" "RIE") (set_attr "type" "branch") + (set_attr "z10prop" "z10_cobra,z10_super") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg *************** *** 1200,1206 **** && !FP_REG_P (operands[0])" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl")]) (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" --- 1256,1263 ---- && !FP_REG_P (operands[0])" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl") ! (set_attr "z10prop" "z10_super_A1")]) (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" *************** *** 1245,1251 **** *,*,*") (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, z10,*,*,*,*,*,longdisp,*,longdisp, ! z10,z10,*,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "register_operand" "") --- 1302,1336 ---- *,*,*") (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, z10,*,*,*,*,*,longdisp,*,longdisp, ! z10,z10,*,*,*,*,*") ! (set_attr "z10prop" "z10_fwd_A1, ! z10_fwd_E1, ! z10_fwd_E1, ! z10_fwd_E1, ! z10_fwd_E1, ! z10_fwd_A1, ! z10_fwd_E1, ! z10_fwd_E1, ! *, ! *, ! z10_fwd_A1, ! z10_fwd_A3, ! z10_fr_E1, ! z10_fwd_A3, ! z10_rec, ! *, ! *, ! *, ! *, ! *, ! z10_rec, ! z10_super, ! *, ! *, ! *, ! *, ! *") ! ]) (define_split [(set (match_operand:DI 0 "register_operand" "") *************** *** 1380,1386 **** la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") ! (set_attr "type" "la")]) (define_peephole2 [(parallel --- 1465,1472 ---- la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") ! (set_attr "type" "la") ! (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_peephole2 [(parallel *************** *** 1431,1437 **** && !FP_REG_P (operands[0])" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl")]) (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" --- 1517,1524 ---- && !FP_REG_P (operands[0])" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl") ! (set_attr "z10prop" "z10_super_A1")]) (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" *************** *** 1465,1474 **** #" [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,SS") ! (set_attr "type" "*,*,*,*,la,larl,lr,load,load,store,store, ! floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,larl,*,*,*") (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, ! *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*")]) (define_insn "*movsi_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") --- 1552,1605 ---- #" [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,SS") ! (set_attr "type" "*, ! *, ! *, ! *, ! la, ! larl, ! lr, ! load, ! load, ! store, ! store, ! floadsf, ! floadsf, ! floadsf, ! fstoresf, ! fstoresf, ! *, ! *, ! *, ! larl, ! *, ! *, ! *") (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, ! *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*") ! (set_attr "z10prop" "z10_fwd_A1, ! z10_fwd_E1, ! z10_fwd_E1, ! z10_fwd_A1, ! z10_fwd_A1, ! z10_fwd_A3, ! z10_fr_E1, ! z10_fwd_A3, ! z10_fwd_A3, ! z10_super, ! z10_rec, ! *, ! *, ! *, ! *, ! *, ! z10_super_E1, ! z10_super, ! *, ! z10_rec, ! z10_super, ! *, ! *")]) (define_insn "*movsi_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") *************** *** 1488,1494 **** lam\t%0,%0,%S1 #" [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") ! (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") --- 1619,1638 ---- lam\t%0,%0,%S1 #" [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") ! (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*") ! (set_attr "z10prop" "z10_fwd_A1, ! z10_fr_E1, ! z10_fwd_A3, ! z10_super, ! *, ! *, ! *, ! z10_super_E1, ! z10_super, ! *, ! *, ! *") ! ]) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") *************** *** 1509,1515 **** la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") ! (set_attr "type" "la")]) (define_peephole2 [(parallel --- 1653,1660 ---- la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") ! (set_attr "type" "la") ! (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_peephole2 [(parallel *************** *** 1544,1550 **** la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") ! (set_attr "type" "la")]) (define_insn_and_split "*la_31_and_cc" [(set (match_operand:SI 0 "register_operand" "=d") --- 1689,1696 ---- la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") ! (set_attr "type" "la") ! (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_insn_and_split "*la_31_and_cc" [(set (match_operand:SI 0 "register_operand" "=d") *************** *** 1569,1575 **** la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX") ! (set_attr "type" "la")]) ; ; movhi instruction pattern(s). --- 1715,1722 ---- la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX") ! (set_attr "type" "la") ! (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) ; ; movhi instruction pattern(s). *************** *** 1610,1616 **** #" [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,SS") (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*") ! (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*")]) (define_peephole2 [(set (match_operand:HI 0 "register_operand" "") --- 1757,1773 ---- #" [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,SS") (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*") ! (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*") ! (set_attr "z10prop" "z10_fr_E1, ! z10_fwd_A1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super, ! z10_rec, ! z10_rec, ! z10_super, ! *")]) (define_peephole2 [(set (match_operand:HI 0 "register_operand" "") *************** *** 1659,1665 **** mviy\t%S0,%b1 #" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") ! (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) (define_peephole2 [(set (match_operand:QI 0 "nonimmediate_operand" "") --- 1816,1831 ---- mviy\t%S0,%b1 #" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") ! (set_attr "type" "lr,*,*,*,store,store,store,store,*") ! (set_attr "z10prop" "z10_fr_E1, ! z10_fwd_A1, ! z10_super_E1, ! z10_super_E1, ! z10_super, ! z10_rec, ! z10_super, ! z10_super, ! *")]) (define_peephole2 [(set (match_operand:QI 0 "nonimmediate_operand" "") *************** *** 1682,1688 **** "@ ic\t%0,%1 icy\t%0,%1" ! [(set_attr "op_type" "RX,RXY")]) ; ; movstricthi instruction pattern(s). --- 1848,1855 ---- "@ ic\t%0,%1 icy\t%0,%1" ! [(set_attr "op_type" "RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super")]) ; ; movstricthi instruction pattern(s). *************** *** 1696,1702 **** "@ icm\t%0,3,%S1 icmy\t%0,3,%S1" ! [(set_attr "op_type" "RS,RSY")]) ; ; movstrictsi instruction pattern(s). --- 1863,1870 ---- "@ icm\t%0,3,%S1 icmy\t%0,3,%S1" ! [(set_attr "op_type" "RS,RSY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; ; movstrictsi instruction pattern(s). *************** *** 1712,1718 **** ly\t%0,%1 ear\t%0,%1" [(set_attr "op_type" "RR,RX,RXY,RRE") ! (set_attr "type" "lr,load,load,*")]) ; ; mov(tf|td) instruction pattern(s). --- 1880,1887 ---- ly\t%0,%1 ear\t%0,%1" [(set_attr "op_type" "RR,RX,RXY,RRE") ! (set_attr "type" "lr,load,load,*") ! (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) ; ; mov(tf|td) instruction pattern(s). *************** *** 1802,1808 **** (define_split [(set (match_operand:TD_TF 0 "register_operand" "") (match_operand:TD_TF 1 "memory_operand" ""))] ! "reload_completed && offsettable_memref_p (operands[1]) && FP_REG_P (operands[0])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] --- 1971,1977 ---- (define_split [(set (match_operand:TD_TF 0 "register_operand" "") (match_operand:TD_TF 1 "memory_operand" ""))] ! "reload_completed && offsettable_memref_p (operands[1]) && FP_REG_P (operands[0])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] *************** *** 1862,1868 **** #" [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, ! fstoredf,fstoredf,lr,load,store,*")]) (define_insn "*mov<mode>_64" [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT,?Q") --- 2031,2050 ---- #" [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, ! fstoredf,fstoredf,lr,load,store,*") ! (set_attr "z10prop" "*, ! *, ! *, ! *, ! *, ! *, ! *, ! *, ! z10_fr_E1, ! z10_fwd_A3, ! z10_rec, ! *") ! ]) (define_insn "*mov<mode>_64" [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT,?Q") *************** *** 1880,1887 **** stg\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") ! (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>, ! fstore<bfp>,fstore<bfp>,lr,load,store,*")]) (define_insn "*mov<mode>_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand" --- 2062,2079 ---- stg\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") ! (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, ! fstore<mode>,fstore<mode>,lr,load,store,*") ! (set_attr "z10prop" "*, ! *, ! *, ! *, ! *, ! *, ! z10_fr_E1, ! z10_fwd_A3, ! z10_rec, ! *")]) (define_insn "*mov<mode>_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand" *************** *** 1904,1911 **** # #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") ! (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>, ! fstore<bfp>,fstore<bfp>,lm,lm,stm,stm,*,*,*")]) (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") --- 2096,2103 ---- # #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") ! (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, ! fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*,*")]) (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") *************** *** 1972,1979 **** sty\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") ! (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>, ! fstore<bfp>,fstore<bfp>,lr,load,load,store,store,*")]) ; ; movcc instruction pattern --- 2164,2183 ---- sty\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") ! (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, ! fstore<mode>,fstore<mode>,lr,load,load,store,store,*") ! (set_attr "z10prop" "*, ! *, ! *, ! *, ! *, ! *, ! z10_fr_E1, ! z10_fwd_A3, ! z10_fwd_A3, ! z10_super, ! z10_rec, ! *")]) ; ; movcc instruction pattern *************** *** 1992,1998 **** l\t%1,%0 ly\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") ! (set_attr "type" "lr,*,*,store,store,load,load")]) ; ; Block move (MVC) patterns. --- 2196,2203 ---- l\t%1,%0 ly\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") ! (set_attr "type" "lr,*,*,store,store,load,load") ! (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")]) ; ; Block move (MVC) patterns. *************** *** 2032,2038 **** (use (match_operand 5 "const_int_operand" ""))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel --- 2237,2243 ---- (use (match_operand 5 "const_int_operand" ""))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel *************** *** 2338,2356 **** "clst\t%0,%1\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) ! ; ; movstr instruction pattern. ; (define_expand "movstr" [(set (reg:SI 0) (const_int 0)) ! (parallel [(clobber (match_dup 3)) (set (match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 2 "memory_operand" "")) (set (match_operand 0 "register_operand" "") ! (unspec [(match_dup 1) (match_dup 2) (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))])] --- 2543,2561 ---- "clst\t%0,%1\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) ! ; ; movstr instruction pattern. ; (define_expand "movstr" [(set (reg:SI 0) (const_int 0)) ! (parallel [(clobber (match_dup 3)) (set (match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 2 "memory_operand" "")) (set (match_operand 0 "register_operand" "") ! (unspec [(match_dup 1) (match_dup 2) (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))])] *************** *** 2371,2377 **** (set (mem:BLK (match_operand:P 1 "register_operand" "0")) (mem:BLK (match_operand:P 3 "register_operand" "2"))) (set (match_operand:P 0 "register_operand" "=d") ! (unspec [(mem:BLK (match_dup 1)) (mem:BLK (match_dup 3)) (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))] --- 2576,2582 ---- (set (mem:BLK (match_operand:P 1 "register_operand" "0")) (mem:BLK (match_operand:P 3 "register_operand" "2"))) (set (match_operand:P 0 "register_operand" "=d") ! (unspec [(mem:BLK (match_dup 1)) (mem:BLK (match_dup 3)) (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))] *************** *** 2379,2385 **** "mvst\t%1,%2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) ! ; ; movmemM instruction pattern(s). --- 2584,2590 ---- "mvst\t%1,%2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) ! ; ; movmemM instruction pattern(s). *************** *** 2467,2473 **** "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) (parallel ! [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) (set (match_dup 0) (match_dup 1)) (use (const_int 1))])] --- 2672,2678 ---- "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) (parallel ! [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) (set (match_dup 0) (match_dup 1)) (use (const_int 1))])] *************** *** 2528,2535 **** (define_expand "signbit<mode>2" [(set (reg:CCZ CC_REGNUM) ! (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") ! (match_dup 2)] UNSPEC_TDC_INSN)) (set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] --- 2733,2740 ---- (define_expand "signbit<mode>2" [(set (reg:CCZ CC_REGNUM) ! (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") ! (match_dup 2)] UNSPEC_TDC_INSN)) (set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] *************** *** 2540,2547 **** (define_expand "isinf<mode>2" [(set (reg:CCZ CC_REGNUM) ! (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") ! (match_dup 2)] UNSPEC_TDC_INSN)) (set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] --- 2745,2752 ---- (define_expand "isinf<mode>2" [(set (reg:CCZ CC_REGNUM) ! (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") ! (match_dup 2)] UNSPEC_TDC_INSN)) (set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] *************** *** 2553,2568 **** ; This insn is used to generate all variants of the Test Data Class ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand ; is the register to be tested and the second one is the bit mask ! ; specifying the required test(s). ; (define_insn "*TDC_insn_<mode>" [(set (reg:CCZ CC_REGNUM) ! (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] "TARGET_HARD_FLOAT" "t<_d>c<xde><bt>\t%0,%1" [(set_attr "op_type" "RXE") ! (set_attr "type" "fsimp<bfp>")]) (define_insn_and_split "*ccz_to_int" [(set (match_operand:SI 0 "register_operand" "=d") --- 2758,2773 ---- ; This insn is used to generate all variants of the Test Data Class ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand ; is the register to be tested and the second one is the bit mask ! ; specifying the required test(s). ; (define_insn "*TDC_insn_<mode>" [(set (reg:CCZ CC_REGNUM) ! (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] "TARGET_HARD_FLOAT" "t<_d>c<xde><bt>\t%0,%1" [(set_attr "op_type" "RXE") ! (set_attr "type" "fsimp<mode>")]) (define_insn_and_split "*ccz_to_int" [(set (match_operand:SI 0 "register_operand" "=d") *************** *** 2669,2682 **** "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 2) (label_ref (match_dup 3))) (parallel ! [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) (label_ref (match_dup 3))] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) (clobber (reg:CC CC_REGNUM))])] "operands[3] = gen_label_rtx ();") ! ; Initialize a block of arbitrary length with (operands[2] % 256). (define_expand "setmem_long" [(parallel --- 2874,2887 ---- "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 2) (label_ref (match_dup 3))) (parallel ! [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) (label_ref (match_dup 3))] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) (clobber (reg:CC CC_REGNUM))])] "operands[3] = gen_label_rtx ();") ! ; Initialize a block of arbitrary length with (operands[2] % 256). (define_expand "setmem_long" [(parallel *************** *** 2823,2829 **** "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) (parallel ! [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] --- 3028,3034 ---- "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) (parallel ! [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] *************** *** 2928,2934 **** (define_insn_and_split "*cmpint_sign_cc" [(set (reg CC_REGNUM) ! (compare (ashiftrt:DI (ashift:DI (subreg:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CCU_TO_INT) 0) (const_int 32)) (const_int 32)) --- 3133,3139 ---- (define_insn_and_split "*cmpint_sign_cc" [(set (reg CC_REGNUM) ! (compare (ashiftrt:DI (ashift:DI (subreg:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CCU_TO_INT) 0) (const_int 32)) (const_int 32)) *************** *** 2962,2968 **** "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" ! [(set_attr "op_type" "RS,RSY")]) (define_insn "*sethighpartdi_64" [(set (match_operand:DI 0 "register_operand" "=d") --- 3167,3174 ---- "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" ! [(set_attr "op_type" "RS,RSY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*sethighpartdi_64" [(set (match_operand:DI 0 "register_operand" "=d") *************** *** 2982,2988 **** "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" ! [(set_attr "op_type" "RS,RSY")]) (define_insn_and_split "*extzv<mode>" [(set (match_operand:GPR 0 "register_operand" "=d") --- 3188,3196 ---- "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" ! [(set_attr "op_type" "RS,RSY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ! (define_insn_and_split "*extzv<mode>" [(set (match_operand:GPR 0 "register_operand" "=d") *************** *** 3073,3079 **** return "risbg\t%0,%3,%b2,%b1,%b4"; } ! [(set_attr "op_type" "RIE")]) ; and op1 with a mask being 1 for the selected bits and 0 for the rest ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest --- 3281,3288 ---- return "risbg\t%0,%3,%b2,%b1,%b4"; } ! [(set_attr "op_type" "RIE") ! (set_attr "z10prop" "z10_super_E1")]) ; and op1 with a mask being 1 for the selected bits and 0 for the rest ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest *************** *** 3102,3108 **** return "risbg\t%0,%1,%b5,%b6,%b7"; } ! [(set_attr "op_type" "RIE")]) ; and op1 with a mask being 1 for the selected bits and 0 for the rest (define_insn "*insv<mode>_or_z10_noshift" --- 3311,3318 ---- return "risbg\t%0,%1,%b5,%b6,%b7"; } ! [(set_attr "op_type" "RIE") ! (set_attr "z10prop" "z10_super_E1")]) ; and op1 with a mask being 1 for the selected bits and 0 for the rest (define_insn "*insv<mode>_or_z10_noshift" *************** *** 3141,3150 **** int size = INTVAL (operands[1]) / BITS_PER_UNIT; operands[1] = GEN_INT ((1ul << size) - 1); ! return (which_alternative == 0) ? "stcm\t%2,%1,%S0" : "stcmy\t%2,%1,%S0"; } ! [(set_attr "op_type" "RS,RSY")]) (define_insn "*insvdi_mem_reghigh" [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") --- 3351,3361 ---- int size = INTVAL (operands[1]) / BITS_PER_UNIT; operands[1] = GEN_INT ((1ul << size) - 1); ! return (which_alternative == 0) ? "stcm\t%2,%1,%S0" : "stcmy\t%2,%1,%S0"; } ! [(set_attr "op_type" "RS,RSY") ! (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*insvdi_mem_reghigh" [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") *************** *** 3162,3168 **** operands[1] = GEN_INT ((1ul << size) - 1); return "stcmh\t%2,%1,%S0"; } ! [(set_attr "op_type" "RSY")]) (define_insn "*insv<mode>_reg_imm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") --- 3373,3380 ---- operands[1] = GEN_INT ((1ul << size) - 1); return "stcmh\t%2,%1,%S0"; } ! [(set_attr "op_type" "RSY") ! (set_attr "z10prop" "z10_super")]) (define_insn "*insv<mode>_reg_imm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") *************** *** 3183,3189 **** default: gcc_unreachable(); } } ! [(set_attr "op_type" "RI")]) (define_insn "*insv<mode>_reg_extimm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") --- 3395,3403 ---- default: gcc_unreachable(); } } ! [(set_attr "op_type" "RI") ! (set_attr "z10prop" "z10_super_E1")]) ! (define_insn "*insv<mode>_reg_extimm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") *************** *** 3202,3208 **** default: gcc_unreachable(); } } ! [(set_attr "op_type" "RIL")]) ; ; extendsidi2 instruction pattern(s). --- 3416,3424 ---- default: gcc_unreachable(); } } ! [(set_attr "op_type" "RIL") ! (set_attr "z10prop" "z10_fwd_E1")]) ! ; ; extendsidi2 instruction pattern(s). *************** *** 3233,3239 **** lgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "*,*,z10")]) ; ; extend(hi|qi)(si|di)2 instruction pattern(s). --- 3449,3456 ---- lgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "*,*,z10") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; ; extend(hi|qi)(si|di)2 instruction pattern(s). *************** *** 3277,3290 **** lghrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "extimm,extimm,z10")]) (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] "TARGET_64BIT" "lgh\t%0,%1" ! [(set_attr "op_type" "RXY")]) ; ; extendhisi2 instruction pattern(s). --- 3494,3509 ---- lghrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "extimm,extimm,z10") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] "TARGET_64BIT" "lgh\t%0,%1" ! [(set_attr "op_type" "RXY") ! (set_attr "z10prop" "z10_super_E1")]) ; ; extendhisi2 instruction pattern(s). *************** *** 3301,3307 **** lhrl\t%0,%1" [(set_attr "op_type" "RRE,RX,RXY,RIL") (set_attr "type" "*,*,*,larl") ! (set_attr "cpu_facility" "extimm,extimm,extimm,z10")]) (define_insn "*extendhisi2" [(set (match_operand:SI 0 "register_operand" "=d,d") --- 3520,3527 ---- lhrl\t%0,%1" [(set_attr "op_type" "RRE,RX,RXY,RIL") (set_attr "type" "*,*,*,larl") ! (set_attr "cpu_facility" "extimm,extimm,extimm,z10") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*extendhisi2" [(set (match_operand:SI 0 "register_operand" "=d,d") *************** *** 3310,3316 **** "@ lh\t%0,%1 lhy\t%0,%1" ! [(set_attr "op_type" "RX,RXY")]) ; ; extendqi(si|di)2 instruction pattern(s). --- 3530,3537 ---- "@ lh\t%0,%1 lhy\t%0,%1" ! [(set_attr "op_type" "RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; ; extendqi(si|di)2 instruction pattern(s). *************** *** 3324,3330 **** "@ l<g>br\t%0,%1 l<g>b\t%0,%1" ! [(set_attr "op_type" "RRE,RXY")]) ; lb, lgb (define_insn "*extendqi<mode>2" --- 3545,3552 ---- "@ l<g>br\t%0,%1 l<g>b\t%0,%1" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; lb, lgb (define_insn "*extendqi<mode>2" *************** *** 3332,3338 **** (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "l<g>b\t%0,%1" ! [(set_attr "op_type" "RXY")]) (define_insn_and_split "*extendqi<mode>2_short_displ" [(set (match_operand:GPR 0 "register_operand" "=d") --- 3554,3561 ---- (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "l<g>b\t%0,%1" ! [(set_attr "op_type" "RXY") ! (set_attr "z10prop" "z10_super_E1")]) (define_insn_and_split "*extendqi<mode>2_short_displ" [(set (match_operand:GPR 0 "register_operand" "=d") *************** *** 3382,3388 **** llgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "*,*,z10")]) ; ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). --- 3605,3612 ---- llgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "*,*,z10") ! (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) ; ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). *************** *** 3394,3400 **** (const_int 2147483647)))] "TARGET_64BIT" "llgt\t%0,%1" ! [(set_attr "op_type" "RXE")]) (define_insn_and_split "*llgt_sidi_split" [(set (match_operand:DI 0 "register_operand" "=d") --- 3618,3625 ---- (const_int 2147483647)))] "TARGET_64BIT" "llgt\t%0,%1" ! [(set_attr "op_type" "RXE") ! (set_attr "z10prop" "z10_super_E1")]) (define_insn_and_split "*llgt_sidi_split" [(set (match_operand:DI 0 "register_operand" "=d") *************** *** 3417,3423 **** "@ llgtr\t%0,%1 llgt\t%0,%1" ! [(set_attr "op_type" "RRE,RXE")]) (define_insn "*llgt_didi" [(set (match_operand:DI 0 "register_operand" "=d,d") --- 3642,3649 ---- "@ llgtr\t%0,%1 llgt\t%0,%1" ! [(set_attr "op_type" "RRE,RXE") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*llgt_didi" [(set (match_operand:DI 0 "register_operand" "=d,d") *************** *** 3427,3433 **** "@ llgtr\t%0,%1 llgt\t%0,%N1" ! [(set_attr "op_type" "RRE,RXE")]) (define_split [(set (match_operand:GPR 0 "register_operand" "") --- 3653,3660 ---- "@ llgtr\t%0,%1 llgt\t%0,%N1" ! [(set_attr "op_type" "RRE,RXE") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_split [(set (match_operand:GPR 0 "register_operand" "") *************** *** 3458,3464 **** } else if (!TARGET_EXTIMM) { ! rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - GET_MODE_BITSIZE(<MODE>mode)); operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); --- 3685,3691 ---- } else if (!TARGET_EXTIMM) { ! rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - GET_MODE_BITSIZE(<MODE>mode)); operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); *************** *** 3475,3481 **** if (!TARGET_EXTIMM) { operands[1] = gen_lowpart (SImode, operands[1]); ! emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); DONE; } --- 3702,3708 ---- if (!TARGET_EXTIMM) { operands[1] = gen_lowpart (SImode, operands[1]); ! emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); DONE; } *************** *** 3492,3498 **** ll<g>hrl\t%0,%1" [(set_attr "op_type" "RXY,RRE,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "*,*,z10")]) ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" --- 3719,3726 ---- ll<g>hrl\t%0,%1" [(set_attr "op_type" "RXY,RRE,RIL") (set_attr "type" "*,*,larl") ! (set_attr "cpu_facility" "*,*,z10") ! (set_attr "z10prop" "z10_fwd_A3")]) ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" *************** *** 3502,3508 **** "@ ll<g><hc>r\t%0,%1 ll<g><hc>\t%0,%1" ! [(set_attr "op_type" "RRE,RXY")]) ; llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2" --- 3730,3737 ---- "@ ll<g><hc>r\t%0,%1 ll<g><hc>\t%0,%1" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) ; llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2" *************** *** 3510,3516 **** (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llg<hc>\t%0,%1" ! [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") --- 3739,3746 ---- (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llg<hc>\t%0,%1" ! [(set_attr "op_type" "RXY") ! (set_attr "z10prop" "z10_fwd_A3")]) (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") *************** *** 3554,3560 **** (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llgc\t%0,%1" ! [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") --- 3784,3791 ---- (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llgc\t%0,%1" ! [(set_attr "op_type" "RXY") ! (set_attr "z10prop" "z10_fwd_A3")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") *************** *** 3575,3581 **** [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) (clobber (match_scratch:TD 2 "=f"))])] ! "TARGET_HARD_FLOAT && TARGET_HARD_DFP" { rtx label1 = gen_label_rtx (); --- 3806,3812 ---- [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) (clobber (match_scratch:TD 2 "=f"))])] ! "TARGET_HARD_FLOAT && TARGET_HARD_DFP" { rtx label1 = gen_label_rtx (); *************** *** 3587,3593 **** decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ /* 2^63 can't be represented as 64bit DFP number with full precision. The ! solution is doing the check and the subtraction in TD mode and using a TD -> DI convert afterwards. */ emit_insn (gen_extendddtd2 (temp, operands[1])); temp = force_reg (TDmode, temp); --- 3818,3824 ---- decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ /* 2^63 can't be represented as 64bit DFP number with full precision. The ! solution is doing the check and the subtraction in TD mode and using a TD -> DI convert afterwards. */ emit_insn (gen_extendddtd2 (temp, operands[1])); temp = force_reg (TDmode, temp); *************** *** 3614,3624 **** rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (TDmode); REAL_VALUE_TYPE cmp, sub; ! operands[1] = force_reg (TDmode, operands[1]); decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ ! emit_insn (gen_cmptd (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); emit_jump_insn (gen_blt (label1)); --- 3845,3855 ---- rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (TDmode); REAL_VALUE_TYPE cmp, sub; ! operands[1] = force_reg (TDmode, operands[1]); decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ ! emit_insn (gen_cmptd (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); emit_jump_insn (gen_blt (label1)); *************** *** 3634,3640 **** }) ; ! ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 ; instruction pattern(s). ; --- 3865,3871 ---- }) ; ! ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 ; instruction pattern(s). ; *************** *** 3647,3657 **** rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (<BFP:MODE>mode); REAL_VALUE_TYPE cmp, sub; ! operands[1] = force_reg (<BFP:MODE>mode, operands[1]); real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); ! emit_insn (gen_cmp<BFP:mode> (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode))); emit_jump_insn (gen_blt (label1)); --- 3878,3888 ---- rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (<BFP:MODE>mode); REAL_VALUE_TYPE cmp, sub; ! operands[1] = force_reg (<BFP:MODE>mode, operands[1]); real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); ! emit_insn (gen_cmp<BFP:mode> (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode))); emit_jump_insn (gen_blt (label1)); *************** *** 3714,3720 **** "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP" "cg<DFP:xde>tr\t%0,%h2,%1" [(set_attr "op_type" "RRF") ! (set_attr "type" "ftoi")]) ; --- 3945,3951 ---- "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP" "cg<DFP:xde>tr\t%0,%h2,%1" [(set_attr "op_type" "RRF") ! (set_attr "type" "ftoidfp")]) ; *************** *** 3741,3747 **** "TARGET_64BIT && TARGET_HARD_FLOAT" "c<xde>g<bt>r\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "itof" )]) ; cxfbr, cdfbr, cefbr (define_insn "floatsi<mode>2" --- 3972,3978 ---- "TARGET_64BIT && TARGET_HARD_FLOAT" "c<xde>g<bt>r\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "itof<mode>" )]) ; cxfbr, cdfbr, cefbr (define_insn "floatsi<mode>2" *************** *** 3750,3756 **** "TARGET_HARD_FLOAT" "c<xde>fbr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "itof" )]) ; --- 3981,3987 ---- "TARGET_HARD_FLOAT" "c<xde>fbr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "itof<mode>" )]) ; *************** *** 3777,3783 **** "TARGET_HARD_FLOAT" "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" [(set_attr "length" "6") ! (set_attr "type" "ftrunctf")]) ; ; trunctddd2 and truncddsd2 instruction pattern(s). --- 4008,4014 ---- "TARGET_HARD_FLOAT" "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" [(set_attr "length" "6") ! (set_attr "type" "ftrunctf")]) ; ; trunctddd2 and truncddsd2 instruction pattern(s). *************** *** 3790,3796 **** "TARGET_HARD_FLOAT && TARGET_HARD_DFP" "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" [(set_attr "length" "6") ! (set_attr "type" "ftrunctf")]) (define_insn "truncddsd2" [(set (match_operand:SD 0 "register_operand" "=f") --- 4021,4027 ---- "TARGET_HARD_FLOAT && TARGET_HARD_DFP" "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" [(set_attr "length" "6") ! (set_attr "type" "ftruncdd")]) (define_insn "truncddsd2" [(set (match_operand:SD 0 "register_operand" "=f") *************** *** 3798,3804 **** "TARGET_HARD_FLOAT && TARGET_HARD_DFP" "ledtr\t%0,0,%1,0" [(set_attr "op_type" "RRF") ! (set_attr "type" "fsimptf")]) ; ; extend(sf|df)(df|tf)2 instruction pattern(s). --- 4029,4035 ---- "TARGET_HARD_FLOAT && TARGET_HARD_DFP" "ledtr\t%0,0,%1,0" [(set_attr "op_type" "RRF") ! (set_attr "type" "ftruncsd")]) ; ; extend(sf|df)(df|tf)2 instruction pattern(s). *************** *** 4035,4041 **** "@ algfr\t%0,%2 algf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cconly" [(set (reg CC_REGNUM) --- 4266,4273 ---- "@ algfr\t%0,%2 algf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*adddi3_zero_cconly" [(set (reg CC_REGNUM) *************** *** 4047,4053 **** "@ algfr\t%0,%2 algf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") --- 4279,4286 ---- "@ algfr\t%0,%2 algf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*adddi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") *************** *** 4058,4064 **** "@ algfr\t%0,%2 algf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn_and_split "*adddi3_31z" [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") --- 4291,4298 ---- "@ algfr\t%0,%2 algf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn_and_split "*adddi3_31z" [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") *************** *** 4161,4167 **** a<y>\t%0,%2 a<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry1_cc" --- 4395,4408 ---- a<y>\t%0,%2 a<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") ! (set_attr "z10prop" "z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry1_cc" *************** *** 4180,4186 **** al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry1_cconly" --- 4421,4433 ---- al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") ! (set_attr "z10prop" "z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry1_cconly" *************** *** 4194,4200 **** al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry2_cc" --- 4441,4448 ---- al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry2_cc" *************** *** 4213,4219 **** al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry2_cconly" --- 4461,4473 ---- al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") ! (set_attr "z10prop" "z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry2_cconly" *************** *** 4227,4233 **** al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_cc" --- 4481,4488 ---- al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_cc" *************** *** 4246,4252 **** al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly" --- 4501,4513 ---- al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") ! (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") ! (set_attr "z10prop" "z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly" *************** *** 4260,4266 **** al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly2" --- 4521,4528 ---- al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly2" *************** *** 4273,4279 **** al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add<mode>3_imm_cc" --- 4535,4542 ---- al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add<mode>3_imm_cc" *************** *** 4293,4299 **** a<g>fi\t%0,%2 a<g>si\t%0,%c2" [(set_attr "op_type" "RI,RIL,SIY") ! (set_attr "cpu_facility" "*,extimm,z10")]) ; ; add(tf|df|sf|td|dd)3 instruction pattern(s). --- 4556,4563 ---- a<g>fi\t%0,%2 a<g>si\t%0,%c2" [(set_attr "op_type" "RI,RIL,SIY") ! (set_attr "cpu_facility" "*,extimm,z10") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; ; add(tf|df|sf|td|dd)3 instruction pattern(s). *************** *** 4310,4316 **** a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<bfp>")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add<mode>3_cc" --- 4574,4580 ---- a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<mode>")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add<mode>3_cc" *************** *** 4325,4331 **** a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<bfp>")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add<mode>3_cconly" --- 4589,4595 ---- a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<mode>")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add<mode>3_cconly" *************** *** 4339,4345 **** a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<bfp>")]) ;; --- 4603,4609 ---- a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<mode>")]) ;; *************** *** 4396,4402 **** "@ sgfr\t%0,%2 sgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cc" [(set (reg CC_REGNUM) --- 4660,4667 ---- "@ sgfr\t%0,%2 sgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_c,*")]) (define_insn "*subdi3_zero_cc" [(set (reg CC_REGNUM) *************** *** 4409,4415 **** "@ slgfr\t%0,%2 slgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cconly" [(set (reg CC_REGNUM) --- 4674,4681 ---- "@ slgfr\t%0,%2 slgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) (define_insn "*subdi3_zero_cconly" [(set (reg CC_REGNUM) *************** *** 4421,4427 **** "@ slgfr\t%0,%2 slgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") --- 4687,4694 ---- "@ slgfr\t%0,%2 slgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) (define_insn "*subdi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") *************** *** 4432,4438 **** "@ slgfr\t%0,%2 slgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn_and_split "*subdi3_31z" [(set (match_operand:DI 0 "register_operand" "=&d") --- 4699,4706 ---- "@ slgfr\t%0,%2 slgf\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) (define_insn_and_split "*subdi3_31z" [(set (match_operand:DI 0 "register_operand" "=&d") *************** *** 4529,4535 **** s<g>r\t%0,%2 s<g>\t%0,%2 s<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_borrow_cc" --- 4797,4804 ---- s<g>r\t%0,%2 s<g>\t%0,%2 s<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_borrow_cc" *************** *** 4544,4550 **** sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_borrow_cconly" --- 4813,4820 ---- sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_borrow_cconly" *************** *** 4558,4564 **** sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cc" --- 4828,4835 ---- sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cc" *************** *** 4573,4579 **** sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cc2" --- 4844,4851 ---- sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cc2" *************** *** 4587,4593 **** sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cconly" --- 4859,4866 ---- sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cconly" *************** *** 4601,4607 **** sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cconly2" --- 4874,4882 ---- sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ! ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cconly2" *************** *** 4614,4620 **** sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) ; ; sub(tf|df|sf|td|dd)3 instruction pattern(s). --- 4889,4897 ---- sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" ! [(set_attr "op_type" "RR<E>,RX<Y>,RXY") ! (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ! ; ; sub(tf|df|sf|td|dd)3 instruction pattern(s). *************** *** 4631,4637 **** s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<bfp>")]) ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub<mode>3_cc" --- 4908,4914 ---- s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<mode>")]) ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub<mode>3_cc" *************** *** 4646,4652 **** s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<bfp>")]) ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub<mode>3_cconly" --- 4923,4929 ---- s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<mode>")]) ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub<mode>3_cconly" *************** *** 4660,4666 **** s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<bfp>")]) ;; --- 4937,4943 ---- s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fsimp<mode>")]) ;; *************** *** 4783,4789 **** "@ slb<g>r\t%0,%2 slb<g>\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) ; slbr, slb, slbgr, slbg (define_insn "*sub<mode>3_slb" --- 5060,5067 ---- "@ slb<g>r\t%0,%2 slb<g>\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_c,*")]) ; slbr, slb, slbgr, slbg (define_insn "*sub<mode>3_slb" *************** *** 4796,4802 **** "@ slb<g>r\t%0,%2 slb<g>\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_expand "add<mode>cc" [(match_operand:GPR 0 "register_operand" "") --- 5074,5081 ---- "@ slb<g>r\t%0,%2 slb<g>\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_c,*")]) (define_expand "add<mode>cc" [(match_operand:GPR 0 "register_operand" "") *************** *** 4804,4812 **** (match_operand:GPR 2 "register_operand" "") (match_operand:GPR 3 "const_int_operand" "")] "TARGET_CPU_ZARCH" ! "if (!s390_expand_addcc (GET_CODE (operands[1]), ! s390_compare_op0, s390_compare_op1, ! operands[0], operands[2], operands[3])) FAIL; DONE;") ; --- 5083,5091 ---- (match_operand:GPR 2 "register_operand" "") (match_operand:GPR 3 "const_int_operand" "")] "TARGET_CPU_ZARCH" ! "if (!s390_expand_addcc (GET_CODE (operands[1]), ! s390_compare_op0, s390_compare_op1, ! operands[0], operands[2], operands[3])) FAIL; DONE;") ; *************** *** 4862,4868 **** [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) (clobber (reg:CC CC_REGNUM))])] "" ! { if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) FAIL; operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); --- 5141,5147 ---- [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) (clobber (reg:CC CC_REGNUM))])] "" ! { if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) FAIL; operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); *************** *** 4871,4877 **** (define_insn_and_split "*sne" [(set (match_operand:SI 0 "register_operand" "=d") ! (ne:SI (match_operand:CCZ1 1 "register_operand" "0") (const_int 0))) (clobber (reg:CC CC_REGNUM))] "" --- 5150,5156 ---- (define_insn_and_split "*sne" [(set (match_operand:SI 0 "register_operand" "=d") ! (ne:SI (match_operand:CCZ1 1 "register_operand" "0") (const_int 0))) (clobber (reg:CC CC_REGNUM))] "" *************** *** 4986,4992 **** ; mul(tf|df|sf|td|dd)3 instruction pattern(s). ; ! ; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr (define_insn "mul<mode>3" [(set (match_operand:FP 0 "register_operand" "=f,f") (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") --- 5265,5271 ---- ; mul(tf|df|sf|td|dd)3 instruction pattern(s). ; ! ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr (define_insn "mul<mode>3" [(set (match_operand:FP 0 "register_operand" "=f,f") (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") *************** *** 4996,5004 **** m<xdee><bt>r\t%0,<op1>%2 m<xdee>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fmul<bfp>")]) ! ; maxbr, madbr, maebr, maxb, madb, maeb (define_insn "*fmadd<mode>" [(set (match_operand:DSF 0 "register_operand" "=f,f") (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") --- 5275,5283 ---- m<xdee><bt>r\t%0,<op1>%2 m<xdee>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fmul<mode>")]) ! ; madbr, maebr, maxb, madb, maeb (define_insn "*fmadd<mode>" [(set (match_operand:DSF 0 "register_operand" "=f,f") (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") *************** *** 5456,5462 **** d<xde><bt>r\t%0,<op1>%2 d<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fdiv<bfp>")]) ;; --- 5735,5741 ---- d<xde><bt>r\t%0,<op1>%2 d<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") ! (set_attr "type" "fdiv<mode>")]) ;; *************** *** 5486,5492 **** "@ ngr\t%0,%2 ng\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3_cconly" [(set (reg CC_REGNUM) --- 5765,5772 ---- "@ ngr\t%0,%2 ng\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*anddi3_cconly" [(set (reg CC_REGNUM) *************** *** 5500,5506 **** "@ ngr\t%0,%2 ng\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") --- 5780,5787 ---- "@ ngr\t%0,%2 ng\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1, z10_super_E1")]) (define_insn "*anddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") *************** *** 5524,5530 **** # #" [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") ! (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "s_operand" "") --- 5805,5823 ---- # #" [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") ! (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") ! (set_attr "z10prop" "*, ! *, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! *, ! *")]) (define_split [(set (match_operand:DI 0 "s_operand" "") *************** *** 5554,5560 **** nr\t%0,%2 n\t%0,%2 ny\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY")]) (define_insn "*andsi3_cconly" [(set (reg CC_REGNUM) --- 5847,5854 ---- nr\t%0,%2 n\t%0,%2 ny\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*andsi3_cconly" [(set (reg CC_REGNUM) *************** *** 5570,5576 **** nr\t%0,%2 n\t%0,%2 ny\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY")]) (define_insn "*andsi3_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") --- 5864,5871 ---- nr\t%0,%2 n\t%0,%2 ny\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*andsi3_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") *************** *** 5591,5597 **** ny\t%0,%2 # #" ! [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")]) (define_insn "*andsi3_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") --- 5886,5902 ---- ny\t%0,%2 # #" ! [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") ! (set_attr "z10prop" "*, ! *, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! *, ! *")]) (define_insn "*andsi3_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") *************** *** 5604,5610 **** n\t%0,%2 # #" ! [(set_attr "op_type" "RR,RX,SI,SS")]) (define_split [(set (match_operand:SI 0 "s_operand" "") --- 5909,5917 ---- n\t%0,%2 # #" ! [(set_attr "op_type" "RR,RX,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) ! (define_split [(set (match_operand:SI 0 "s_operand" "") *************** *** 5631,5637 **** nill\t%0,%x2 # #" ! [(set_attr "op_type" "RR,RI,SI,SS")]) (define_insn "*andhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") --- 5938,5946 ---- nill\t%0,%x2 # #" ! [(set_attr "op_type" "RR,RI,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") ! ]) (define_insn "*andhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") *************** *** 5643,5649 **** nr\t%0,%2 # #" ! [(set_attr "op_type" "RR,SI,SS")]) (define_split [(set (match_operand:HI 0 "s_operand" "") --- 5952,5960 ---- nr\t%0,%2 # #" ! [(set_attr "op_type" "RR,SI,SS") ! (set_attr "z10prop" "z10_super_E1,*,*") ! ]) (define_split [(set (match_operand:HI 0 "s_operand" "") *************** *** 5671,5677 **** ni\t%S0,%b2 niy\t%S0,%b2 #" ! [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) (define_insn "*andqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") --- 5982,5989 ---- ni\t%S0,%b2 niy\t%S0,%b2 #" ! [(set_attr "op_type" "RR,RI,SI,SIY,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (define_insn "*andqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") *************** *** 5683,5689 **** nr\t%0,%2 ni\t%S0,%b2 #" ! [(set_attr "op_type" "RR,SI,SS")]) ; ; Block and (NC) patterns. --- 5995,6002 ---- nr\t%0,%2 ni\t%S0,%b2 #" ! [(set_attr "op_type" "RR,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super,*")]) ; ; Block and (NC) patterns. *************** *** 5732,5738 **** (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel --- 6045,6051 ---- (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel *************** *** 5771,5777 **** "@ ogr\t%0,%2 og\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3_cconly" [(set (reg CC_REGNUM) --- 6084,6091 ---- "@ ogr\t%0,%2 og\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*iordi3_cconly" [(set (reg CC_REGNUM) *************** *** 5783,5789 **** "@ ogr\t%0,%2 og\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") --- 6097,6104 ---- "@ ogr\t%0,%2 og\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*iordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") *************** *** 5804,5810 **** # #" [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") ! (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "s_operand" "") --- 6119,6135 ---- # #" [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") ! (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") ! (set_attr "z10prop" "z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! *, ! *")]) (define_split [(set (match_operand:DI 0 "s_operand" "") *************** *** 5833,5839 **** or\t%0,%2 o\t%0,%2 oy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY")]) (define_insn "*iorsi3_cconly" [(set (reg CC_REGNUM) --- 6158,6165 ---- or\t%0,%2 o\t%0,%2 oy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_cconly" [(set (reg CC_REGNUM) *************** *** 5847,5853 **** or\t%0,%2 o\t%0,%2 oy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY")]) (define_insn "*iorsi3_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") --- 6173,6180 ---- or\t%0,%2 o\t%0,%2 oy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") *************** *** 5864,5870 **** oy\t%0,%2 # #" ! [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")]) (define_insn "*iorsi3_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") --- 6191,6205 ---- oy\t%0,%2 # #" ! [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") ! (set_attr "z10prop" "z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! z10_super_E1, ! *, ! *")]) (define_insn "*iorsi3_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") *************** *** 5877,5883 **** o\t%0,%2 # #" ! [(set_attr "op_type" "RR,RX,SI,SS")]) (define_split [(set (match_operand:SI 0 "s_operand" "") --- 6212,6219 ---- o\t%0,%2 # #" ! [(set_attr "op_type" "RR,RX,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:SI 0 "s_operand" "") *************** *** 5904,5910 **** oill\t%0,%x2 # #" ! [(set_attr "op_type" "RR,RI,SI,SS")]) (define_insn "*iorhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") --- 6240,6247 ---- oill\t%0,%x2 # #" ! [(set_attr "op_type" "RR,RI,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (define_insn "*iorhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") *************** *** 5916,5922 **** or\t%0,%2 # #" ! [(set_attr "op_type" "RR,SI,SS")]) (define_split [(set (match_operand:HI 0 "s_operand" "") --- 6253,6260 ---- or\t%0,%2 # #" ! [(set_attr "op_type" "RR,SI,SS") ! (set_attr "z10prop" "z10_super_E1,*,*")]) (define_split [(set (match_operand:HI 0 "s_operand" "") *************** *** 5944,5950 **** oi\t%S0,%b2 oiy\t%S0,%b2 #" ! [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) (define_insn "*iorqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") --- 6282,6289 ---- oi\t%S0,%b2 oiy\t%S0,%b2 #" ! [(set_attr "op_type" "RR,RI,SI,SIY,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (define_insn "*iorqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") *************** *** 5956,5962 **** or\t%0,%2 oi\t%S0,%b2 #" ! [(set_attr "op_type" "RR,SI,SS")]) ; ; Block inclusive or (OC) patterns. --- 6295,6302 ---- or\t%0,%2 oi\t%S0,%b2 #" ! [(set_attr "op_type" "RR,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super,*")]) ; ; Block inclusive or (OC) patterns. *************** *** 6005,6011 **** (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel --- 6345,6351 ---- (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel *************** *** 6044,6050 **** "@ xgr\t%0,%2 xg\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*xordi3_cconly" [(set (reg CC_REGNUM) --- 6384,6391 ---- "@ xgr\t%0,%2 xg\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*xordi3_cconly" [(set (reg CC_REGNUM) *************** *** 6056,6062 **** "@ xgr\t%0,%2 xg\t%0,%2" ! [(set_attr "op_type" "RRE,RXY")]) (define_insn "*xordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") --- 6397,6404 ---- "@ xgr\t%0,%2 xg\t%0,%2" ! [(set_attr "op_type" "RRE,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*xordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") *************** *** 6072,6078 **** # #" [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") ! (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "s_operand" "") --- 6414,6421 ---- # #" [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") ! (set_attr "cpu_facility" "extimm,extimm,*,*,*,*") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:DI 0 "s_operand" "") *************** *** 6101,6107 **** xr\t%0,%2 x\t%0,%2 xy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY")]) (define_insn "*xorsi3_cconly" [(set (reg CC_REGNUM) --- 6444,6451 ---- xr\t%0,%2 x\t%0,%2 xy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*xorsi3_cconly" [(set (reg CC_REGNUM) *************** *** 6115,6121 **** xr\t%0,%2 x\t%0,%2 xy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY")]) (define_insn "*xorsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") --- 6459,6466 ---- xr\t%0,%2 x\t%0,%2 xy\t%0,%2" ! [(set_attr "op_type" "RIL,RR,RX,RXY") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*xorsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") *************** *** 6130,6136 **** xy\t%0,%2 # #" ! [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")]) (define_split [(set (match_operand:SI 0 "s_operand" "") --- 6475,6482 ---- xy\t%0,%2 # #" ! [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:SI 0 "s_operand" "") *************** *** 6157,6163 **** xr\t%0,%2 # #" ! [(set_attr "op_type" "RIL,RR,SI,SS")]) (define_split [(set (match_operand:HI 0 "s_operand" "") --- 6503,6510 ---- xr\t%0,%2 # #" ! [(set_attr "op_type" "RIL,RR,SI,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:HI 0 "s_operand" "") *************** *** 6185,6191 **** xi\t%S0,%b2 xiy\t%S0,%b2 #" ! [(set_attr "op_type" "RIL,RR,SI,SIY,SS")]) ; ; Block exclusive or (XC) patterns. --- 6532,6540 ---- xi\t%S0,%b2 xiy\t%S0,%b2 #" ! [(set_attr "op_type" "RIL,RR,SI,SIY,SS") ! (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) ! ; ; Block exclusive or (XC) patterns. *************** *** 6234,6240 **** (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel --- 6583,6589 ---- (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) ! && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel *************** *** 6306,6312 **** "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE")]) ! (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) --- 6655,6661 ---- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE")]) ! (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) *************** *** 6324,6330 **** (neg:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; lcr, lcgr (define_insn "*neg<mode>2_cconly" --- 6673,6680 ---- (neg:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_super_c_E1")]) ; lcr, lcgr (define_insn "*neg<mode>2_cconly" *************** *** 6334,6340 **** (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; lcr, lcgr (define_insn "*neg<mode>2" --- 6684,6691 ---- (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_super_c_E1")]) ; lcr, lcgr (define_insn "*neg<mode>2" *************** *** 6343,6349 **** (clobber (reg:CC CC_REGNUM))] "" "lc<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) (define_insn_and_split "*negdi2_31" [(set (match_operand:DI 0 "register_operand" "=d") --- 6694,6701 ---- (clobber (reg:CC CC_REGNUM))] "" "lc<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_super_c_E1")]) (define_insn_and_split "*negdi2_31" [(set (match_operand:DI 0 "register_operand" "=d") *************** *** 6415,6421 **** "TARGET_HARD_FLOAT && TARGET_DFP" "lcdfr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<bfp>")]) ; lcxbr, lcdbr, lcebr (define_insn "*neg<mode>2" --- 6767,6773 ---- "TARGET_HARD_FLOAT && TARGET_DFP" "lcdfr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<mode>")]) ; lcxbr, lcdbr, lcebr (define_insn "*neg<mode>2" *************** *** 6465,6473 **** (abs:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ! ; lpr, lpgr (define_insn "*abs<mode>2_cconly" [(set (reg CC_REGNUM) (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) --- 6817,6826 ---- (abs:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_c")]) ! ; lpr, lpgr (define_insn "*abs<mode>2_cconly" [(set (reg CC_REGNUM) (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) *************** *** 6475,6481 **** (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; lpr, lpgr (define_insn "abs<mode>2" --- 6828,6835 ---- (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_c")]) ; lpr, lpgr (define_insn "abs<mode>2" *************** *** 6484,6490 **** (clobber (reg:CC CC_REGNUM))] "" "lp<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; ; abs(df|sf)2 instruction pattern(s). --- 6838,6845 ---- (clobber (reg:CC CC_REGNUM))] "" "lp<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_c")]) ; ; abs(df|sf)2 instruction pattern(s). *************** *** 6528,6534 **** "TARGET_HARD_FLOAT && TARGET_DFP" "lpdfr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<bfp>")]) ; lpxbr, lpdbr, lpebr (define_insn "*abs<mode>2" --- 6883,6889 ---- "TARGET_HARD_FLOAT && TARGET_DFP" "lpdfr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<mode>")]) ; lpxbr, lpdbr, lpebr (define_insn "*abs<mode>2" *************** *** 6560,6566 **** "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" [(set_attr "op_type" "RRE")]) ! (define_insn "*negabsdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI --- 6915,6921 ---- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" [(set_attr "op_type" "RRE")]) ! (define_insn "*negabsdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI *************** *** 6579,6585 **** (neg:GPR (abs:GPR (match_dup 1))))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; lnr, lngr (define_insn "*negabs<mode>2_cconly" --- 6934,6941 ---- (neg:GPR (abs:GPR (match_dup 1))))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_c")]) ; lnr, lngr (define_insn "*negabs<mode>2_cconly" *************** *** 6589,6595 **** (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; lnr, lngr (define_insn "*negabs<mode>2" --- 6945,6952 ---- (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_c")]) ; lnr, lngr (define_insn "*negabs<mode>2" *************** *** 6598,6604 **** (clobber (reg:CC CC_REGNUM))] "" "ln<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>")]) ; ; Floating point --- 6955,6962 ---- (clobber (reg:CC CC_REGNUM))] "" "ln<g>r\t%0,%1" ! [(set_attr "op_type" "RR<E>") ! (set_attr "z10prop" "z10_c")]) ; ; Floating point *************** *** 6634,6640 **** "TARGET_HARD_FLOAT && TARGET_DFP" "lndfr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<bfp>")]) ; lnxbr, lndbr, lnebr (define_insn "*negabs<mode>2" --- 6992,6998 ---- "TARGET_HARD_FLOAT && TARGET_DFP" "lndfr\t%0,%1" [(set_attr "op_type" "RRE") ! (set_attr "type" "fsimp<mode>")]) ; lnxbr, lndbr, lnebr (define_insn "*negabs<mode>2" *************** *** 6654,6665 **** (define_insn "copysign<mode>3" [(set (match_operand:FP 0 "register_operand" "=f") (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") ! (match_operand:FP 2 "register_operand" "f")] UNSPEC_COPYSIGN))] "TARGET_HARD_FLOAT && TARGET_DFP" "cpsdr\t%0,%2,%1" [(set_attr "op_type" "RRF") ! (set_attr "type" "fsimp<bfp>")]) ;; ;;- Square root instructions. --- 7012,7023 ---- (define_insn "copysign<mode>3" [(set (match_operand:FP 0 "register_operand" "=f") (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") ! (match_operand:FP 2 "register_operand" "f")] UNSPEC_COPYSIGN))] "TARGET_HARD_FLOAT && TARGET_DFP" "cpsdr\t%0,%2,%1" [(set_attr "op_type" "RRF") ! (set_attr "type" "fsimp<mode>")]) ;; ;;- Square root instructions. *************** *** 6669,6675 **** ; sqrt(df|sf)2 instruction pattern(s). ; ! ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb (define_insn "sqrt<mode>2" [(set (match_operand:BFP 0 "register_operand" "=f,f") (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] --- 7027,7033 ---- ; sqrt(df|sf)2 instruction pattern(s). ; ! ; sqxbr, sqdbr, sqebr, sqdb, sqeb (define_insn "sqrt<mode>2" [(set (match_operand:BFP 0 "register_operand" "=f,f") (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] *************** *** 6716,6722 **** emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); ! insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); set_unique_reg_note (insn, REG_EQUAL, clz_equal); DONE; --- 7074,7080 ---- emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); ! insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); set_unique_reg_note (insn, REG_EQUAL, clz_equal); DONE; *************** *** 6725,6740 **** (define_insn "clztidi2" [(set (match_operand:TI 0 "register_operand" "=d") (ior:TI ! (ashift:TI ! (zero_extend:TI (xor:DI (match_operand:DI 1 "register_operand" "d") (lshiftrt (match_operand:DI 2 "const_int_operand" "") (subreg:SI (clz:DI (match_dup 1)) 4)))) ! (const_int 64)) (zero_extend:TI (clz:DI (match_dup 1))))) (clobber (reg:CC CC_REGNUM))] ! "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) == (unsigned HOST_WIDE_INT) 1 << 63 && TARGET_EXTIMM && TARGET_64BIT" "flogr\t%0,%1" --- 7083,7098 ---- (define_insn "clztidi2" [(set (match_operand:TI 0 "register_operand" "=d") (ior:TI ! (ashift:TI ! (zero_extend:TI (xor:DI (match_operand:DI 1 "register_operand" "d") (lshiftrt (match_operand:DI 2 "const_int_operand" "") (subreg:SI (clz:DI (match_dup 1)) 4)))) ! (const_int 64)) (zero_extend:TI (clz:DI (match_dup 1))))) (clobber (reg:CC CC_REGNUM))] ! "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) == (unsigned HOST_WIDE_INT) 1 << 63 && TARGET_EXTIMM && TARGET_64BIT" "flogr\t%0,%1" *************** *** 6757,6763 **** "TARGET_CPU_ZARCH" "rll<g>\t%0,%1,%Y2" [(set_attr "op_type" "RSE") ! (set_attr "atype" "reg")]) ; rll, rllg (define_insn "*rotl<mode>3_and" --- 7115,7122 ---- "TARGET_CPU_ZARCH" "rll<g>\t%0,%1,%Y2" [(set_attr "op_type" "RSE") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; rll, rllg (define_insn "*rotl<mode>3_and" *************** *** 6768,6774 **** "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" "rll<g>\t%0,%1,%Y2" [(set_attr "op_type" "RSE") ! (set_attr "atype" "reg")]) ;; --- 7127,7134 ---- "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" "rll<g>\t%0,%1,%Y2" [(set_attr "op_type" "RSE") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ;; *************** *** 6804,6810 **** "" "s<lr>l<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; sldl, srdl (define_insn "*<shift>di3_31_and" --- 7164,7171 ---- "" "s<lr>l<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; sldl, srdl (define_insn "*<shift>di3_31_and" *************** *** 6826,6832 **** "(INTVAL (operands[3]) & 63) == 63" "s<lr>l<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; ; ashr(di|si)3 instruction pattern(s). --- 7187,7194 ---- "(INTVAL (operands[3]) & 63) == 63" "s<lr>l<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; ; ashr(di|si)3 instruction pattern(s). *************** *** 6885,6891 **** "s390_match_ccmode(insn, CCSmode)" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; sra, srag (define_insn "*ashr<mode>3_cconly" --- 7247,7254 ---- "s390_match_ccmode(insn, CCSmode)" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3_cconly" *************** *** 6897,6903 **** "s390_match_ccmode(insn, CCSmode)" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; sra, srag (define_insn "*ashr<mode>3" --- 7260,7267 ---- "s390_match_ccmode(insn, CCSmode)" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3" *************** *** 6908,6914 **** "" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; shift pattern with implicit ANDs --- 7272,7279 ---- "" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; shift pattern with implicit ANDs *************** *** 6963,6969 **** "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; sra, srag (define_insn "*ashr<mode>3_cconly_and" --- 7328,7335 ---- "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3_cconly_and" *************** *** 6976,6982 **** "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ; sra, srag (define_insn "*ashr<mode>3_and" --- 7342,7349 ---- "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3_and" *************** *** 6988,6994 **** "(INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg")]) ;; --- 7355,7362 ---- "(INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") ! (set_attr "atype" "reg") ! (set_attr "z10prop" "z10_super_E1")]) ;; *************** *** 7148,7154 **** "" { if (operands[1] != const0_rtx) FAIL; ! operands[0] = s390_emit_compare (GET_CODE (operands[0]), s390_compare_op0, s390_compare_op1); }) --- 7516,7522 ---- "" { if (operands[1] != const0_rtx) FAIL; ! operands[0] = s390_emit_compare (GET_CODE (operands[0]), s390_compare_op0, s390_compare_op1); }) *************** *** 7171,7177 **** c<g>rt%C0\t%1,%2 c<g>it%C0\t%1,%h2" [(set_attr "op_type" "RRF,RIE") ! (set_attr "type" "branch")]) ; clrt, clgrt, clfit, clgit (define_insn "*cmp_and_trap_unsigned_int<mode>" --- 7539,7546 ---- c<g>rt%C0\t%1,%2 c<g>it%C0\t%1,%h2" [(set_attr "op_type" "RRF,RIE") ! (set_attr "type" "branch") ! (set_attr "z10prop" "z10_c,*")]) ; clrt, clgrt, clfit, clgit (define_insn "*cmp_and_trap_unsigned_int<mode>" *************** *** 7184,7190 **** cl<g>rt%C0\t%1,%2 cl<gf>it%C0\t%1,%x2" [(set_attr "op_type" "RRF,RIE") ! (set_attr "type" "branch")]) ;; ;;- Loop instructions. --- 7553,7560 ---- cl<g>rt%C0\t%1,%2 cl<gf>it%C0\t%1,%x2" [(set_attr "op_type" "RRF,RIE") ! (set_attr "type" "branch") ! (set_attr "z10prop" "z10_c,*")]) ;; ;;- Loop instructions. *************** *** 7246,7251 **** --- 7616,7624 ---- (pc)))] "" [(set_attr "op_type" "RI") + ; Strictly speaking, the z10 properties are valid for brct only, however, it does not + ; hurt us in the (rare) case of ahi. + (set_attr "z10prop" "z10_super") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) *************** *** 7285,7290 **** --- 7658,7666 ---- (pc)))] "" [(set_attr "op_type" "RI") + ; Strictly speaking, the z10 properties are valid for brct only, however, it does not + ; hurt us in the (rare) case of ahi. + (set_attr "z10prop" "z10_super") (set_attr "type" "branch") (set (attr "length") (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) *************** *** 7351,7356 **** --- 7727,7735 ---- (pc)))] "" [(set_attr "op_type" "RI") + ; Strictly speaking, the z10 properties are valid for brct only, however, it does not + ; hurt us in the (rare) case of ahi. + (set_attr "z10prop" "z10_super") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) *************** *** 7417,7423 **** (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") ! (set_attr "atype" "agen")]) ; ; casesi instruction pattern(s). --- 7796,7803 ---- (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") ! (set_attr "atype" "agen") ! (set_attr "z10prop" "z10_super")]) ; ; casesi instruction pattern(s). *************** *** 7760,7766 **** UNSPEC_TLS_LOAD))] "TARGET_64BIT" "lg\t%0,%1%J2" ! [(set_attr "op_type" "RXE")]) (define_insn "*tls_load_31" [(set (match_operand:SI 0 "register_operand" "=d,d") --- 8140,8147 ---- UNSPEC_TLS_LOAD))] "TARGET_64BIT" "lg\t%0,%1%J2" ! [(set_attr "op_type" "RXE") ! (set_attr "z10prop" "z10_fwd_A3")]) (define_insn "*tls_load_31" [(set (match_operand:SI 0 "register_operand" "=d,d") *************** *** 7771,7777 **** "@ l\t%0,%1%J2 ly\t%0,%1%J2" ! [(set_attr "op_type" "RX,RXY")]) (define_insn "*bras_tls" [(set (match_operand 0 "" "") --- 8152,8159 ---- "@ l\t%0,%1%J2 ly\t%0,%1%J2" ! [(set_attr "op_type" "RX,RXY") ! (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) (define_insn "*bras_tls" [(set (match_operand 0 "" "") *************** *** 7841,7846 **** --- 8223,8230 ---- "" "bcr\t15,0" [(set_attr "op_type" "RR")]) + ; Although bcr is superscalar on Z10, this variant will never become part of + ; an execution group. ; ; compare and swap patterns. *************** *** 7873,7879 **** (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))])] "" ! "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], operands[3]); DONE;") (define_expand "sync_compare_and_swap_cc<mode>" --- 8257,8263 ---- (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))])] "" ! "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], operands[3]); DONE;") (define_expand "sync_compare_and_swap_cc<mode>" *************** *** 7926,7932 **** UNSPECV_CAS)) (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))] ! "" "cs<g>\t%0,%3,%S1" [(set_attr "op_type" "RS<E>") (set_attr "type" "sem")]) --- 8310,8316 ---- UNSPECV_CAS)) (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))] ! "" "cs<g>\t%0,%3,%S1" [(set_attr "op_type" "RS<E>") (set_attr "type" "sem")]) *************** *** 7941,7947 **** (match_operand:HQI 1 "memory_operand") (match_operand:HQI 2 "general_operand")] "" ! "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], false); DONE;") (define_expand "sync_<atomic><mode>" --- 8325,8331 ---- (match_operand:HQI 1 "memory_operand") (match_operand:HQI 2 "general_operand")] "" ! "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], false); DONE;") (define_expand "sync_<atomic><mode>" *************** *** 7949,7955 **** (ATOMIC:HQI (match_dup 0) (match_operand:HQI 1 "general_operand")))] "" ! "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], operands[1], false); DONE;") (define_expand "sync_old_<atomic><mode>" --- 8333,8339 ---- (ATOMIC:HQI (match_dup 0) (match_operand:HQI 1 "general_operand")))] "" ! "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], operands[1], false); DONE;") (define_expand "sync_old_<atomic><mode>" *************** *** 7959,7974 **** (ATOMIC:HQI (match_dup 1) (match_operand:HQI 2 "general_operand")))] "" ! "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], operands[2], false); DONE;") (define_expand "sync_new_<atomic><mode>" [(set (match_operand:HQI 0 "register_operand") (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") ! (match_operand:HQI 2 "general_operand"))) (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] "" ! "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], operands[2], true); DONE;") ;; --- 8343,8358 ---- (ATOMIC:HQI (match_dup 1) (match_operand:HQI 2 "general_operand")))] "" ! "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], operands[2], false); DONE;") (define_expand "sync_new_<atomic><mode>" [(set (match_operand:HQI 0 "register_operand") (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") ! (match_operand:HQI 2 "general_operand"))) (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] "" ! "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], operands[2], true); DONE;") ;; *************** *** 8080,8086 **** if (TARGET_BACKCHAIN) temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); ! emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); --- 8464,8470 ---- if (TARGET_BACKCHAIN) temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); ! emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); *************** *** 8168,8174 **** "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl")]) (define_insn "main_pool" [(set (match_operand 0 "register_operand" "=a") --- 8552,8559 ---- "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl") ! (set_attr "z10prop" "z10_super_A1")]) (define_insn "main_pool" [(set (match_operand 0 "register_operand" "=a") *************** *** 8177,8183 **** { gcc_unreachable (); } ! [(set (attr "type") (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_string "larl") (const_string "la")))]) --- 8562,8568 ---- { gcc_unreachable (); } ! [(set (attr "type") (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_string "larl") (const_string "la")))]) *************** *** 8195,8201 **** "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl")]) (define_insn "pool" [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] --- 8580,8587 ---- "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") ! (set_attr "type" "larl") ! (set_attr "z10prop" "z10_super_A1")]) (define_insn "pool" [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] *************** *** 8356,8361 **** instruction. */ return ""; ! ! } [(set_attr "type" "load,larl") ! (set_attr "op_type" "RXY,RIL")]) --- 8742,8748 ---- instruction. */ return ""; ! } ! [(set_attr "type" "load,larl") ! (set_attr "op_type" "RXY,RIL") ! (set_attr "z10prop" "z10_super")]) Index: gcc/config/s390/s390.c =================================================================== *** gcc/config/s390/s390.c.orig 2008-08-15 09:08:50.000000000 +0200 --- gcc/config/s390/s390.c 2008-08-15 09:09:26.000000000 +0200 *************** struct processor_costs z9_109_cost = *** 192,224 **** static const struct processor_costs z10_cost = { ! COSTS_N_INSNS (4), /* M */ ! COSTS_N_INSNS (2), /* MGHI */ ! COSTS_N_INSNS (2), /* MH */ ! COSTS_N_INSNS (2), /* MHI */ ! COSTS_N_INSNS (4), /* ML */ ! COSTS_N_INSNS (4), /* MR */ ! COSTS_N_INSNS (5), /* MS */ ! COSTS_N_INSNS (6), /* MSG */ ! COSTS_N_INSNS (4), /* MSGF */ ! COSTS_N_INSNS (4), /* MSGFR */ ! COSTS_N_INSNS (4), /* MSGR */ ! COSTS_N_INSNS (4), /* MSR */ ! COSTS_N_INSNS (1), /* multiplication in DFmode */ ! COSTS_N_INSNS (28), /* MXBR */ ! COSTS_N_INSNS (130), /* SQXBR */ ! COSTS_N_INSNS (66), /* SQDBR */ COSTS_N_INSNS (38), /* SQEBR */ ! COSTS_N_INSNS (1), /* MADBR */ ! COSTS_N_INSNS (1), /* MAEBR */ ! COSTS_N_INSNS (60), /* DXBR */ ! COSTS_N_INSNS (40), /* DDBR */ ! COSTS_N_INSNS (26), /* DEBR */ ! COSTS_N_INSNS (30), /* DLGR */ ! COSTS_N_INSNS (23), /* DLR */ ! COSTS_N_INSNS (23), /* DR */ ! COSTS_N_INSNS (24), /* DSGFR */ ! COSTS_N_INSNS (24), /* DSGR */ }; extern int reload_completed; --- 192,224 ---- static const struct processor_costs z10_cost = { ! COSTS_N_INSNS (10), /* M */ ! COSTS_N_INSNS (10), /* MGHI */ ! COSTS_N_INSNS (10), /* MH */ ! COSTS_N_INSNS (10), /* MHI */ ! COSTS_N_INSNS (10), /* ML */ ! COSTS_N_INSNS (10), /* MR */ ! COSTS_N_INSNS (10), /* MS */ ! COSTS_N_INSNS (10), /* MSG */ ! COSTS_N_INSNS (10), /* MSGF */ ! COSTS_N_INSNS (10), /* MSGFR */ ! COSTS_N_INSNS (10), /* MSGR */ ! COSTS_N_INSNS (10), /* MSR */ ! COSTS_N_INSNS (10), /* multiplication in DFmode */ ! COSTS_N_INSNS (50), /* MXBR */ ! COSTS_N_INSNS (120), /* SQXBR */ ! COSTS_N_INSNS (52), /* SQDBR */ COSTS_N_INSNS (38), /* SQEBR */ ! COSTS_N_INSNS (10), /* MADBR */ ! COSTS_N_INSNS (10), /* MAEBR */ ! COSTS_N_INSNS (111), /* DXBR */ ! COSTS_N_INSNS (39), /* DDBR */ ! COSTS_N_INSNS (32), /* DEBR */ ! COSTS_N_INSNS (160), /* DLGR */ ! COSTS_N_INSNS (71), /* DLR */ ! COSTS_N_INSNS (71), /* DR */ ! COSTS_N_INSNS (71), /* DSGFR */ ! COSTS_N_INSNS (71), /* DSGR */ }; extern int reload_completed; *************** s390_agen_dep_p (rtx dep_insn, rtx insn) *** 5249,5254 **** --- 5249,5255 ---- return 0; } + /* A C statement (sans semicolon) to update the integer scheduling priority INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, reduce the priority to execute INSN later. Do not define this macro if Index: gcc/config/s390/2084.md =================================================================== *** gcc/config/s390/2084.md.orig 2008-08-15 09:08:50.000000000 +0200 --- gcc/config/s390/2084.md 2008-08-15 09:09:26.000000000 +0200 *************** *** 243,249 **** (define_insn_reservation "x_itof" 7 (and (eq_attr "cpu" "z990,z9_109") ! (eq_attr "type" "itof")) "x_e1_t*3,x-wr-fp") (define_bypass 1 "x_fsimpdf" "x_fstoredf") --- 243,249 ---- (define_insn_reservation "x_itof" 7 (and (eq_attr "cpu" "z990,z9_109") ! (eq_attr "type" "itoftf,itofdf,itofsf")) "x_e1_t*3,x-wr-fp") (define_bypass 1 "x_fsimpdf" "x_fstoredf")
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