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DISCONTINUED:openSUSE:11.1:Update
xen
19400-ensure-ltr-execute.patch
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File 19400-ensure-ltr-execute.patch of Package xen
# HG changeset patch # User Keir Fraser <keir.fraser@citrix.com> # Date 1237482246 0 # Node ID e1562a36094e89fdebd952ccbfc78b9d3de2649f # Parent 633e08774dab5b411ef7614fb9fc2e1a5eb2cb9c x86: Ensure we execute LTR when running on non-compat GDT which has busy bit clear in TSS descriptor. Signed-off-by: Keir Fraser <keir.fraser@citrix.com> # HG changeset patch # User Keir Fraser <keir.fraser@citrix.com> # Date 1237538064 0 # Node ID f87b2374cdf065758b4504e34cbd1f393bfe2197 # Parent e1562a36094e89fdebd952ccbfc78b9d3de2649f x86: Fix the 32-bit build after c/s 19400. Signed-off-by: Keir Fraser <keir.fraser@citrix.com> --- a/xen/arch/x86/acpi/suspend.c +++ b/xen/arch/x86/acpi/suspend.c @@ -31,13 +31,9 @@ void save_rest_processor_state(void) void restore_rest_processor_state(void) { - int cpu = smp_processor_id(); - struct tss_struct *t = &init_tss[cpu]; struct vcpu *v = current; - /* Rewriting the TSS desc is necessary to clear the Busy flag. */ - set_tss_desc(cpu, t); - load_TR(cpu); + load_TR(); #if defined(CONFIG_X86_64) /* Recover syscall MSRs */ @@ -47,7 +43,7 @@ void restore_rest_processor_state(void) wrmsr(MSR_SYSCALL_MASK, EF_VM|EF_RF|EF_NT|EF_DF|EF_IE|EF_TF, 0U); #else /* !defined(CONFIG_X86_64) */ if ( supervisor_mode_kernel && cpu_has_sep ) - wrmsr(MSR_IA32_SYSENTER_ESP, &t->esp1, 0); + wrmsr(MSR_IA32_SYSENTER_ESP, &init_tss[smp_processor_id()].esp1, 0); #endif /* Maybe load the debug registers. */ --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -613,8 +613,7 @@ void __cpuinit cpu_init(void) BUG_ON((get_stack_bottom() & 15) != 0); t->rsp0 = get_stack_bottom(); #endif - set_tss_desc(cpu,t); - load_TR(cpu); + load_TR(); asm volatile ( "lldt %%ax" : : "a" (0) ); /* Clear all 6 debug registers: */ --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2981,20 +2981,31 @@ void set_intr_gate(unsigned int n, void __set_intr_gate(n, 0, addr); } -void set_tss_desc(unsigned int n, void *addr) +void load_TR(void) { + struct tss_struct *tss = &init_tss[smp_processor_id()]; + struct desc_ptr old_gdt, tss_gdt = { + .base = (long)(this_cpu(gdt_table) - FIRST_RESERVED_GDT_ENTRY), + .limit = LAST_RESERVED_GDT_BYTE + }; + _set_tssldt_desc( - per_cpu(gdt_table, n) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY, - (unsigned long)addr, + this_cpu(gdt_table) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY, + (unsigned long)tss, offsetof(struct tss_struct, __cacheline_filler) - 1, 9); #ifdef CONFIG_COMPAT _set_tssldt_desc( - per_cpu(compat_gdt_table, n) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY, - (unsigned long)addr, + this_cpu(compat_gdt_table) + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY, + (unsigned long)tss, offsetof(struct tss_struct, __cacheline_filler) - 1, 11); #endif + + /* Switch to non-compat GDT (which has B bit clear) to execute LTR. */ + asm volatile ( + "sgdt %1; lgdt %2; ltr %%ax; lgdt %1" + : : "a" (TSS_ENTRY << 3), "m" (old_gdt), "m" (tss_gdt) : "memory" ); } void __devinit percpu_traps_init(void) --- a/xen/include/asm-x86/desc.h +++ b/xen/include/asm-x86/desc.h @@ -57,8 +57,6 @@ #ifndef __ASSEMBLY__ -#define load_TR(n) __asm__ __volatile__ ("ltr %%ax" : : "a" (TSS_ENTRY<<3) ) - #if defined(__x86_64__) #define GUEST_KERNEL_RPL(d) (is_pv_32bit_domain(d) ? 1 : 3) #elif defined(__i386__) @@ -219,7 +217,7 @@ DECLARE_PER_CPU(struct desc_struct *, co #endif extern void set_intr_gate(unsigned int irq, void * addr); -extern void set_tss_desc(unsigned int n, void *addr); +extern void load_TR(void); #endif /* !__ASSEMBLY__ */
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