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DISCONTINUED:openSUSE:11.2
gcc41
partial-flag-regstall.patch
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File partial-flag-regstall.patch of Package gcc41
From jh@suse.cz Wed Sep 20 00:31:51 2006 Date: Wed, 20 Sep 2006 00:31:44 +0200 From: Jan Hubicka <jh@suse.cz> To: <rguenther@suse.de> Subject: [hjl@lucon.org: A possible regression in gcc 4.1] Hi, please can you drop this into our compiler? It is pretty safe and independently on the fix we should not produce the shifts for cores. Honza ----- Forwarded message from "H. J. Lu" <hjl@lucon.org> ----- X-Original-To: hubicka@kam.ms.mff.cuni.cz Delivered-To: hubicka@kam.ms.mff.cuni.cz X-Sieve: CMU Sieve 2.2 Date: Tue, 19 Sep 2006 10:07:51 -0700 From: "H. J. Lu" <hjl@lucon.org> To: jh@suse.cz Subject: A possible regression in gcc 4.1 User-Agent: Mutt/1.4.2.1i X-Virus-Scanned: by amavisd-new at suse.cz X-Spam-Checker-Version: SpamAssassin 3.0.3 (2005-04-27) on kamikaze.ms.mff.cuni.cz X-Spam-Status: No, score=0.1 required=5.0 tests=AWL,FORGED_RCVD_HELO autolearn=disabled version=3.0.3 X-Spam-Level: X-DSPAM-Result: Whitelisted X-DSPAM-Processed: Tue Sep 19 19:08:17 2006 X-DSPAM-Confidence: 0.9997 X-DSPAM-Probability: 0.0000 X-DSPAM-Signature: 45102401108816553515993 X-DSPAM-Factors: 27, lu+intel, 0.00010, Return-Path*lucon+org, 0.00010, *hjl+lucon, 0.00010, ccmode, 0.00010, ccmode, 0.00010, ccmode+insn, 0.00010, ccmode+insn, 0.00010, From*"H. J. Lu" <hjl@lucon.org>, 0.00010, operator+ok, 0.00010, operator+ok, 0.00010, ashrdi3, 0.00010, ashrdi3, 0.00010, branch+could, 0.00010, TARGET+PARTIAL, 0.00010, TARGET+PARTIAL, 0.00010, dup+TARGET, 0.00010, dup+TARGET, 0.00010, md+revision, 0.00010, md+revision, 0.00010, From*hjl+lucon, 0.00010, Received*hjjean, 0.00010, mainline+If, 0.00010, hongjiu, 0.00010, Subject*in+gcc, 0.00010, DI+match, 0.00010, DI+match, 0.00010, ix86+binary, 0.00010 Hi Jan, Do you sync gcc 4.1 used by Novell with gcc 4.1 branch? The bug fix in 4.1 branch for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28946 will cause a regression in gcc 4.1 with -mtune=generic patch. This is a back ported patch from mainline. If you sync your gcc 4.1 with gcc 4.1 branch, could you consider this patch? Thanks. H.J. ---- 2006-09-05 H.J. Lu <hongjiu.lu@intel.com> * config/i386/i386.c (x86_partial_flag_reg_stall): New. * config/i386/i386.h (x86_partial_flag_reg_stall): New. (TARGET_PARTIAL_FLAG_REG_STALL): New. * config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for TARGET_PARTIAL_FLAG_REG_STALL. (*ashldi3_cconly_rex64): Likewise. (*ashlsi3_cmp): Likewise. (*ashlsi3_cconly): Likewise. (*ashlsi3_cmp_zext): Likewise. (*ashlhi3_cmp): Likewise. (*ashlhi3_cconly): Likewise. (*ashlqi3_cmp): Likewise. (*ashlqi3_cconly): Likewise. (*ashrdi3_cmp_rex64): Likewise. (*ashrdi3_cconly_rex64): Likewise. (*ashrsi3_cmp): Likewise. (*ashrsi3_cconly): Likewise. (*ashrsi3_cmp_zext): Likewise. (*ashrhi3_cmp): Likewise. (*ashrhi3_cconly): Likewise. (*ashrqi3_cmp): Likewise. (*ashrqi3_cconly): Likewise. (*lshrdi3_cmp_rex64): Likewise. (*lshrdi3_cconly_rex64): Likewise. (*lshrsi3_cmp): Likewise. (*lshrsi3_cconly): Likewise. (*lshrsi3_cmp_zext): Likewise. (*lshrhi3_cmp): Likewise. (*lshrhi3_cconly): Likewise. (*lshrqi2_cmp): Likewise. (*lshrqi2_cconly): Likewise. Index: gcc/config/i386/i386.h =================================================================== --- gcc/config/i386/i386.h (revision 116756) +++ gcc/config/i386/i386.h (revision 116757) @@ -164,6 +164,7 @@ extern const int x86_use_bt; extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd; extern const int x86_use_incdec; extern const int x86_pad_returns; +extern const int x86_partial_flag_reg_stall; extern int x86_prefetch_sse; #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) @@ -182,6 +183,7 @@ extern int x86_prefetch_sse; #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) #define TARGET_MOVX (x86_movx & TUNEMASK) #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) +#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK) #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (revision 116756) +++ gcc/config/i386/i386.md (revision 116757) @@ -10396,7 +10396,12 @@ (set (match_operand:DI 0 "nonimmediate_operand" "=rm") (ashift:DI (match_dup 1) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, DImode, operands)" + && ix86_binary_operator_ok (ASHIFT, DImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))" { switch (get_attr_type (insn)) { @@ -10432,7 +10437,12 @@ (const_int 0))) (clobber (match_scratch:DI 0 "=r"))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, DImode, operands)" + && ix86_binary_operator_ok (ASHIFT, DImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || TARGET_DOUBLE_WITH_ADD)))" { switch (get_attr_type (insn)) { @@ -10713,7 +10723,12 @@ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") (ashift:SI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, SImode, operands)" + && ix86_binary_operator_ok (ASHIFT, SImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))" { switch (get_attr_type (insn)) { @@ -10749,7 +10764,12 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, SImode, operands)" + && ix86_binary_operator_ok (ASHIFT, SImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || TARGET_DOUBLE_WITH_ADD)))" { switch (get_attr_type (insn)) { @@ -10786,7 +10806,12 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, SImode, operands)" + && ix86_binary_operator_ok (ASHIFT, SImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || TARGET_DOUBLE_WITH_ADD)))" { switch (get_attr_type (insn)) { @@ -10905,7 +10930,12 @@ (set (match_operand:HI 0 "nonimmediate_operand" "=rm") (ashift:HI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, HImode, operands)" + && ix86_binary_operator_ok (ASHIFT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))" { switch (get_attr_type (insn)) { @@ -10941,7 +10971,12 @@ (const_int 0))) (clobber (match_scratch:HI 0 "=r"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, HImode, operands)" + && ix86_binary_operator_ok (ASHIFT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || TARGET_DOUBLE_WITH_ADD)))" { switch (get_attr_type (insn)) { @@ -11099,7 +11134,12 @@ (set (match_operand:QI 0 "nonimmediate_operand" "=qm") (ashift:QI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, QImode, operands)" + && ix86_binary_operator_ok (ASHIFT, QImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))" { switch (get_attr_type (insn)) { @@ -11135,7 +11175,12 @@ (const_int 0))) (clobber (match_scratch:QI 0 "=q"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFT, QImode, operands)" + && ix86_binary_operator_ok (ASHIFT, QImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL + || (operands[2] == const1_rtx + && (TARGET_SHIFT1 + || TARGET_DOUBLE_WITH_ADD)))" { switch (get_attr_type (insn)) { @@ -11332,7 +11377,9 @@ (set (match_operand:DI 0 "nonimmediate_operand" "=rm") (ashiftrt:DI (match_dup 1) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, DImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{q}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "DI")]) @@ -11345,7 +11392,9 @@ (const_int 0))) (clobber (match_scratch:DI 0 "=r"))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, DImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{q}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "DI")]) @@ -11579,7 +11628,9 @@ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") (ashiftrt:SI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{l}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "SI")]) @@ -11592,7 +11643,9 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{l}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "SI")]) @@ -11606,7 +11659,9 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "SI")]) @@ -11692,7 +11747,9 @@ (set (match_operand:HI 0 "nonimmediate_operand" "=rm") (ashiftrt:HI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{w}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "HI")]) @@ -11705,7 +11762,9 @@ (const_int 0))) (clobber (match_scratch:HI 0 "=r"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{w}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "HI")]) @@ -11819,7 +11878,9 @@ (set (match_operand:QI 0 "nonimmediate_operand" "=qm") (ashiftrt:QI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, QImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{b}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "QI")]) @@ -11832,7 +11893,9 @@ (const_int 0))) (clobber (match_scratch:QI 0 "=q"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" + && ix86_binary_operator_ok (ASHIFTRT, QImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "sar{b}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "QI")]) @@ -11976,7 +12039,9 @@ (set (match_operand:DI 0 "nonimmediate_operand" "=rm") (lshiftrt:DI (match_dup 1) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{q}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "DI")]) @@ -11989,7 +12054,9 @@ (const_int 0))) (clobber (match_scratch:DI 0 "=r"))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{q}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "DI")]) @@ -12147,7 +12214,9 @@ (set (match_operand:SI 0 "nonimmediate_operand" "=rm") (lshiftrt:SI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{l}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "SI")]) @@ -12160,7 +12229,9 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{l}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "SI")]) @@ -12174,7 +12245,9 @@ (set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "SI")]) @@ -12260,7 +12333,9 @@ (set (match_operand:HI 0 "nonimmediate_operand" "=rm") (lshiftrt:HI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{w}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "HI")]) @@ -12273,7 +12348,9 @@ (const_int 0))) (clobber (match_scratch:HI 0 "=r"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{w}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "HI")]) @@ -12386,7 +12463,9 @@ (set (match_operand:QI 0 "nonimmediate_operand" "=qm") (lshiftrt:QI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, QImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{b}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "QI")]) @@ -12399,7 +12478,9 @@ (const_int 0))) (clobber (match_scratch:QI 0 "=q"))] "ix86_match_ccmode (insn, CCGOCmode) - && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" + && ix86_binary_operator_ok (LSHIFTRT, QImode, operands) + && (optimize_size + || !TARGET_PARTIAL_FLAG_REG_STALL)" "shr{b}\t{%2, %0|%0, %2}" [(set_attr "type" "ishift") (set_attr "mode" "QI")]) Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (revision 116756) +++ gcc/config/i386/i386.c (revision 116757) @@ -761,6 +761,7 @@ const int x86_use_sahf = m_PPRO | m_K6 | with partial reg. dependencies used by Athlon/P4 based chips, it is better to leave it off for generic32 for now. */ const int x86_partial_reg_stall = m_PPRO; +const int x86_partial_flag_reg_stall = m_GENERIC; const int x86_use_himode_fiop = m_386 | m_486 | m_K6; const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC); const int x86_use_mov0 = m_K6; ----- End forwarded message -----
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