File ucode-intel.changes of Package ucode-intel

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File ucode-intel.changes of Package ucode-intel (Revision 1c7b085b4e39fd3a1111b717de655eed)

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Fri Aug 24 15:03:09 UTC 2018 - meissner@suse.com

- updated to 20180807a, no change except licensing. (bsc#1104479)

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Wed Aug  8 13:53:07 UTC 2018 - meissner@suse.com

- Update to 20180807 release, for the listed CPU chipsets
  this fixes CVE-2018-3640 (Spectre v3a) CVE-2018-3639 (Spectre v4).
  (bsc#1104134 bsc#1087082 bsc#1087083)

Processor             Identifier     Version       Products
  Model        Stepping F-MO-S/PI      Old->New
  ---- new platforms ----------------------------------------
  WSM-EP/WS    U1       6-2c-2/03           0000001f Xeon E/L/X56xx, W36xx
  NHM-EX       D0       6-2e-6/04           0000000d Xeon E/L/X65xx/75xx
  BXT          C0       6-5c-2/01           00000014 Atom T5500/5700
  APL          E0       6-5c-a/03           0000000c Atom x5-E39xx
  DVN          B0       6-5f-1/01           00000024 Atom C3xxx
  ---- updated platforms ------------------------------------
  NHM-EP/WS    D0       6-1a-5/03 00000019->0000001d Xeon E/L/X/W55xx
  NHM          B1       6-1e-5/13 00000007->0000000a Core i7-8xx, i5-7xx; Xeon L3426, X24xx
  WSM          B1       6-25-2/12 0000000e->00000011 Core i7-6xx, i5-6xx/4xxM, i3-5xx/3xxM, Pentium G69xx, Celeon P45xx; Xeon L3406
  WSM          K0       6-25-5/92 00000004->00000007 Core i7-6xx, i5-6xx/5xx/4xx, i3-5xx/3xx, Pentium G69xx/P6xxx/U5xxx, Celeron P4xxx/U3xxx
  SNB          D2       6-2a-7/12 0000002d->0000002e Core Gen2; Xeon E3
  WSM-EX       A2       6-2f-2/05 00000037->0000003b Xeon E7
  IVB          E2       6-3a-9/12 0000001f->00000020 Core Gen3 Mobile
  HSW-H/S/E3   Cx/Dx    6-3c-3/32 00000024->00000025 Core Gen4 Desktop; Xeon E3 v3
  BDW-U/Y      E/F      6-3d-4/c0 0000002a->0000002b Core Gen5 Mobile
  HSW-ULT      Cx/Dx    6-45-1/72 00000023->00000024 Core Gen4 Mobile and derived Pentium/Celeron
  HSW-H        Cx       6-46-1/32 00000019->0000001a Core Extreme i7-5xxxX
  BDW-H/E3     E/G      6-47-1/22 0000001d->0000001e Core i5-5xxxR/C, i7-5xxxHQ/EQ; Xeon E3 v4
  SKL-U/Y      D0       6-4e-3/c0 000000c2->000000c6 Core Gen6 Mobile
  BDX-DE       V1       6-56-2/10 00000015->00000017 Xeon D-1520/40
  BDX-DE       V2/3     6-56-3/10 07000012->07000013 Xeon D-1518/19/21/27/28/31/33/37/41/48, Pentium D1507/08/09/17/19
  BDX-DE       Y0       6-56-4/10 0f000011->0f000012 Xeon D-1557/59/67/71/77/81/87
  APL          D0       6-5c-9/03 0000002c->00000032 Pentium N/J4xxx, Celeron N/J3xxx, Atom x5/7-E39xx
  SKL-H/S/E3   R0       6-5e-3/36 000000c2->000000c6 Core Gen6; Xeon E3 v5
  GLK          B0       6-7a-1/01 00000022->00000028 Pentium Silver N/J5xxx, Celeron N/J4xxx
  KBL-U/Y      H0       6-8e-9/c0 00000084->0000008e Core Gen7 Mobile
  CFL-U43e     D0       6-8e-a/c0 00000084->00000096 Core Gen8 Mobile
  KBL-H/S/E3   B0       6-9e-9/2a 00000084->0000008e Core Gen7; Xeon E3 v6
  CFL-H/S/E3   U0       6-9e-a/22 00000084->00000096 Core Gen8
  CFL-H/S/E3   B0       6-9e-b/02 00000084->0000008e Core Gen8 Desktop

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Mon Jul 30 15:11:13 UTC 2018 - meissner@suse.com

- rename /lib/firmware/intel-ucode/06-4f-01.early to /lib/firmware/intel-ucode/06-4f-01
  (bsc#1103116)

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Wed Jul  4 15:05:31 UTC 2018 - meissner@suse.com

- Update to 20180703 release, for the listed CPU chipsets
  this fixes CVE-2018-3640 (Spectre v3a) CVE-2018-3639 (Spectre v4).
  (bsc#1100147 bsc#1087082 bsc#1087083)

https://downloadcenter.intel.com/download/27945/Linux-Processor-Microcode-Data-File

Following chipsets are fixed in this round:

Model        Stepping F-MO-S/PI      Old->New
  ---- updated platforms ------------------------------------
  SNB-EP       C1       6-2d-6/6d 0000061c->0000061d Xeon E5
  SNB-EP       C2       6-2d-7/6d 00000713->00000714 Xeon E5
  IVT          C0       6-3e-4/ed 0000042c->0000042d Xeon E5 v2; Core i7-4960X/4930K/4820K
  IVT          D1       6-3e-7/ed 00000713->00000714 Xeon E5 v2
  HSX-E/EP/4S  C0       6-3f-2/6f 0000003c->0000003d Xeon E5 v3
  HSX-EX       E0       6-3f-4/80 00000011->00000012 Xeon E7 v3
  SKX-SP/D/W/X H0       6-55-4/b7 02000043->0200004d Xeon Bronze 31xx, Silver 41xx, Gold 51xx/61xx Platinum 81xx, D/W-21xx; Core i9-7xxxX
  BDX-DE       A1       6-56-5/10 0e000009->0e00000a Xeon D-15x3N

---- intel-ucode-with-caveats/ ----------------------------
  BDX-ML       B/M/R0   6-4f-1/ef 0b00002c->0b00002e Xeon E5/E7 v4; Core i7-69xx/68xx

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Wed Jun  6 14:38:13 CEST 2018 - tiwai@suse.de

- Add a new style supplements for the recent kernels (bsc#1096141)

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Fri May 14 09:42:54 UTC 2018 - trenn@suse.de

- Update to version 20180425 (bsc#1091836)
- Name microcodes which are not allowed to load late
  with a *.early suffix
- Add releasenotes and microcode list to docs
- Remove BuildRequires on iucode-tool, as the microcode files are
  not provided as one big microcode.dat blob anymore, but are
  already split up in the needed family-model-stepping files.

-- Updates upon 20180312 release --
---- updated platforms ------------------------------------
GLK          B0       6-7a-1/01 0000001e->00000022
             Pentium Silver N/J5xxx,-Celeron N/J4xxx
---- removed platforms ------------------------------------
BDX-ML       B/M/R0   6-4f-1/ef 0b000021
             Xeon E5/E7 v4; Core-i7-69xx/68xx
-- Special release with caveats --
BDX-ML       B/M/R0   6-4f-1/ef           0b00002c
             Xeon E5/E7 v4; Corei7-69xx/68xx

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Wed Mar 14 14:15:49 UTC 2018 - meissner@suse.com

- Updated to microcode version: 20180312 (bsc#1085207 CVE-2017-5715)
  -- New Platforms --
  BDX-DE EGW A0 6-56-5:10 e000009
  SKX B1 6-55-3:97 1000140
  -- Updates --
  SNB D2 6-2a-7:12 29->2d
  JKT C1 6-2d-6:6d 619->61c
  JKT C2 6-2d-7:6d 710->713
  IVB E2 6-3a-9:12 1c->1f
  IVT C0 6-3e-4:ed 428->42c
  IVT D1 6-3e-7:ed 70d->713
  HSW Cx/Dx 6-3c-3:32 22->24
  HSW-ULT Cx/Dx 6-45-1:72 20->23
  CRW Cx 6-46-1:32 17->19
  HSX C0 6-3f-2:6f 3a->3c
  HSX-EX E0 6-3f-4:80 0f->11
  BDW-U/Y E/F 6-3d-4:c0 25->2a
  BDW-H E/G 6-47-1:22 17->1d
  BDX-DE V0/V1 6-56-2:10 0f->15
  BDW-DE V2 6-56-3:10 700000d->7000012
  BDW-DE Y0 6-56-4:10 f00000a->f000011
  SKL-U/Y D0 6-4e-3:c0 ba->c2
  SKL R0 6-5e-3:36 ba->c2
  KBL-U/Y H0 6-8e-9:c0 62->84
  KBL B0 6-9e-9:2a 5e->84
  CFL D0 6-8e-a:c0 70->84
  CFL U0 6-9e-a:22 70->84
  CFL B0 6-9e-b:02 72->84
  SKX H0 6-55-4:b7 2000035->2000043

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Thu Feb  8 14:35:47 UTC 2018 - meissner@suse.com

- This reverts the ucode-intel package back to the 20170707 release. The
  version is 20180108.revertto20170707 to make sure it is installed on
  affected systems. (bsc#1079890 bsc#1074919)

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Wed Jan 10 11:38:08 UTC 2018 - trenn@suse.de

- Update to version 20180108 (bsc#1075262)
- Revert last changes:
D firmware-CVE-2017-5715.tar.gz
  The pre-released microcode fixing some important security issues
  is now officially published (and included in the added tarball).
- New firmware updates since last version (20170707) are avail for these
  Intel processors:

IVT C0          (06-3e-04:ed) 428->42a
  SKL-U/Y D0      (06-4e-03:c0) ba->c2
  BDW-U/Y E/F     (06-3d-04:c0) 25->28
  HSW-ULT Cx/Dx   (06-45-01:72) 20->21
  Crystalwell Cx  (06-46-01:32) 17->18
  BDW-H E/G       (06-47-01:22) 17->1b
  HSX-EX E0       (06-3f-04:80) 0f->10
  SKL-H/S R0      (06-5e-03:36) ba->c2
  HSW Cx/Dx       (06-3c-03:32) 22->23
  HSX C0          (06-3f-02:6f) 3a->3b
  BDX-DE V0/V1    (06-56-02:10) 0f->14
  BDX-DE V2       (06-56-03:10) 700000d->7000011
  KBL-U/Y H0      (06-8e-09:c0) 62->80
  KBL Y0 / CFL D0 (06-8e-0a:c0) 70->80
  KBL-H/S B0      (06-9e-09:2a) 5e->80
  CFL U0          (06-9e-0a:22) 70->80
  CFL B0          (06-9e-0b:02) 72->80
  SKX H0          (06-55-04:b7) 2000035->200003c
  GLK B0          (06-7a-01:01) 1e->22

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Sat Dec 23 13:12:18 UTC 2017 - meissner@suse.com

- firmware-CVE-2017-5715.tar.gz: updates for:
  HSX EP 000306F2
  BDX E EP EP4S EX 000406F1
  SKX H0 00050654
  (bsc#1068032 CVE-2017-5715)

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Thu Jul 13 14:27:51 UTC 2017 - trenn@suse.de

- Update to version 20170707 (bsc#1048133, bsc#1043358):

KBL H0 (06-8e-09:c0) 62
  KBL Y0 (06-8e-0a:c0) 66
  KBL B0 (06-9e-09:2a) 5e
  SKX H0 (06-55-04:97) 2000022

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Mon Jul  3 14:00:48 UTC 2017 - trenn@suse.de

- Update to version 20170511 (bsc#1046175):

BDX-ML B0/M0/R0 (06-4f-01:ef) b00001f->b000021
  Skylake D0 (06-4e-03:c0) 9e->ba
  Broadwell ULT/ULX E/F-step (06-3d-04:c0) 24->25
  ULT Cx/Dx (06-45-01:72) 1f->20
  Crystalwell Cx (06-46-01:32) 16->17
  Broadwell Halo E/G-step (06-47-01:22) 16->17
  HSX EX E0 (06-3f-04:80) d->f
  Skylake R0 (06-5e-03:36) 9e->ba
  Haswell Cx/Dx (06-3c-03:32) 20->22
  HSX C0 (06-3f-02:6f) 39->3a

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Fri Apr 28 12:14:42 UTC 2017 - trenn@suse.de

- Update to version 20161104 (bsc#1030224).

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Thu Jul 21 09:45:14 UTC 2016 - trenn@suse.de

- Update to version 20160714 (bsc#986034).

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Thu Nov 12 09:57:25 UTC 2015 - trenn@suse.de

- Update to latest microcode version 20151106 (bnc#954423)

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Mon Mar 23 07:11:41 UTC 2015 - trenn@suse.de

- Update to latest microcode version 20150121 (bnc#913004)

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Fri Sep 19 12:46:55 UTC 2014 - trenn@suse.de

- Do not try to reload/update microcode at runtime after package
  installation. Only supported way of updating microcode is via
  early microcode update via initrd. bnc#896736

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Wed Sep 17 09:13:25 UTC 2014 - trenn@suse.de

- Update to Intel microcode version 20140624 (bnc#896736, fate#317896)
  This microcode disables lock elision on CPUs which are known to
  not work reliable with this feature

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Wed Jul  2 11:59:34 CEST 2014 - tiwai@suse.de

- Update to Intel microcode version 20140624 (bnc#885213)

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Fri Jun 13 17:15:38 UTC 2014 - trenn@suse.de

- Delete mkinitrd scripts. This is done via %rpm regenerate_initrd_* macros
  (bnc#894160)

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Mon May  5 15:45:49 UTC 2014 - trenn@suse.de

- Update to Intel microcode version 20140430 (bnc#876073)

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Fri Apr  4 13:39:48 UTC 2014 - mmarek@suse.cz

- Regenerate the initrd in %posttrans (fate#313506)

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Tue Feb 11 09:13:12 UTC 2014 - idonmez@suse.com

- ucode 20140122, no changelog available.

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Tue Dec 10 12:43:57 UTC 2013 - trenn@suse.de

- Loading firmware needs udev to be running

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Mon Dec  2 14:17:33 UTC 2013 - trenn@suse.de

- Add mkinitrd script to add Intel microcode to initrd.
  This is needed because microcode driver is built in or gets loaded
  automatically via udev early. Therefore the microcode has to be available
  in initrd already.
  This must not be mixed up with early micorcode loading. This feature will
  not be implemented via mkinitrd. Dracut is doing early microcode loading.
- bnc#847158
- mkinitrd scripts:
    - mkinitrd_setup-intel_microcode.sh
      Adding microcode to the initrd
    - mkinitrd_boot-intel_microcode.sh
      Triggering the reload at boot

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Mon Nov 25 11:14:51 UTC 2013 - trenn@suse.de

- Correct Supplements string so that the package gets correctly installed
  on machines with Intel CPUs
  bnc#847158

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Sun Sep 22 16:23:54 UTC 2013 - crrodriguez@opensuse.org

- ucode 20130906, no changelog available.

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Fri Aug 30 23:31:41 UTC 2013 - crrodriguez@opensuse.org

- ucode 20130808, as usual, no changelog available.

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Thu Jul 25 06:33:45 UTC 2013 - aj@suse.com

- Run spec-cleaner

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Wed Jul 24 23:17:08 UTC 2013 - jeffm@suse.com

- Initial packaging. Moved microcode from microctl_ctl package.

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File ucode-intel.changes of Package ucode-intel (Revision 1c7b085b4e39fd3a1111b717de655eed)

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