File 55111ee4-x86-support-newer-Intel-CPU-models.patch of Package xen.10697

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File 55111ee4-x86-support-newer-Intel-CPU-models.patch of Package xen.10697

References: bsc#990970

# Commit 8779c65538a1132751c0342266ffc4090e5f41e1
# Date 2015-03-24 09:23:00 +0100
# Author Jan Beulich <jbeulich@suse.com>
# Committer Jan Beulich <jbeulich@suse.com>
x86: support newer Intel CPU models

This just follows what the January 2015 edition of the SDM documents,
with additional clarification from Intel:
- Broadwell models 0x4f and 0x56 don't cross-reference other tables,
  but should be treated like other Boradwell (0x3d),
- Xeon Phi model 0x57 lists LASTBRANCH_TOS but not where the actual
  stack is. Being told it's Silvermont based, attach it there.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -69,6 +69,7 @@
 #define GET_CC3_RES(val)  GET_HW_RES_IN_NS(0x3FC, val)
 #define GET_CC6_RES(val)  GET_HW_RES_IN_NS(0x3FD, val)
 #define GET_CC7_RES(val)  GET_HW_RES_IN_NS(0x3FE, val) /* SNB only */
+#define PHI_CC6_RES(val)  GET_HW_RES_IN_NS(0x3FF, val) /* Xeon Phi only */
 
 static void lapic_timer_nop(void) { }
 void (*__read_mostly lapic_timer_off)(void);
@@ -109,6 +110,8 @@ struct acpi_processor_power *__read_most
 
 struct hw_residencies
 {
+    uint64_t mc0;
+    uint64_t mc6;
     uint64_t pc2;
     uint64_t pc3;
     uint64_t pc6;
@@ -139,8 +142,11 @@ static void do_get_hw_residencies(void *
     case 0x3F:
     case 0x45:
     case 0x46:
-    /* future */
+    /* Broadwell */
     case 0x3D:
+    case 0x4F:
+    case 0x56:
+    /* future */
     case 0x4E:
         GET_PC2_RES(hw_res->pc2);
         GET_CC7_RES(hw_res->cc7);
@@ -160,6 +166,16 @@ static void do_get_hw_residencies(void *
         GET_CC3_RES(hw_res->cc3);
         GET_CC6_RES(hw_res->cc6);
         break;
+    /* next gen Xeon Phi */
+    case 0x57:
+        GET_CC3_RES(hw_res->mc0); /* abusing GET_CC3_RES */
+        GET_CC6_RES(hw_res->mc6); /* abusing GET_CC6_RES */
+        GET_PC2_RES(hw_res->pc2);
+        GET_PC3_RES(hw_res->pc3);
+        GET_PC6_RES(hw_res->pc6);
+        GET_PC7_RES(hw_res->pc7);
+        PHI_CC6_RES(hw_res->cc6);
+        break;
     }
 }
 
@@ -179,6 +195,9 @@ static void print_hw_residencies(uint32_
 
     get_hw_residencies(cpu, &hw_res);
 
+    if ( hw_res.mc0 | hw_res.mc6 )
+        printk("MC0[%"PRIu64"] MC6[%"PRIu64"]\n",
+               hw_res.mc0, hw_res.mc6);
     printk("PC2[%"PRId64"] PC3[%"PRId64"] PC6[%"PRId64"] PC7[%"PRId64"]\n",
            hw_res.pc2, hw_res.pc3, hw_res.pc6, hw_res.pc7);
     printk("CC3[%"PRId64"] CC6[%"PRId64"] CC7[%"PRId64"]\n",
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1958,14 +1958,20 @@ static const struct lbr_info *last_branc
         case 58: case 62:
         /* Haswell */
         case 60: case 63: case 69: case 70:
+        /* Broadwell */
+        case 61: case 79: case 86:
         /* future */
-        case 61: case 78:
+        case 78:
             return nh_lbr;
             break;
         /* Atom */
         case 28: case 38: case 39: case 53: case 54:
         /* Silvermont */
         case 55: case 74: case 77: case 90: case 93:
+        /* next gen Xeon Phi */
+        case 87:
+        /* Airmont */
+        case 76:
             return at_lbr;
             break;
         }
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -915,9 +915,16 @@ int vmx_vpmu_initialise(struct vcpu *v,
         case 0x45:
         case 0x46:
 
-        /* future: */
+        /* Broadwell */
         case 0x3d:
+        case 0x4f:
+        case 0x56:
+
+        /* future: */
         case 0x4e:
+
+        /* next gen Xeon Phi */
+        case 0x57:
             ret = core2_vpmu_initialise(v, vpmu_flags);
             if ( !ret )
                 vpmu->arch_vpmu_ops = &core2_vpmu_ops;

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File 55111ee4-x86-support-newer-Intel-CPU-models.patch of Package xen.10697

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