File 56e197e7-x86-don-t-flush-the-whole-cache-when-c... of Package xen.10697

Overview Repositories Revisions Requests Users Attributes Meta

File 56e197e7-x86-don-t-flush-the-whole-cache-when-changing-cachability.patch of Package xen.10697

# Commit dff593c7b6eb1cfd4591b662a880a0c9325cce40
# Date 2016-03-10 16:51:03 +0100
# Author David Vrabel <david.vrabel@citrix.com>
# Committer Jan Beulich <jbeulich@suse.com>
x86: don't flush the whole cache when changing cachability

Introduce the FLUSH_VA_VALID flag to flush_area_mask() and friends to
say that it is safe to use CLFLUSH (i.e., the virtual address is still
valid).

Use this when changing the cachability of the Xen direct mappings (in
response to the guest changing the cachability of its mappings). This
significantly improves performance by avoiding an expensive WBINVD.

This fixes a performance regression introduced by
c61a6f74f80eb36ed83a82f713db3143159b9009 (x86: enforce consistent
cachability of MMIO mappings), the fix for XSA-154.

e.g., A set_memory_wc() call in Linux:

before: 4097 us
after:    47 us

Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -152,7 +152,8 @@ void flush_area_local(const void *va, un
         if ( order < (BITS_PER_LONG - PAGE_SHIFT) )
             sz = 1UL << (order + PAGE_SHIFT);
 
-        if ( !(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) &&
+        if ( (!(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) ||
+              (flags & FLUSH_VA_VALID)) &&
              c->x86_clflush_size && c->x86_cache_size && sz &&
              ((sz >> 10) < c->x86_cache_size) )
         {
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -5436,7 +5436,12 @@ int map_pages_to_xen(
         flush_flags |= FLUSH_TLB_GLOBAL;       \
     if ( (flags & _PAGE_PRESENT) &&            \
          (((o_) ^ flags) & PAGE_CACHE_ATTRS) ) \
+    {                                          \
         flush_flags |= FLUSH_CACHE;            \
+        if ( virt >= DIRECTMAP_VIRT_START &&   \
+             virt < HYPERVISOR_VIRT_END )      \
+            flush_flags |= FLUSH_VA_VALID;     \
+    }                                          \
 } while (0)
 
     while ( nr_mfns != 0 )
--- a/xen/include/asm-x86/flushtlb.h
+++ b/xen/include/asm-x86/flushtlb.h
@@ -84,6 +84,8 @@ void write_cr3(unsigned long cr3);
 #define FLUSH_TLB_GLOBAL 0x200
  /* Flush data caches */
 #define FLUSH_CACHE      0x400
+ /* VA for the flush has a valid mapping */
+#define FLUSH_VA_VALID   0x800
 
 /* Flush local TLBs/caches. */
 void flush_area_local(const void *va, unsigned int flags);

Places

File 56e197e7-x86-don-t-flush-the-whole-cache-when-changing-cachability.patch of Package xen.10697

Places