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SUSE:SLE-12-SP1:GA
xen.5015
587de4a9-x86emul-VEX-B-ignored-in-compat-mode.p...
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File 587de4a9-x86emul-VEX-B-ignored-in-compat-mode.patch of Package xen.5015
# Commit 89c76ee7f60777b81c8fd0475a6af7c84e72a791 # Date 2017-01-17 10:32:25 +0100 # Author Jan Beulich <jbeulich@suse.com> # Committer Jan Beulich <jbeulich@suse.com> x86emul: VEX.B is ignored in compatibility mode While VEX.R and VEX.X are guaranteed to be 1 in compatibility mode (and hence a respective mode_64bit() check can be dropped), VEX.B can be encoded as zero, but would be ignored by the processor. Since we emulate instructions in 64-bit mode (except possibly in the test harness), we need to force the bit to 1 in order to not act on the wrong {X,Y,Z}MM register (which has no bad effect on 32-bit test harness builds, as there the bit would again be ignored by the hardware, and would by default be expected to be 1 anyway). We must not, however, fiddle with the high bit of VEX.VVVV in the decode phase, as that would undermine the checking of instructions requiring the field to be all ones independent of mode. This is being enforced in copy_REX_VEX() instead. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> # Commit beb82042447c5d6e7073d816d6afc25c5a423cde # Date 2017-01-25 15:08:59 +0100 # Author Jan Beulich <jbeulich@suse.com> # Committer Jan Beulich <jbeulich@suse.com> x86emul: correct VEX/XOP/EVEX operand size handling for 16-bit code Operand size defaults to 32 bits in that case, but would not have been set that way in the absence of an operand size override. Reported-by: Wei Liu <wei.liu2@citrix.com> (by AFL fuzzing) Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -299,7 +299,11 @@ union vex { #define copy_REX_VEX(ptr, rex, vex) do { \ if ( (vex).opcx != vex_none ) \ + { \ + if ( !mode_64bit() ) \ + vex.reg |= 8; \ ptr[0] = 0xc4, ptr[1] = (vex).raw[0], ptr[2] = (vex).raw[1]; \ + } \ else if ( mode_64bit() ) \ ptr[1] = rex | REX_PREFIX; \ } while (0) @@ -1563,6 +1567,11 @@ x86_emulate( case 8: /* VEX */ generate_exception_if(rex_prefix || vex.pfx, EXC_UD, -1); + /* + * With operand size override disallowed (see above), op_bytes + * should not have changed from its default. + */ + ASSERT(op_bytes == def_op_bytes); vex.raw[0] = modrm; if ( b & 1 ) @@ -1588,8 +1597,14 @@ x86_emulate( op_bytes = 8; } } + else + { + /* Operand size fixed at 4 (no override via W bit). */ + op_bytes = 4; + vex.b = 1; + } } - if ( mode_64bit() && !vex.r ) + if ( !vex.r ) rex_prefix |= REX_R; fail_if(vex.opcx != vex_0f);
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