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SUSE:SLE-12-SP1:GA
xen.8005
540f269e-x86-mwait-idle-Broadwell-support.patch
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File 540f269e-x86-mwait-idle-Broadwell-support.patch of Package xen.8005
References: bsc#1037413 # Commit c645b32ae1f4f4a0e9bd787cc7aab7e2a6e7593c # Date 2014-09-09 18:11:10 +0200 # Author Len Brown <len.brown@intel.com> # Committer Jan Beulich <jbeulich@suse.com> x86/mwait-idle: Broadwell support Broadwell (BDW) is similar to Haswell (HSW), the preceding processor generation. Currently, the only difference in their C-state tables is that PC3 max exit latency is 33usec on HSW and 40usec on BDW. Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com> # Commit e8577050577f703074e8d057096b6f0dffb918c4 # Date 2015-05-20 13:23:17 +0200 # Author Len Brown <len.brown@intel.com> # Committer Jan Beulich <jbeulich@suse.com> mwait-idle: support additional Broadwell model Signed-off-by: Len Brown <len.brown@intel.com> [Linux commit bea57077e44ec9c1e6d3a3c142c8a3c0289e290d] Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -273,6 +273,58 @@ static const struct cpuidle_state hsw_cs {} }; +static const struct cpuidle_state bdw_cstates[] = { + { + .name = "C1-BDW", + .flags = MWAIT2flg(0x00), + .exit_latency = 2, + .target_residency = 2, + }, + { + .name = "C1E-BDW", + .flags = MWAIT2flg(0x01), + .exit_latency = 10, + .target_residency = 20, + }, + { + .name = "C3-BDW", + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 40, + .target_residency = 100, + }, + { + .name = "C6-BDW", + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 133, + .target_residency = 400, + }, + { + .name = "C7s-BDW", + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 166, + .target_residency = 500, + }, + { + .name = "C8-BDW", + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 300, + .target_residency = 900, + }, + { + .name = "C9-BDW", + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 600, + .target_residency = 1800, + }, + { + .name = "C10-BDW", + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 2600, + .target_residency = 7700, + }, + {} +}; + static const struct cpuidle_state atom_cstates[] = { { .name = "C1E-ATM", @@ -436,6 +488,11 @@ static const struct idle_cpu idle_cpu_hs .disable_promotion_to_c1e = 1, }; +static const struct idle_cpu idle_cpu_bdw = { + .state_table = bdw_cstates, + .disable_promotion_to_c1e = 1, +}; + #define ICPU(model, cpu) { 6, model, &idle_cpu_##cpu } static struct intel_idle_id { @@ -459,6 +516,10 @@ static struct intel_idle_id { ICPU(0x3f, hsw), ICPU(0x45, hsw), ICPU(0x46, hsw), + ICPU(0x3d, bdw), + ICPU(0x47, bdw), + ICPU(0x4f, bdw), + ICPU(0x56, bdw), {} };
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