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SUSE:SLE-12-SP1:GA
xen.8005
56c5cfae-x86emul-fix-rIP-handling.patch
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File 56c5cfae-x86emul-fix-rIP-handling.patch of Package xen.8005
# Commit 0640ffb67fb92e2561c63b9308c27b71281fdd72 # Date 2016-02-18 15:05:34 +0100 # Author Jan Beulich <jbeulich@suse.com> # Committer Jan Beulich <jbeulich@suse.com> x86emul: fix rIP handling Deal with rIP just like with any other register: Truncate to designated width upon entry, write back the zero-extended 32-bit value when emulating 32-bit code, and leave the upper 48 bits unchanged for 16-bit code. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -576,7 +576,6 @@ do{ asm volatile ( /* Fetch next part of the instruction being emulated. */ #define insn_fetch_bytes(_size) \ ({ unsigned long _x = 0, _eip = _regs.eip; \ - if ( !mode_64bit() ) _eip = (uint32_t)_eip; /* ignore upper dword */ \ _regs.eip += (_size); /* real hardware doesn't truncate */ \ generate_exception_if((uint8_t)(_regs.eip - ctxt->regs->eip) > 15, \ EXC_GP, 0); \ @@ -1371,6 +1370,10 @@ x86_emulate( #endif } + /* Truncate rIP to def_ad_bytes (2 or 4) if necessary. */ + if ( def_ad_bytes < sizeof(_regs.eip) ) + _regs.eip &= (1UL << (def_ad_bytes * 8)) - 1; + /* Prefix bytes. */ for ( ; ; ) { @@ -3669,6 +3672,21 @@ x86_emulate( /* Commit shadow register state. */ _regs.eflags &= ~EFLG_RF; + switch ( __builtin_expect(def_ad_bytes, sizeof(_regs.eip)) ) + { + uint16_t ip; + + case 2: + ip = _regs.eip; + _regs.eip = ctxt->regs->eip; + *(uint16_t *)&_regs.eip = ip; + break; +#ifdef __x86_64__ + case 4: + _regs.rip = _regs._eip; + break; +#endif + } *ctxt->regs = _regs; done:
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