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SUSE:SLE-12-SP1:GA
xen.8005
5afc13ae-2-x86-express-Xen-SPEC_CTRL-choice-as-...
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File 5afc13ae-2-x86-express-Xen-SPEC_CTRL-choice-as-variable.patch of Package xen.8005
# Commit 66dfae0f32bfbc899c2f3446d5ee57068cb7f957 # Date 2018-05-16 12:19:10 +0100 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/spec_ctrl: Express Xen's choice of MSR_SPEC_CTRL value as a variable At the moment, we have two different encodings of Xen's MSR_SPEC_CTRL value, which is a side effect of how the Spectre series developed. One encoding is via an alias with the bottom bit of bti_ist_info, and can encode IBRS or not, but not other configurations such as STIBP. Break Xen's value out into a separate variable (in the top of stack block for XPTI reasons) and use this instead of bti_ist_info in the IST path. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Wei Liu <wei.liu2@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -34,7 +34,7 @@ static int8_t __initdata opt_ibrs = -1; static bool_t __initdata opt_rsb_native = 1; static bool_t __initdata opt_rsb_vmexit = 1; bool_t __read_mostly opt_ibpb = 1; -int8_t __read_mostly default_xen_ibrs = -1; +int8_t __read_mostly default_xen_spec_ctrl = -1; uint8_t __read_mostly default_xen_rsb = 0; static int __init parse_bti(const char *s) @@ -94,8 +94,8 @@ static void __init print_details(enum in printk("BTI mitigations: Thunk %s, Others:%s%s%s%s\n", thunk == THUNK_NONE ? "N/A" : thunk == THUNK_RETPOLINE ? "RETPOLINE" : "?", - default_xen_ibrs > 0 ? " IBRS+" : - default_xen_ibrs == 0 ? " IBRS-" : "", + default_xen_spec_ctrl < 0 ? "" : + default_xen_spec_ctrl & SPEC_CTRL_IBRS ? " IBRS+" : " IBRS-", opt_ibpb ? " IBPB" : "", default_xen_rsb & XEN_RSB_NATIVE ? " RSB_NATIVE" : "", default_xen_rsb & XEN_RSB_VMEXIT ? " RSB_VMEXIT" : ""); @@ -139,7 +139,7 @@ void __init init_speculation_mitigations * need the IBRS entry/exit logic to virtualise IBRS support for * guests. */ - default_xen_ibrs = ibrs; + default_xen_spec_ctrl = ibrs ? SPEC_CTRL_IBRS : 0; } /* --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -139,7 +139,7 @@ void __dummy__(void) OFFSET(CPUINFO_pv_cr3, struct cpu_info, pv_cr3); OFFSET(CPUINFO_shadow_spec_ctrl, struct cpu_info, shadow_spec_ctrl); OFFSET(CPUINFO_use_shadow_spec_ctrl, struct cpu_info, use_shadow_spec_ctrl); - OFFSET(CPUINFO_xen_ibrs, struct cpu_info, xen_ibrs); + OFFSET(CPUINFO_xen_spec_ctrl, struct cpu_info, xen_spec_ctrl); OFFSET(CPUINFO_xen_rsb, struct cpu_info, xen_rsb); DEFINE(CPUINFO_sizeof, sizeof(struct cpu_info)); BLANK(); --- a/xen/include/asm-x86/current.h +++ b/xen/include/asm-x86/current.h @@ -40,7 +40,7 @@ struct cpu_info { /* See asm-x86/spec_ctrl_asm.h for usage. */ unsigned int shadow_spec_ctrl; bool_t use_shadow_spec_ctrl; - int8_t xen_ibrs; + int8_t xen_spec_ctrl; uint8_t xen_rsb; /* get_stack_bottom() must be 16-byte aligned */ --- a/xen/include/asm-x86/spec_ctrl.h +++ b/xen/include/asm-x86/spec_ctrl.h @@ -27,7 +27,7 @@ void init_speculation_mitigations(void); extern int8_t opt_xpti; extern bool_t opt_ibpb; -extern int8_t default_xen_ibrs; +extern int8_t default_xen_spec_ctrl; extern uint8_t default_xen_rsb; static inline void init_shadow_spec_ctrl_state(void) @@ -35,14 +35,14 @@ static inline void init_shadow_spec_ctrl struct cpu_info *info = get_cpu_info(); info->shadow_spec_ctrl = info->use_shadow_spec_ctrl = 0; - info->xen_ibrs = default_xen_ibrs; + info->xen_spec_ctrl = default_xen_spec_ctrl; info->xen_rsb = default_xen_rsb; } /* WARNING! `ret`, `call *`, `jmp *` not safe after this call. */ static always_inline void spec_ctrl_enter_idle(struct cpu_info *info) { - if ( info->xen_ibrs <= 0 ) + if ( info->xen_spec_ctrl <= 0 ) return; /* @@ -59,7 +59,7 @@ static always_inline void spec_ctrl_ente /* WARNING! `ret`, `call *`, `jmp *` not safe before this call. */ static always_inline void spec_ctrl_exit_idle(struct cpu_info *info) { - if ( info->xen_ibrs <= 0 ) + if ( info->xen_spec_ctrl <= 0 ) return; /* --- a/xen/include/asm-x86/spec_ctrl_asm.h +++ b/xen/include/asm-x86/spec_ctrl_asm.h @@ -131,7 +131,7 @@ * which point we need to save the guest value before setting IBRS for Xen. * Unilaterally saving the guest value is shorter and faster than checking. */ - cmpb $0, CPUINFO_xen_ibrs(%rsp) + cmpb $0, CPUINFO_xen_spec_ctrl(%rsp) jl .Lspec_entry_done\@ mov $MSR_SPEC_CTRL, %ecx @@ -145,7 +145,7 @@ movb %dl, CPUINFO_use_shadow_spec_ctrl(%rsp) /* Load Xen's intended value. */ - movzbl CPUINFO_xen_ibrs(%rsp), %eax + movzbl CPUINFO_xen_spec_ctrl(%rsp), %eax wrmsr .Lspec_entry_done\@: .endm @@ -163,9 +163,9 @@ xor %edx, %edx .if \maybexen - cmp %dl, STACK_CPUINFO_FIELD(xen_ibrs)(%r14) + cmp %dl, STACK_CPUINFO_FIELD(xen_spec_ctrl)(%r14) .else - cmp %dl, CPUINFO_xen_ibrs(%rsp) + cmp %dl, CPUINFO_xen_spec_ctrl(%rsp) .endif jl .Lspec_entry_done\@ @@ -187,9 +187,9 @@ /* Load Xen's intended value. */ .if \maybexen - movzbl STACK_CPUINFO_FIELD(xen_ibrs)(%r14), %eax + movzbl STACK_CPUINFO_FIELD(xen_spec_ctrl)(%r14), %eax .else - movzbl CPUINFO_xen_ibrs(%rsp), %eax + movzbl CPUINFO_xen_spec_ctrl(%rsp), %eax .endif wrmsr .Lspec_entry_done\@: @@ -225,7 +225,7 @@ * guest value. */ xor %edx, %edx - cmp %dl, CPUINFO_xen_ibrs(%rsp) + cmp %dl, CPUINFO_xen_spec_ctrl(%rsp) jl .Lspec_exit_done\@ /* Set up shadow value *before* enabling shadowing. */
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