File U_sna-gen8-BLT-broken-when-address-has-bit-4-se... of Package xf86-video-intel

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File U_sna-gen8-BLT-broken-when-address-has-bit-4-set.patch of Package xf86-video-intel

From 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad Mon Sep 17 00:00:00 2001
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date: Wed, 19 Nov 2014 15:10:05 +0200
Subject: [PATCH] sna: gen8 BLT broken when address has bit 4 set
Git-commit: 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
References: bnc#908326

With bit 4 set in address, the gen8 blitter fails and blits errorneously
into the cacheline preceeding the destination and similarly when reading from
the source, corrupting memory.

V2: Update the destination base offset pattern as revealed
    by igt/tests/gem_userptr_blits/destination-bo-align

V3: Check base address as well

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: xunx.fang@intel.com [v2]
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>

---
 src/sna/kgem.h |   13 +++++++++++++
 1 file changed, 13 insertions(+)

--- a/src/sna/kgem.h
+++ b/src/sna/kgem.h
@@ -548,6 +548,13 @@ static inline bool kgem_bo_blt_pitch_is_
 					   struct kgem_bo *bo)
 {
 	int pitch = bo->pitch;
+
+	if (kgem->gen >= 0100 && pitch & (1 << 4)) { /* bdw is broken */
+		DBG(("%s: can not blt to handle=%d, pitch=%d\n",
+		     __FUNCTION__, bo->handle, pitch));
+		return false;
+	}
+
 	if (kgem->gen >= 040 && bo->tiling)
 		pitch /= 4;
 	if (pitch > MAXSHORT) {
@@ -570,6 +577,12 @@ static inline bool kgem_bo_can_blt(struc
 		return false;
 	}
 
+	if (kgem->gen >= 0100 && bo->proxy && bo->delta & (1 << 4)) {
+		DBG(("%s: can not blt to handle=%d, delta=%d\n",
+		     __FUNCTION__, bo->handle, bo->delta));
+		return false;
+	}
+
 	return kgem_bo_blt_pitch_is_ok(kgem, bo);
 }

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File U_sna-gen8-BLT-broken-when-address-has-bit-4-set.patch of Package xf86-video-intel

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