File backport-llvm-r203234 of Package llvm.7809

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File backport-llvm-r203234 of Package llvm.7809

------------------------------------------------------------------------
r203234 | rsandifo | 2014-03-07 12:34:35 +0100 (Fri, 07 Mar 2014) | 8 lines

[SystemZ] Move sign_extend optimization to PerformDAGCombine

The target was marking SIGN_EXTEND as Custom because it wanted to optimize
certain sign-extended shifts.  In all other respects the extension is Legal,
so it'd be better to do the optimization in PerformDAGCombine instead.

No functional change intended.

------------------------------------------------------------------------
Index: lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.h.orig
+++ lib/Target/SystemZ/SystemZISelLowering.h
@@ -253,6 +253,8 @@ public:
   virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
                                               SelectionDAG &DAG) const
     LLVM_OVERRIDE;
+  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
+    LLVM_OVERRIDE;
 
 private:
   const SystemZSubtarget &Subtarget;
@@ -279,7 +281,6 @@ private:
   SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
-  SDValue lowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
Index: lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.cpp.orig
+++ lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -210,9 +210,6 @@ SystemZTargetLowering::SystemZTargetLowe
   // Give LowerOperation the chance to replace 64-bit ORs with subregs.
   setOperationAction(ISD::OR, MVT::i64, Custom);
 
-  // Give LowerOperation the chance to optimize SIGN_EXTEND sequences.
-  setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
-
   // FIXME: Can we support these natively?
   setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
@@ -294,6 +291,9 @@ SystemZTargetLowering::SystemZTargetLowe
   setOperationAction(ISD::VACOPY,  MVT::Other, Custom);
   setOperationAction(ISD::VAEND,   MVT::Other, Expand);
 
+  // Codes for which we want to perform some z-specific combinations.
+  setTargetDAGCombine(ISD::SIGN_EXTEND);
+
   // We want to use MVC in preference to even a single load/store pair.
   MaxStoresPerMemcpy = 0;
   MaxStoresPerMemcpyOptSize = 0;
@@ -2178,36 +2178,6 @@ SDValue SystemZTargetLowering::lowerOR(S
                                    MVT::i64, HighOp, Low32);
 }
 
-SDValue SystemZTargetLowering::lowerSIGN_EXTEND(SDValue Op,
-                                                SelectionDAG &DAG) const {
-  // Convert (sext (ashr (shl X, C1), C2)) to
-  // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
-  // cheap as narrower ones.
-  SDValue N0 = Op.getOperand(0);
-  EVT VT = Op.getValueType();
-  if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
-    ConstantSDNode *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
-    SDValue Inner = N0.getOperand(0);
-    if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
-      ConstantSDNode *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1));
-      if (ShlAmt) {
-        unsigned Extra = (VT.getSizeInBits() -
-                          N0.getValueType().getSizeInBits());
-        unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
-        unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
-        EVT ShiftVT = N0.getOperand(1).getValueType();
-        SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
-                                  Inner.getOperand(0));
-        SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
-                                  DAG.getConstant(NewShlAmt, ShiftVT));
-        return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
-                           DAG.getConstant(NewSraAmt, ShiftVT));
-      }
-    }
-  }
-  return SDValue();
-}
-
 // Op is an atomic load.  Lower it into a normal volatile load.
 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
                                                 SelectionDAG &DAG) const {
@@ -2460,8 +2430,6 @@ SDValue SystemZTargetLowering::LowerOper
     return lowerUDIVREM(Op, DAG);
   case ISD::OR:
     return lowerOR(Op, DAG);
-  case ISD::SIGN_EXTEND:
-    return lowerSIGN_EXTEND(Op, DAG);
   case ISD::ATOMIC_SWAP:
     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
   case ISD::ATOMIC_STORE:
@@ -2554,6 +2522,40 @@ const char *SystemZTargetLowering::getTa
 #undef OPCODE
 }
 
+SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
+                                                 DAGCombinerInfo &DCI) const {
+  SelectionDAG &DAG = DCI.DAG;
+  unsigned Opcode = N->getOpcode();
+  if (Opcode == ISD::SIGN_EXTEND) {
+    // Convert (sext (ashr (shl X, C1), C2)) to
+    // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
+    // cheap as narrower ones.
+    SDValue N0 = N->getOperand(0);
+    EVT VT = N->getValueType(0);
+    if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
+      ConstantSDNode *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+      SDValue Inner = N0.getOperand(0);
+      if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
+        if (ConstantSDNode *ShlAmt =
+              dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
+          unsigned Extra = (VT.getSizeInBits() -
+                            N0.getValueType().getSizeInBits());
+          unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
+          unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
+          EVT ShiftVT = N0.getOperand(1).getValueType();
+          SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
+                                    Inner.getOperand(0));
+          SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
+                                    DAG.getConstant(NewShlAmt, ShiftVT));
+          return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
+                             DAG.getConstant(NewSraAmt, ShiftVT));
+        }
+      }
+    }
+  }
+  return SDValue();
+}
+
 //===----------------------------------------------------------------------===//
 // Custom insertion
 //===----------------------------------------------------------------------===//

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