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SUSE:SLE-12-SP2:Update
llvm.7809
backport-llvm-r236432
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File backport-llvm-r236432 of Package llvm.7809
------------------------------------------------------------------------ r236432 | uweigand | 2015-05-04 19:40:53 +0200 (Mon, 04 May 2015) | 11 lines [SystemZ] Clean up AsmParser isMem() handling We know what MemoryKind an operand has at the time we construct it, so we might as well just record it in an unused part of the structure. This makes it easier to add scatter/gather addresses later. No behavioral change intended. Patch originally by Richard Sandiford. ------------------------------------------------------------------------ Index: lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp =================================================================== --- lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp.orig +++ lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -85,14 +85,14 @@ private: }; // Base + Disp + Index, where Base and Index are LLVM registers or 0. - // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg). - // Length is the operand length for D(L,B)-style operands, otherwise - // it is null. + // MemKind says what type of memory this is and RegKind says what type + // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand + // length for D(L,B)-style operands, otherwise it is null. struct MemOp { unsigned Base : 8; unsigned Index : 8; + unsigned MemKind : 8; unsigned RegKind : 8; - unsigned Unused : 8; const MCExpr *Disp; const MCExpr *Length; }; @@ -157,11 +157,12 @@ public: Op->Imm = Expr; return Op; } - static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base, - const MCExpr *Disp, unsigned Index, - const MCExpr *Length, SMLoc StartLoc, - SMLoc EndLoc) { + static SystemZOperand *createMem(MemoryKind MemKind, RegisterKind RegKind, + unsigned Base, const MCExpr *Disp, + unsigned Index, const MCExpr *Length, + SMLoc StartLoc, SMLoc EndLoc) { SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc); + Op->Mem.MemKind = MemKind; Op->Mem.RegKind = RegKind; Op->Mem.Base = Base; Op->Mem.Index = Index; @@ -225,20 +226,24 @@ public: virtual bool isMem() const LLVM_OVERRIDE { return Kind == KindMem; } - bool isMem(RegisterKind RegKind, MemoryKind MemKind) const { + bool isMem(MemoryKind MemKind) const { return (Kind == KindMem && - Mem.RegKind == RegKind && - (MemKind == BDXMem || !Mem.Index) && - (MemKind == BDLMem) == (Mem.Length != 0)); + (Mem.MemKind == MemKind || + // A BDMem can be treated as a BDXMem in which the index + // register field is 0. + (Mem.MemKind == BDMem && MemKind == BDXMem))); + } + bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { + return isMem(MemKind) && Mem.RegKind == RegKind; } - bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const { - return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff); + bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { + return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); } - bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const { - return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287); + bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { + return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); } bool isMemDisp12Len8(RegisterKind RegKind) const { - return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100); + return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100); } // Override MCParsedAsmOperand. @@ -263,20 +268,20 @@ public: } void addBDAddrOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands"); - assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type"); + assert(isMem(BDMem) && "Invalid operand type"); Inst.addOperand(MCOperand::CreateReg(Mem.Base)); addExpr(Inst, Mem.Disp); } void addBDXAddrOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands"); - assert(Kind == KindMem && "Invalid operand type"); + assert(isMem(BDXMem) && "Invalid operand type"); Inst.addOperand(MCOperand::CreateReg(Mem.Base)); addExpr(Inst, Mem.Disp); Inst.addOperand(MCOperand::CreateReg(Mem.Index)); } void addBDLAddrOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands"); - assert(Kind == KindMem && "Invalid operand type"); + assert(isMem(BDLMem) && "Invalid operand type"); Inst.addOperand(MCOperand::CreateReg(Mem.Base)); addExpr(Inst, Mem.Disp); addExpr(Inst, Mem.Length); @@ -301,12 +306,12 @@ public: bool isFP32() const { return isReg(FP32Reg); } bool isFP64() const { return isReg(FP64Reg); } bool isFP128() const { return isReg(FP128Reg); } - bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); } - bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); } - bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); } - bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); } - bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); } - bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); } + bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); } + bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); } + bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); } + bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); } + bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); } + bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); } bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); } bool isU4Imm() const { return isImm(0, 15); } bool isU6Imm() const { return isImm(0, 63); } @@ -351,8 +356,7 @@ private: OperandMatchResultTy parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, - const unsigned *Regs, RegisterKind RegKind, - MemoryKind MemKind); + MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind); OperandMatchResultTy parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands, @@ -432,19 +436,19 @@ public: } OperandMatchResultTy parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem); + return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg); } OperandMatchResultTy parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem); + return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg); } OperandMatchResultTy parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem); + return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg); } OperandMatchResultTy parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem); + return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg); } OperandMatchResultTy parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands); @@ -605,8 +609,8 @@ bool SystemZAsmParser::parseAddress(unsi // are as above. SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, - const unsigned *Regs, RegisterKind RegKind, - MemoryKind MemKind) { + MemoryKind MemKind, const unsigned *Regs, + RegisterKind RegKind) { SMLoc StartLoc = Parser.getTok().getLoc(); unsigned Base, Index; const MCExpr *Disp; @@ -634,8 +638,9 @@ SystemZAsmParser::parseAddress(SmallVect SMLoc EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index, - Length, StartLoc, EndLoc)); + Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, + Index, Length, StartLoc, + EndLoc)); return MatchOperand_Success; }
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