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SUSE:SLE-12-SP2:Update
xen.6649
5a6b36cd-3-x86-migrate-MSR_SPEC_CTRL.patch
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File 5a6b36cd-3-x86-migrate-MSR_SPEC_CTRL.patch of Package xen.6649
# Commit 0cf2a4eb769302b7d7d7835540e7b2f15006df30 # Date 2018-01-26 14:10:21 +0000 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/migrate: Move MSR_SPEC_CTRL on migrate Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Wei Liu <wei.liu2@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1261,6 +1261,8 @@ long arch_do_domctl( vmsrs->msr_count = nr_msrs; else { + uint32_t edx, dummy; + i = 0; vcpu_pause(v); @@ -1298,6 +1300,21 @@ long arch_do_domctl( } } + domain_cpuid(d, 7, 0, &dummy, &dummy, &dummy, &edx); + if ( (edx & cpufeat_mask(X86_FEATURE_IBRSB)) && + v->arch.spec_ctrl ) + { + if ( i < vmsrs->msr_count && !ret ) + { + msr.index = MSR_SPEC_CTRL; + msr.reserved = 0; + msr.value = v->arch.spec_ctrl; + if ( copy_to_guest_offset(vmsrs->msrs, i, &msr, 1) ) + ret = -EFAULT; + } + ++i; + } + vcpu_unpause(v); if ( i > vmsrs->msr_count && !ret ) @@ -1325,6 +1342,20 @@ long arch_do_domctl( switch ( msr.index ) { + case MSR_SPEC_CTRL: + if ( !boot_cpu_has(X86_FEATURE_IBRSB) ) + break; /* MSR available? */ + + /* + * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. + * ignored) when STIBP isn't enumerated in hardware. + */ + + if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) ) + break; + v->arch.spec_ctrl = msr.value; + continue; + case MSR_AMD64_DR0_ADDRESS_MASK: if ( !boot_cpu_has(X86_FEATURE_DBEXT) || (msr.value >> 32) ) --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -824,14 +824,24 @@ static bool_t vmx_set_guest_bndcfgs(stru static unsigned int __init vmx_init_msr(void) { - return (cpu_has_mpx && cpu_has_vmx_mpx) + + return !!boot_cpu_has(X86_FEATURE_IBRSB) + + (cpu_has_mpx && cpu_has_vmx_mpx) + (cpu_has_xsaves && cpu_has_vmx_xsaves); } static void vmx_save_msr(struct vcpu *v, struct hvm_msr *ctxt) { + uint32_t edx, dummy; + vmx_vmcs_enter(v); + domain_cpuid(v->domain, 7, 0, &dummy, &dummy, &dummy, &edx); + if ( (edx & cpufeat_mask(X86_FEATURE_IBRSB)) && v->arch.spec_ctrl ) + { + ctxt->msr[ctxt->count].index = MSR_SPEC_CTRL; + ctxt->msr[ctxt->count++].val = v->arch.spec_ctrl; + } + if ( cpu_has_mpx && cpu_has_vmx_mpx ) { __vmread(GUEST_BNDCFGS, &ctxt->msr[ctxt->count].val); @@ -860,6 +870,19 @@ static int vmx_load_msr(struct vcpu *v, { switch ( ctxt->msr[i].index ) { + case MSR_SPEC_CTRL: + if ( !boot_cpu_has(X86_FEATURE_IBRSB) ) + err = -ENXIO; /* MSR available? */ + /* + * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. + * ignored) when STIBP isn't enumerated in hardware. + */ + else if ( ctxt->msr[i].val & + ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) ) + err = -ENXIO; + else + v->arch.spec_ctrl = ctxt->msr[i].val; + break; case MSR_IA32_BNDCFGS: if ( !vmx_set_guest_bndcfgs(v, ctxt->msr[i].val) && ctxt->msr[i].val )
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