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SUSE:SLE-12-SP2:Update
xen.7652
5ad8c3a7-x86-spec_ctrl-update-retpoline-decisio...
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File 5ad8c3a7-x86-spec_ctrl-update-retpoline-decision-making.patch of Package xen.7652
# Commit 1232378bd2fef45f613db049b33852fdf84d7ddf # Date 2018-04-19 17:28:23 +0100 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/spec_ctrl: Updates to retpoline-safety decision making All of this is as recommended by the Intel whitepaper: https://software.intel.com/sites/default/files/managed/1d/46/Retpoline-A-Branch-Target-Injection-Mitigation.pdf The 'RSB Alternative' bit in MSR_ARCH_CAPABILITIES may be set by a hypervisor to indicate that the virtual machine may migrate to a processor which isn't retpoline-safe. Introduce a shortened name (to reduce code volume), treat it as authorative in retpoline_safe(), and print its value along with the other ARCH_CAPS bits. The exact processor models which do have RSB semantics which fall back to BTB predictions are enumerated, and include Kabylake and Coffeelake. Leave a printk() in the default case to help identify cases which aren't covered. The exact microcode versions from Broadwell RSB-safety are taken from the referenced microcode update file (adjusting for the known-bad microcode versions). Despite the exact wording of the text, it is only Broadwell processors which need a microcode check. In practice, this means that all Broadwell hardware with up-to-date microcode will use retpoline in preference to IBRS, which will be a performance improvement for desktop and server systems which would previously always opt for IBRS over retpoline. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> # Commit 27170adb54a558e11defcd51989326a9beb95afe # Date 2018-04-24 13:34:12 +0100 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/spec_ctrl: Fix typo in ARCH_CAPS decode Reported-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com> --- sle12sp2.orig/xen/arch/x86/spec_ctrl.c 2018-04-18 14:55:42.000000000 +0200 +++ sle12sp2/xen/arch/x86/spec_ctrl.c 2018-04-27 15:59:11.000000000 +0200 @@ -97,12 +97,13 @@ static void __init print_details(enum in printk(XENLOG_DEBUG "Speculative mitigation facilities:\n"); /* Hardware features which pertain to speculative mitigations. */ - printk(XENLOG_DEBUG " Hardware features:%s%s%s%s%s\n", + printk(XENLOG_DEBUG " Hardware features:%s%s%s%s%s%s\n", (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "", (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "", (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "", (caps & ARCH_CAPABILITIES_IBRS_ALL) ? " IBRS_ALL" : "", - (caps & ARCH_CAPABILITIES_RDCL_NO) ? " RDCL_NO" : ""); + (caps & ARCH_CAPABILITIES_RDCL_NO) ? " RDCL_NO" : "", + (caps & ARCH_CAPS_RSBA) ? " RSBA" : ""); /* Compiled-in support which pertains to BTI mitigations. */ if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) ) @@ -135,6 +136,20 @@ static bool_t __init retpoline_safe(void boot_cpu_data.x86 != 6 ) return 0; + if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) + { + uint64_t caps; + + rdmsrl(MSR_ARCH_CAPABILITIES, caps); + + /* + * RBSA may be set by a hypervisor to indicate that we may move to a + * processor which isn't retpoline-safe. + */ + if ( caps & ARCH_CAPS_RSBA ) + return 0; + } + switch ( boot_cpu_data.x86_model ) { case 0x17: /* Penryn */ @@ -161,18 +176,40 @@ static bool_t __init retpoline_safe(void * versions. */ case 0x3d: /* Broadwell */ - return ucode_rev >= 0x28; + return ucode_rev >= 0x2a; case 0x47: /* Broadwell H */ - return ucode_rev >= 0x1b; + return ucode_rev >= 0x1d; case 0x4f: /* Broadwell EP/EX */ - return ucode_rev >= 0xb000025; + return ucode_rev >= 0xb000021; case 0x56: /* Broadwell D */ - return 0; /* TBD. */ + switch ( boot_cpu_data.x86_mask ) + { + case 2: return ucode_rev >= 0x15; + case 3: return ucode_rev >= 0x7000012; + case 4: return ucode_rev >= 0xf000011; + case 5: return ucode_rev >= 0xe000009; + default: + printk("Unrecognised CPU stepping %#x - assuming not reptpoline safe\n", + boot_cpu_data.x86_mask); + return 0; + } + break; /* - * Skylake and later processors are not retpoline-safe. + * Skylake, Kabylake and Cannonlake processors are not retpoline-safe. */ + case 0x4e: + case 0x55: + case 0x5e: + case 0x66: + case 0x67: + case 0x8e: + case 0x9e: + return 0; + default: + printk("Unrecognised CPU model %#x - assuming not reptpoline safe\n", + boot_cpu_data.x86_model); return 0; } } --- sle12sp2.orig/xen/include/asm-x86/msr-index.h 2018-04-18 14:55:19.000000000 +0200 +++ sle12sp2/xen/include/asm-x86/msr-index.h 2018-04-27 15:59:11.000000000 +0200 @@ -42,6 +42,7 @@ #define MSR_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAPABILITIES_RDCL_NO (_AC(1, ULL) << 0) #define ARCH_CAPABILITIES_IBRS_ALL (_AC(1, ULL) << 1) +#define ARCH_CAPS_RSBA (_AC(1, ULL) << 2) /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1
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