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SUSE:SLE-12-SP2:Update
xen.7652
xsa260-2.patch
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File xsa260-2.patch of Package xen.7652
From: Andrew Cooper <andrew.cooper3@citrix.com> Subject: x86/pv: Move exception injection into {,compat_}test_all_events() This allows paths to jump straight to {,compat_}test_all_events() and have injection of pending exceptions happen automatically, rather than requiring all calling paths to handle exceptions themselves. The normal exception path is simplified as a result, and compat_post_handle_exception() is removed entirely. This is part of XSA-260 / CVE-2018-8897. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_64/compat/entry.S +++ b/xen/arch/x86/x86_64/compat/entry.S @@ -107,6 +107,12 @@ ENTRY(compat_test_all_events) leaq irq_stat+IRQSTAT_softirq_pending(%rip),%rcx cmpl $0,(%rcx,%rax,1) jne compat_process_softirqs + + /* Inject exception if pending. */ + lea VCPU_trap_bounce(%rbx), %rdx + testb $TBF_EXCEPTION, TRAPBOUNCE_flags(%rdx) + jnz .Lcompat_process_trapbounce + testb $1,VCPU_mce_pending(%rbx) jnz compat_process_mce .Lcompat_test_guest_nmi: @@ -136,6 +142,15 @@ compat_process_softirqs: call do_softirq jmp compat_test_all_events + ALIGN +/* %rbx: struct vcpu, %rdx: struct trap_bounce */ +.Lcompat_process_trapbounce: + sti +.Lcompat_bounce_exception: + call compat_create_bounce_frame + movb $0, TRAPBOUNCE_flags(%rdx) + jmp compat_test_all_events + ALIGN /* %rbx: struct vcpu */ compat_process_mce: @@ -260,15 +275,6 @@ ENTRY(cr4_pv32_restore) xor %eax, %eax ret -/* %rdx: trap_bounce, %rbx: struct vcpu */ -ENTRY(compat_post_handle_exception) - testb $TBF_EXCEPTION,TRAPBOUNCE_flags(%rdx) - jz compat_test_all_events -.Lcompat_bounce_exception: - call compat_create_bounce_frame - movb $0,TRAPBOUNCE_flags(%rdx) - jmp compat_test_all_events - /* See lstar_enter for entry register state. */ ENTRY(cstar_enter) /* sti could live here when we don't switch page tables below. */ --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -253,6 +253,12 @@ test_all_events: leaq irq_stat+IRQSTAT_softirq_pending(%rip),%rcx cmpl $0,(%rcx,%rax,1) jne process_softirqs + + /* Inject exception if pending. */ + lea VCPU_trap_bounce(%rbx), %rdx + testb $TBF_EXCEPTION, TRAPBOUNCE_flags(%rdx) + jnz .Lprocess_trapbounce + testb $1,VCPU_mce_pending(%rbx) jnz process_mce .Ltest_guest_nmi: @@ -281,6 +287,15 @@ process_softirqs: jmp test_all_events ALIGN +/* %rbx: struct vcpu, %rdx struct trap_bounce */ +.Lprocess_trapbounce: + sti +.Lbounce_exception: + call create_bounce_frame + movb $0, TRAPBOUNCE_flags(%rdx) + jmp test_all_events + + ALIGN /* %rbx: struct vcpu */ process_mce: testb $1 << VCPU_TRAP_MCE,VCPU_async_exception_mask(%rbx) @@ -698,15 +713,9 @@ handle_exception_saved: mov %r15, STACK_CPUINFO_FIELD(xen_cr3)(%r14) testb $3,UREGS_cs(%rsp) jz restore_all_xen - leaq VCPU_trap_bounce(%rbx),%rdx movq VCPU_domain(%rbx),%rax testb $1,DOMAIN_is_32bit_pv(%rax) - jnz compat_post_handle_exception - testb $TBF_EXCEPTION,TRAPBOUNCE_flags(%rdx) - jz test_all_events -.Lbounce_exception: - call create_bounce_frame - movb $0,TRAPBOUNCE_flags(%rdx) + jnz compat_test_all_events jmp test_all_events /* No special register assumptions. */
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