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SUSE:SLE-12-SP3:GA
qemu-linux-user.11147
0442-x86-add-infrastructure-for-7_0_EDX-.patch
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File 0442-x86-add-infrastructure-for-7_0_EDX-.patch of Package qemu-linux-user.11147
From 012edfd63a6d5b8d5b0ff634ab386abfcedaf094 Mon Sep 17 00:00:00 2001 From: Luwei Kang <luwei.kang@intel.com> Date: Mon, 31 Oct 2016 16:27:26 +0800 Subject: [PATCH] x86: add infrastructure for 7_0_EDX features The spec can be found in Intel Software Developer Manual or in Instruction Set Extensions Programming Reference. Signed-off-by: Piotr Luc <piotr.luc@intel.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Message-Id: <1477902446-5932-1-git-send-email-he.chen@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> (cherry picked from commit 95ea69fb46266aaa46d0c8b7f0ba8c4903dbe4e3) [BR: BSC#1068032 CVE-2017-5715 - orig patch modified to not provide new feature, just infrastructure, and change to match current code's feat_name type] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target-i386/cpu.c | 21 ++++++++++++++++++++- target-i386/cpu.h | 1 + 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 13f7d6cefc..1b4d450eb8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -262,6 +262,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; +static const char *cpuid_7_0_edx_feature_name[] = { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + typedef struct FeatureWordInfo { const char **feat_names; uint32_t cpuid_eax; /* Input EAX for CPUID */ @@ -305,6 +316,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_needs_ecx = true, .cpuid_ecx = 0, .cpuid_reg = R_EBX, }, + [FEAT_7_0_EDX] = { + .feat_names = cpuid_7_0_edx_feature_name, + .cpuid_eax = 7, + .cpuid_needs_ecx = true, .cpuid_ecx = 0, + .cpuid_reg = R_EDX, + }, }; typedef struct X86RegisterInfo32 { @@ -594,6 +611,7 @@ struct X86CPUDefinition { CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ +#define TCG_7_0_EDX_FEATURES 0 static X86CPUDefinition builtin_x86_defs[] = { { @@ -2202,7 +2220,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *eax = 0; /* Maximum ECX value for sub-leaves */ *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ *ecx = 0; /* Reserved */ - *edx = 0; /* Reserved */ + *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ } else { *eax = 0; *ebx = 0; @@ -2616,6 +2634,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->features[FEAT_1_EDX] &= TCG_FEATURES; env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES; env->features[FEAT_7_0_EBX] &= TCG_7_0_EBX_FEATURES; + env->features[FEAT_7_0_EDX] &= TCG_7_0_EDX_FEATURES; env->features[FEAT_8000_0001_EDX] &= TCG_EXT2_FEATURES; env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES; env->features[FEAT_SVM] &= TCG_SVM_FEATURES; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2935be51d9..fa162f1d27 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -399,6 +399,7 @@ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ FEAT_1_ECX, /* CPUID[1].ECX */ FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ + FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
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