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SUSE:SLE-12-SP4:Update
qemu.7436
0281-i386-Add-bit-2-of-SPEC_CTRL-MSR-sup.patch
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File 0281-i386-Add-bit-2-of-SPEC_CTRL-MSR-sup.patch of Package qemu.7436
From 32214e669413abbb7774e9f98693921bdbe58518 Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Date: Wed, 11 Apr 2018 17:26:51 -0400 Subject: [PATCH] i386: Add bit(2) of SPEC_CTRL MSR support - SSBD i386: Add bit(2) of SPEC_CTRL MSR support - Reduced Data Speculation Now users can do: cpu host,+spec-ctrl,+ssbd to have both IBRS and SSBD support. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> [BR: BSC#1092885 CVE-2018-3639] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target-i386/cpu.c | 2 +- target-i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b840868c3e..461fd48207 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -289,7 +289,7 @@ static const char *cpuid_7_0_edx_feature_name[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "ssbd", }; static const char *cpuid_apm_edx_feature_name[] = { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index d19a7f1760..88e1fdc2cf 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -611,6 +611,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4) #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
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