File xsa297-0d.patch of Package xen.17654

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File xsa297-0d.patch of Package xen.17654

x86/spec-ctrl: Misc non-functional cleanup

* Identify BTI in the spec_ctrl_{enter,exit}_idle() comments, as other
   mitigations will shortly appear.
 * Use alternative_input() and cover the lack of memory cobber with a further
   barrier.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/include/asm-x86/spec_ctrl.h
+++ b/xen/include/asm-x86/spec_ctrl.h
@@ -61,6 +61,8 @@ static always_inline void spec_ctrl_ente
     uint32_t val = 0;
 
     /*
+     * Branch Target Injection:
+     *
      * Latch the new shadow value, then enable shadowing, then update the MSR.
      * There are no SMP issues here; only local processor ordering concerns.
      */
@@ -68,10 +70,10 @@ static always_inline void spec_ctrl_ente
     barrier();
     info->spec_ctrl_flags |= SCF_use_shadow;
     barrier();
-    asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", %c3)
-                   :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
-                      "i" (X86_FEATURE_SC_MSR_IDLE)
-                   : "memory" );
+    alternative_input(ASM_NOP3, "wrmsr", %c3,
+                      "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
+                      "i" (X86_FEATURE_SC_MSR_IDLE));
+    barrier();
 }
 
 /* WARNING! `ret`, `call *`, `jmp *` not safe before this call. */
@@ -80,15 +82,17 @@ static always_inline void spec_ctrl_exit
     uint32_t val = info->xen_spec_ctrl;
 
     /*
+     * Branch Target Injection:
+     *
      * Disable shadowing before updating the MSR.  There are no SMP issues
      * here; only local processor ordering concerns.
      */
     info->spec_ctrl_flags &= ~SCF_use_shadow;
     barrier();
-    asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", %c3)
-                   :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
-                      "i" (X86_FEATURE_SC_MSR_IDLE)
-                   : "memory" );
+    alternative_input(ASM_NOP3, "wrmsr", %c3,
+                      "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
+                      "i" (X86_FEATURE_SC_MSR_IDLE));
+    barrier();
 }
 
 #endif /* !__X86_SPEC_CTRL_H__ */

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