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llvm-mainline-backports.patch
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File llvm-mainline-backports.patch of Package llvm
Backports of (parts of) the following LLVM mainline SVN revisions: 202861, 203580, 203664, 204507, 204614, 204634, 208413, 209662, 210271, 210282, 210297, 210336, 210474, 210493, 210536, 211111, 211170, 211171, 211172, 211174, 211190, 211193, 211203, 211368, 211382, 211384, 211492, 211493, 211494, 211495, 211497, 211627, 211779, 211781, 211885, 211897, 212274, 212476, 212477, 212478, 212547, 212832, 212834, 213482, 213483, 213484, 213485, 213487, 213489, 213490, 213491, 213492, 213493, 213915, 214429, 214714, 214716, 214718, 214721, 214800, 214923 Index: llvm-suse/include/llvm/MC/MCELF.h =================================================================== --- llvm-suse.orig/include/llvm/MC/MCELF.h +++ llvm-suse/include/llvm/MC/MCELF.h @@ -27,9 +27,9 @@ class MCELF { static void SetType(MCSymbolData &SD, unsigned Type); static unsigned GetType(const MCSymbolData &SD); static void SetVisibility(MCSymbolData &SD, unsigned Visibility); - static unsigned GetVisibility(MCSymbolData &SD); + static unsigned GetVisibility(const MCSymbolData &SD); static void setOther(MCSymbolData &SD, unsigned Other); - static unsigned getOther(MCSymbolData &SD); + static unsigned getOther(const MCSymbolData &SD); }; } Index: llvm-suse/include/llvm/Object/ELFObjectFile.h =================================================================== --- llvm-suse.orig/include/llvm/Object/ELFObjectFile.h +++ llvm-suse/include/llvm/Object/ELFObjectFile.h @@ -62,6 +62,7 @@ protected: virtual error_code getSymbolAlignment(DataRefImpl Symb, uint32_t &Res) const; virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const; virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const; + virtual error_code getSymbolOther(DataRefImpl Symb, uint8_t &Res) const; virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const; virtual error_code getSymbolSection(DataRefImpl Symb, @@ -191,6 +192,11 @@ public: virtual unsigned getArch() const; virtual StringRef getLoadName() const; + error_code getPlatformFlags(unsigned &Result) const { + Result = EF.getHeader()->e_flags; + return object_error::success; + } + const ELFFile<ELFT> *getELFFile() const { return &EF; } bool isDyldType() const { return isDyldELFObject; } @@ -337,6 +343,13 @@ error_code ELFObjectFile<ELFT>::getSymbo return object_error::success; } +template <class ELFT> +error_code ELFObjectFile<ELFT>::getSymbolOther(DataRefImpl Symb, + uint8_t &Result) const { + Result = toELFSymIter(Symb)->st_other; + return object_error::success; +} + template <class ELFT> error_code ELFObjectFile<ELFT>::getSymbolType(DataRefImpl Symb, SymbolRef::Type &Result) const { Index: llvm-suse/include/llvm/Object/ObjectFile.h =================================================================== --- llvm-suse.orig/include/llvm/Object/ObjectFile.h +++ llvm-suse/include/llvm/Object/ObjectFile.h @@ -220,6 +220,7 @@ public: error_code getAlignment(uint32_t &Result) const; error_code getSize(uint64_t &Result) const; error_code getType(SymbolRef::Type &Result) const; + error_code getOther(uint8_t &Result) const; /// Get symbol flags (bitwise OR of SymbolRef::Flags) error_code getFlags(uint32_t &Result) const; @@ -297,6 +298,9 @@ protected: virtual error_code getSymbolSection(DataRefImpl Symb, section_iterator &Res) const = 0; virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const = 0; + virtual error_code getSymbolOther(DataRefImpl Symb, uint8_t &Res) const { + return object_error::invalid_file_type; + } // Same as above for SectionRef. friend class SectionRef; @@ -372,6 +376,12 @@ public: /// LC_ID_DYLIB (install name) on MachO. virtual StringRef getLoadName() const = 0; + /// Returns platform-specific object flags, if any. + virtual error_code getPlatformFlags(unsigned &Result) const { + Result = 0; + return object_error::invalid_file_type; + } + /// @returns Pointer to ObjectFile subclass to handle this type of object. /// @param ObjectPath The path to the object file. ObjectPath.isObject must /// return true. @@ -442,6 +452,10 @@ inline error_code SymbolRef::getValue(ui return OwningObject->getSymbolValue(SymbolPimpl, Val); } +inline error_code SymbolRef::getOther(uint8_t &Result) const { + return OwningObject->getSymbolOther(SymbolPimpl, Result); +} + inline DataRefImpl SymbolRef::getRawDataRefImpl() const { return SymbolPimpl; } Index: llvm-suse/include/llvm/Object/RelocVisitor.h =================================================================== --- llvm-suse.orig/include/llvm/Object/RelocVisitor.h +++ llvm-suse/include/llvm/Object/RelocVisitor.h @@ -215,12 +215,14 @@ private: /// PPC64 ELF RelocToApply visitELF_PPC64_ADDR32(RelocationRef R, uint64_t Value) { - int64_t Addend = getAddend64BE(R); + int64_t Addend; + getELFRelocationAddend(R, Addend); uint32_t Res = (Value + Addend) & 0xFFFFFFFF; return RelocToApply(Res, 4); } RelocToApply visitELF_PPC64_ADDR64(RelocationRef R, uint64_t Value) { - int64_t Addend = getAddend64BE(R); + int64_t Addend; + getELFRelocationAddend(R, Addend); return RelocToApply(Value + Addend, 8); } Index: llvm-suse/include/llvm/Support/ELF.h =================================================================== --- llvm-suse.orig/include/llvm/Support/ELF.h +++ llvm-suse/include/llvm/Support/ELF.h @@ -474,6 +474,37 @@ enum { R_PPC_REL16_HA = 252 }; +// Specific e_flags for PPC64 +enum { + // e_flags bits specifying ABI: + // 1 for original ABI using function descriptors, + // 2 for revised ABI without function descriptors, + // 0 for unspecified or not using any features affected by the differences. + EF_PPC64_ABI = 3 +}; + +// Special values for the st_other field in the symbol table entry for PPC64. +enum { + STO_PPC64_LOCAL_BIT = 5, + STO_PPC64_LOCAL_MASK = (7 << STO_PPC64_LOCAL_BIT) +}; +static inline int64_t +decodePPC64LocalEntryOffset(unsigned Other) { + unsigned Val = (Other & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT; + return ((1 << Val) >> 2) << 2; +} +static inline unsigned +encodePPC64LocalEntryOffset(int64_t Offset) { + unsigned Val = (Offset >= 4 * 4 + ? (Offset >= 8 * 4 + ? (Offset >= 16 * 4 ? 6 : 5) + : 4) + : (Offset >= 2 * 4 + ? 3 + : (Offset >= 1 * 4 ? 2 : 0))); + return Val << STO_PPC64_LOCAL_BIT; +} + // ELF Relocation types for PPC64 enum { R_PPC64_NONE = 0, Index: llvm-suse/include/llvm/Target/TargetCallingConv.h =================================================================== --- llvm-suse.orig/include/llvm/Target/TargetCallingConv.h +++ llvm-suse/include/llvm/Target/TargetCallingConv.h @@ -44,8 +44,12 @@ namespace ISD { static const uint64_t SplitOffs = 11; static const uint64_t OrigAlign = 0x1FULL<<27; static const uint64_t OrigAlignOffs = 27; - static const uint64_t ByValSize = 0xffffffffULL<<32; ///< Struct size + static const uint64_t ByValSize = 0x3fffffffULL<<32; ///< Struct size static const uint64_t ByValSizeOffs = 32; + static const uint64_t InConsecutiveRegsLast = 0x1ULL<<62; ///< Struct size + static const uint64_t InConsecutiveRegsLastOffs = 62; + static const uint64_t InConsecutiveRegs = 0x1ULL<<63; ///< Struct size + static const uint64_t InConsecutiveRegsOffs = 63; static const uint64_t One = 1ULL; ///< 1 of this type, for shifts @@ -74,6 +78,12 @@ namespace ISD { bool isReturned() const { return Flags & Returned; } void setReturned() { Flags |= One << ReturnedOffs; } + bool isInConsecutiveRegs() const { return Flags & InConsecutiveRegs; } + void setInConsecutiveRegs() { Flags |= One << InConsecutiveRegsOffs; } + + bool isInConsecutiveRegsLast() const { return Flags & InConsecutiveRegsLast; } + void setInConsecutiveRegsLast() { Flags |= One << InConsecutiveRegsLastOffs; } + unsigned getByValAlign() const { return (unsigned) ((One << ((Flags & ByValAlign) >> ByValAlignOffs)) / 2); Index: llvm-suse/include/llvm/Target/TargetCallingConv.td =================================================================== --- llvm-suse.orig/include/llvm/Target/TargetCallingConv.td +++ llvm-suse/include/llvm/Target/TargetCallingConv.td @@ -42,6 +42,11 @@ class CCIf<string predicate, CCAction A> class CCIfByVal<CCAction A> : CCIf<"ArgFlags.isByVal()", A> { } +/// CCIfConsecutiveRegs - If the current argument has InConsecutiveRegs +/// parameter attribute, apply Action A. +class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> { +} + /// CCIfCC - Match if the current calling convention is 'CC'. class CCIfCC<string CC, CCAction A> : CCIf<!strconcat("State.getCallingConv() == ", CC), A> {} Index: llvm-suse/include/llvm/Target/TargetLowering.h =================================================================== --- llvm-suse.orig/include/llvm/Target/TargetLowering.h +++ llvm-suse/include/llvm/Target/TargetLowering.h @@ -668,6 +668,13 @@ public: /// reduce runtime. virtual bool ShouldShrinkFPConstant(EVT) const { return true; } + /// When splitting a value of the specified type into parts, does the Lo + /// or Hi part come first? This usually follows the endianness, except + /// for ppcf128, where the Hi part always comes first. + bool hasBigEndianPartOrdering(EVT VT) const { + return isBigEndian() || VT == MVT::ppcf128; + } + /// If true, the target has custom DAG combine transformations that it can /// perform for the specified node. bool hasTargetDAGCombine(ISD::NodeType NT) const { @@ -2072,6 +2079,15 @@ public: return VT.bitsLT(MinVT) ? MinVT : VT; } + /// For some targets, an LLVM struct type must be broken down into multiple + /// simple types, but the calling convention specifies that the entire struct + /// must be passed in a block of consecutive registers. + virtual bool + functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, + bool isVarArg) const { + return false; + } + /// Returns a 0 terminated array of registers that can be safely used as /// scratch registers. virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const { Index: llvm-suse/lib/CodeGen/AggressiveAntiDepBreaker.cpp =================================================================== --- llvm-suse.orig/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ llvm-suse/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -571,7 +571,9 @@ bool AggressiveAntiDepBreaker::FindSuita unsigned Reg = Regs[i]; if (Reg == SuperReg) continue; bool IsSub = TRI->isSubRegister(SuperReg, Reg); - assert(IsSub && "Expecting group subregister"); + // FIXME: remove this once PR18663 has been properly fixed. For now, + // return a conservative answer: + // assert(IsSub && "Expecting group subregister"); if (!IsSub) return false; } Index: llvm-suse/lib/CodeGen/AsmPrinter/AsmPrinter.cpp =================================================================== --- llvm-suse.orig/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ llvm-suse/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1821,7 +1821,8 @@ static void emitGlobalConstantFP(const C // PPC's long double has odd notions of endianness compared to how LLVM // handles it: p[0] goes first for *big* endian on PPC. - if (AP.TM.getDataLayout()->isBigEndian() != CFP->getType()->isPPC_FP128Ty()) { + if (AP.TM.getDataLayout()->isBigEndian() && + !CFP->getType()->isPPC_FP128Ty()) { int Chunk = API.getNumWords() - 1; if (TrailingBytes) Index: llvm-suse/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm-suse.orig/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm-suse/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5734,6 +5734,9 @@ SDValue DAGCombiner::visitBITCAST(SDNode if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && // Do not change the width of a volatile load. !cast<LoadSDNode>(N0)->isVolatile() && + // Do not remove the cast if the types differ in endian layout. + TLI.hasBigEndianPartOrdering(N0.getValueType()) == + TLI.hasBigEndianPartOrdering(VT) && (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) && TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); Index: llvm-suse/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp =================================================================== --- llvm-suse.orig/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp +++ llvm-suse/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp @@ -58,12 +58,15 @@ void DAGTypeLegalizer::ExpandRes_BITCAST case TargetLowering::TypeExpandFloat: // Convert the expanded pieces of the input. GetExpandedOp(InOp, Lo, Hi); + if (TLI.hasBigEndianPartOrdering(InVT) != + TLI.hasBigEndianPartOrdering(OutVT)) + std::swap(Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; case TargetLowering::TypeSplitVector: GetSplitVector(InOp, Lo, Hi); - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(OutVT)) std::swap(Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); @@ -80,7 +83,7 @@ void DAGTypeLegalizer::ExpandRes_BITCAST EVT LoVT, HiVT; llvm::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); llvm::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT); - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(OutVT)) std::swap(Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); @@ -174,7 +177,7 @@ void DAGTypeLegalizer::ExpandRes_BITCAST false, false, MinAlign(Alignment, IncrementSize)); // Handle endianness of the load. - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(OutVT)) std::swap(Lo, Hi); } @@ -243,7 +246,8 @@ void DAGTypeLegalizer::ExpandRes_NormalL SDLoc dl(N); LoadSDNode *LD = cast<LoadSDNode>(N); - EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0)); + EVT ValueVT = LD->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); unsigned Alignment = LD->getAlignment(); @@ -273,7 +277,7 @@ void DAGTypeLegalizer::ExpandRes_NormalL Hi.getValue(1)); // Handle endianness of the load. - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(ValueVT)) std::swap(Lo, Hi); // Modified the chain - switch anything that used the old chain to use @@ -293,7 +297,7 @@ void DAGTypeLegalizer::ExpandRes_VAARG(S Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2), 0); // Handle endianness of the load. - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(OVT)) std::swap(Lo, Hi); // Modified the chain - switch anything that used the old chain to use @@ -456,8 +460,8 @@ SDValue DAGTypeLegalizer::ExpandOp_Norma SDLoc dl(N); StoreSDNode *St = cast<StoreSDNode>(N); - EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), - St->getValue().getValueType()); + EVT ValueVT = St->getValue().getValueType(); + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); SDValue Chain = St->getChain(); SDValue Ptr = St->getBasePtr(); unsigned Alignment = St->getAlignment(); @@ -471,7 +475,7 @@ SDValue DAGTypeLegalizer::ExpandOp_Norma SDValue Lo, Hi; GetExpandedOp(St->getValue(), Lo, Hi); - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(ValueVT)) std::swap(Lo, Hi); Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getPointerInfo(), Index: llvm-suse/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- llvm-suse.orig/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ llvm-suse/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -168,7 +168,7 @@ static SDValue getCopyFromParts(Selectio SDValue Lo, Hi; Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); - if (TLI.isBigEndian()) + if (TLI.hasBigEndianPartOrdering(ValueVT)) std::swap(Lo, Hi); Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); } else { @@ -7019,8 +7019,13 @@ TargetLowering::LowerCallTo(TargetLoweri for (unsigned i = 0, e = Args.size(); i != e; ++i) { SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(*this, Args[i].Ty, ValueVTs); - for (unsigned Value = 0, NumValues = ValueVTs.size(); - Value != NumValues; ++Value) { + Type *FinalType = Args[i].Ty; + if (Args[i].isByVal) + FinalType = cast<PointerType>(Args[i].Ty)->getElementType(); + bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters( + FinalType, CLI.CallConv, CLI.IsVarArg); + for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; + ++Value) { EVT VT = ValueVTs[Value]; Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); SDValue Op = SDValue(Args[i].Node.getNode(), @@ -7053,6 +7058,11 @@ TargetLowering::LowerCallTo(TargetLoweri } if (Args[i].isNest) Flags.setNest(); + if (NeedsRegBlock) { + Flags.setInConsecutiveRegs(); + if (Value == NumValues - 1) + Flags.setInConsecutiveRegsLast(); + } Flags.setOrigAlign(OriginalAlignment); MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); @@ -7241,6 +7251,11 @@ void SelectionDAGISel::LowerArguments(co ComputeValueVTs(*TLI, I->getType(), ValueVTs); bool isArgValueUsed = !I->use_empty(); unsigned PartBase = 0; + Type *FinalType = I->getType(); + if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) + FinalType = cast<PointerType>(FinalType)->getElementType(); + bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( + FinalType, F.getCallingConv(), F.isVarArg()); for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; ++Value) { EVT VT = ValueVTs[Value]; @@ -7273,6 +7288,11 @@ void SelectionDAGISel::LowerArguments(co } if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) Flags.setNest(); + if (NeedsRegBlock) { + Flags.setInConsecutiveRegs(); + if (Value == NumValues - 1) + Flags.setInConsecutiveRegsLast(); + } Flags.setOrigAlign(OriginalAlignment); MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT); Index: llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp =================================================================== --- llvm-suse.orig/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp +++ llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp @@ -392,7 +392,8 @@ void RuntimeDyldImpl::addRelocationForSy } } -uint8_t *RuntimeDyldImpl::createStubFunction(uint8_t *Addr) { +uint8_t *RuntimeDyldImpl::createStubFunction(uint8_t *Addr, + unsigned AbiVariant) { if (Arch == Triple::aarch64) { // This stub has to be able to access the full address space, // since symbol lookup won't necessarily find a handy, in-range, @@ -435,22 +436,31 @@ uint8_t *RuntimeDyldImpl::createStubFunc *StubAddr = NopInstr; return Addr; } else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le) { - // PowerPC64 stub: the address points to a function descriptor - // instead of the function itself. Load the function address - // on r11 and sets it to control register. Also loads the function - // TOC in r2 and environment pointer to r11. + // Depending on which version of the ELF ABI is in use, we need to + // generate one of two variants of the stub. They both start with + // the same sequence to load the target address into r12. writeInt32BE(Addr, 0x3D800000); // lis r12, highest(addr) writeInt32BE(Addr+4, 0x618C0000); // ori r12, higher(addr) writeInt32BE(Addr+8, 0x798C07C6); // sldi r12, r12, 32 writeInt32BE(Addr+12, 0x658C0000); // oris r12, r12, h(addr) writeInt32BE(Addr+16, 0x618C0000); // ori r12, r12, l(addr) - writeInt32BE(Addr+20, 0xF8410028); // std r2, 40(r1) - writeInt32BE(Addr+24, 0xE96C0000); // ld r11, 0(r12) - writeInt32BE(Addr+28, 0xE84C0008); // ld r2, 0(r12) - writeInt32BE(Addr+32, 0x7D6903A6); // mtctr r11 - writeInt32BE(Addr+36, 0xE96C0010); // ld r11, 16(r2) - writeInt32BE(Addr+40, 0x4E800420); // bctr - + if (AbiVariant == 2) { + // PowerPC64 stub ELFv2 ABI: The address points to the function itself. + // The address is already in r12 as required by the ABI. Branch to it. + writeInt32BE(Addr+20, 0xF8410018); // std r2, 24(r1) + writeInt32BE(Addr+24, 0x7D8903A6); // mtctr r12 + writeInt32BE(Addr+28, 0x4E800420); // bctr + } else { + // PowerPC64 stub ELFv1 ABI: The address points to a function descriptor. + // Load the function address on r11 and sets it to control register. Also + // loads the function TOC in r2 and environment pointer to r11. + writeInt32BE(Addr+20, 0xF8410028); // std r2, 40(r1) + writeInt32BE(Addr+24, 0xE96C0000); // ld r11, 0(r12) + writeInt32BE(Addr+28, 0xE84C0008); // ld r2, 0(r12) + writeInt32BE(Addr+32, 0x7D6903A6); // mtctr r11 + writeInt32BE(Addr+36, 0xE96C0010); // ld r11, 16(r2) + writeInt32BE(Addr+40, 0x4E800420); // bctr + } return Addr; } else if (Arch == Triple::systemz) { writeInt16BE(Addr, 0xC418); // lgrl %r1,.+8 Index: llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp =================================================================== --- llvm-suse.orig/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp +++ llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp @@ -548,32 +548,40 @@ void RuntimeDyldELF::resolveMIPSRelocati } } -// Return the .TOC. section address to R_PPC64_TOC relocations. -uint64_t RuntimeDyldELF::findPPC64TOC() const { +// Return the .TOC. section and offset. +void RuntimeDyldELF::findPPC64TOCSection(ObjectImage &Obj, + ObjSectionToIDMap &LocalSections, + RelocationValueRef &Rel) { + // Set a default SectionID in case we do not find a TOC section below. + // This may happen for references to TOC base base (sym@toc, .odp + // relocation) without a .toc directive. In this case just use the + // first section (which is usually the .odp) since the code won't + // reference the .toc base directly. + Rel.SymbolName = NULL; + Rel.SectionID = 0; + // The TOC consists of sections .got, .toc, .tocbss, .plt in that // order. The TOC starts where the first of these sections starts. - SectionList::const_iterator it = Sections.begin(); - SectionList::const_iterator ite = Sections.end(); - for (; it != ite; ++it) { - if (it->Name == ".got" || - it->Name == ".toc" || - it->Name == ".tocbss" || - it->Name == ".plt") + error_code err; + for (section_iterator si = Obj.begin_sections(), + se = Obj.end_sections(); si != se; si.increment(err)) { + check(err); + + StringRef SectionName; + check(si->getName(SectionName)); + + if (SectionName == ".got" + || SectionName == ".toc" + || SectionName == ".tocbss" + || SectionName == ".plt") { + Rel.SectionID = findOrEmitSection(Obj, *si, false, LocalSections); break; + } } - if (it == ite) { - // This may happen for - // * references to TOC base base (sym@toc, .odp relocation) without - // a .toc directive. - // In this case just use the first section (which is usually - // the .odp) since the code won't reference the .toc base - // directly. - it = Sections.begin(); - } - assert (it != ite); + // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 // thus permitting a full 64 Kbytes segment. - return it->LoadAddress + 0x8000; + Rel.Addend = 0x8000; } // Returns the sections and offset associated with the ODP entry referenced @@ -642,69 +650,103 @@ void RuntimeDyldELF::findOPDEntrySection llvm_unreachable("Attempting to get address of ODP entry!"); } -// Relocation masks following the #lo(value), #hi(value), #higher(value), -// and #highest(value) macros defined in section 4.5.1. Relocation Types -// in PPC-elf64abi document. -// -static inline -uint16_t applyPPClo (uint64_t value) -{ - return value & 0xffff; -} +// Relocation masks following the #lo(value), #hi(value), #ha(value), +// #higher(value), #highera(value), #highest(value), and #highesta(value) +// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi +// document. -static inline -uint16_t applyPPChi (uint64_t value) -{ +static inline uint16_t applyPPClo(uint64_t value) { return value & 0xffff; } + +static inline uint16_t applyPPChi(uint64_t value) { return (value >> 16) & 0xffff; } -static inline -uint16_t applyPPChigher (uint64_t value) -{ +static inline uint16_t applyPPCha (uint64_t value) { + return ((value + 0x8000) >> 16) & 0xffff; +} + +static inline uint16_t applyPPChigher(uint64_t value) { return (value >> 32) & 0xffff; } -static inline -uint16_t applyPPChighest (uint64_t value) -{ +static inline uint16_t applyPPChighera (uint64_t value) { + return ((value + 0x8000) >> 32) & 0xffff; +} + +static inline uint16_t applyPPChighest(uint64_t value) { return (value >> 48) & 0xffff; } +static inline uint16_t applyPPChighesta (uint64_t value) { + return ((value + 0x8000) >> 48) & 0xffff; +} + void RuntimeDyldELF::resolvePPC64Relocation(const SectionEntry &Section, - uint64_t Offset, - uint64_t Value, - uint32_t Type, - int64_t Addend) { - uint8_t* LocalAddress = Section.Address + Offset; + uint64_t Offset, uint64_t Value, + uint32_t Type, int64_t Addend) { + uint8_t *LocalAddress = Section.Address + Offset; switch (Type) { default: llvm_unreachable("Relocation type not implemented yet!"); - break; - case ELF::R_PPC64_ADDR16_LO : - writeInt16BE(LocalAddress, applyPPClo (Value + Addend)); break; - case ELF::R_PPC64_ADDR16_HI : - writeInt16BE(LocalAddress, applyPPChi (Value + Addend)); + case ELF::R_PPC64_ADDR16: + writeInt16BE(LocalAddress, applyPPClo(Value + Addend)); + break; + case ELF::R_PPC64_ADDR16_DS: + writeInt16BE(LocalAddress, applyPPClo(Value + Addend) & ~3); + break; + case ELF::R_PPC64_ADDR16_LO: + writeInt16BE(LocalAddress, applyPPClo(Value + Addend)); + break; + case ELF::R_PPC64_ADDR16_LO_DS: + writeInt16BE(LocalAddress, applyPPClo(Value + Addend) & ~3); + break; + case ELF::R_PPC64_ADDR16_HI: + writeInt16BE(LocalAddress, applyPPChi(Value + Addend)); break; - case ELF::R_PPC64_ADDR16_HIGHER : - writeInt16BE(LocalAddress, applyPPChigher (Value + Addend)); + case ELF::R_PPC64_ADDR16_HA: + writeInt16BE(LocalAddress, applyPPCha(Value + Addend)); break; - case ELF::R_PPC64_ADDR16_HIGHEST : - writeInt16BE(LocalAddress, applyPPChighest (Value + Addend)); + case ELF::R_PPC64_ADDR16_HIGHER: + writeInt16BE(LocalAddress, applyPPChigher(Value + Addend)); break; - case ELF::R_PPC64_ADDR14 : { + case ELF::R_PPC64_ADDR16_HIGHERA: + writeInt16BE(LocalAddress, applyPPChighera(Value + Addend)); + break; + case ELF::R_PPC64_ADDR16_HIGHEST: + writeInt16BE(LocalAddress, applyPPChighest(Value + Addend)); + break; + case ELF::R_PPC64_ADDR16_HIGHESTA: + writeInt16BE(LocalAddress, applyPPChighesta(Value + Addend)); + break; + case ELF::R_PPC64_ADDR14: { assert(((Value + Addend) & 3) == 0); // Preserve the AA/LK bits in the branch instruction - uint8_t aalk = *(LocalAddress+3); + uint8_t aalk = *(LocalAddress + 3); writeInt16BE(LocalAddress + 2, (aalk & 3) | ((Value + Addend) & 0xfffc)); } break; - case ELF::R_PPC64_ADDR32 : { + case ELF::R_PPC64_REL16_LO: { + uint64_t FinalAddress = (Section.LoadAddress + Offset); + uint64_t Delta = Value - FinalAddress + Addend; + writeInt16BE(LocalAddress, applyPPClo(Delta)); + } break; + case ELF::R_PPC64_REL16_HI: { + uint64_t FinalAddress = (Section.LoadAddress + Offset); + uint64_t Delta = Value - FinalAddress + Addend; + writeInt16BE(LocalAddress, applyPPChi(Delta)); + } break; + case ELF::R_PPC64_REL16_HA: { + uint64_t FinalAddress = (Section.LoadAddress + Offset); + uint64_t Delta = Value - FinalAddress + Addend; + writeInt16BE(LocalAddress, applyPPCha(Delta)); + } break; + case ELF::R_PPC64_ADDR32: { int32_t Result = static_cast<int32_t>(Value + Addend); if (SignExtend32<32>(Result) != Result) llvm_unreachable("Relocation R_PPC64_ADDR32 overflow"); writeInt32BE(LocalAddress, Result); } break; - case ELF::R_PPC64_REL24 : { + case ELF::R_PPC64_REL24: { uint64_t FinalAddress = (Section.LoadAddress + Offset); int32_t delta = static_cast<int32_t>(Value - FinalAddress + Addend); if (SignExtend32<24>(delta) != delta) @@ -712,7 +754,7 @@ void RuntimeDyldELF::resolvePPC64Relocat // Generates a 'bl <address>' instruction writeInt32BE(LocalAddress, 0x48000001 | (delta & 0x03FFFFFC)); } break; - case ELF::R_PPC64_REL32 : { + case ELF::R_PPC64_REL32: { uint64_t FinalAddress = (Section.LoadAddress + Offset); int32_t delta = static_cast<int32_t>(Value - FinalAddress + Addend); if (SignExtend32<32>(delta) != delta) @@ -724,22 +766,9 @@ void RuntimeDyldELF::resolvePPC64Relocat uint64_t Delta = Value - FinalAddress + Addend; writeInt64BE(LocalAddress, Delta); } break; - case ELF::R_PPC64_ADDR64 : + case ELF::R_PPC64_ADDR64: writeInt64BE(LocalAddress, Value + Addend); break; - case ELF::R_PPC64_TOC : - writeInt64BE(LocalAddress, findPPC64TOC()); - break; - case ELF::R_PPC64_TOC16 : { - uint64_t TOCStart = findPPC64TOC(); - Value = applyPPClo((Value + Addend) - TOCStart); - writeInt16BE(LocalAddress, applyPPClo(Value)); - } break; - case ELF::R_PPC64_TOC16_DS : { - uint64_t TOCStart = findPPC64TOC(); - Value = ((Value + Addend) - TOCStart); - writeInt16BE(LocalAddress, applyPPClo(Value)); - } break; } } @@ -1063,6 +1092,10 @@ void RuntimeDyldELF::processRelocationRe } } else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le) { if (RelType == ELF::R_PPC64_REL24) { + // Determine ABI variant in use for this object. + unsigned AbiVariant; + Obj.getObjectFile()->getPlatformFlags(AbiVariant); + AbiVariant &= ELF::EF_PPC64_ABI; // A PPC branch relocation will need a stub function if the target is // an external symbol (Symbol::ST_Unknown) or if the target address // is not within the signed 24-bits branch address. @@ -1070,9 +1103,18 @@ void RuntimeDyldELF::processRelocationRe uint8_t *Target = Section.Address + Offset; bool RangeOverflow = false; if (SymType != SymbolRef::ST_Unknown) { - // A function call may points to the .opd entry, so the final symbol value - // in calculated based in the relocation values in .opd section. - findOPDEntrySection(Obj, ObjSectionToID, Value); + if (AbiVariant != 2) { + // In the ELFv1 ABI, a function call may point to the .opd entry, + // so the final symbol value is calculated based on the relocation + // values in the .opd section. + findOPDEntrySection(Obj, ObjSectionToID, Value); + } else { + // In the ELFv2 ABI, a function symbol may provide a local entry + // point, which must be used for direct calls. + uint8_t SymOther; + Symbol->getOther(SymOther); + Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + } uint8_t *RelocTarget = Sections[Value.SectionID].Address + Value.Addend; int32_t delta = static_cast<int32_t>(Target - RelocTarget); // If it is within 24-bits branch range, just set the branch target @@ -1099,53 +1141,100 @@ void RuntimeDyldELF::processRelocationRe // Create a new stub function. DEBUG(dbgs() << " Create a new stub function\n"); Stubs[Value] = Section.StubOffset; - uint8_t *StubTargetAddr = createStubFunction(Section.Address + - Section.StubOffset); + uint8_t *StubTargetAddr = + createStubFunction(Section.Address + Section.StubOffset, + AbiVariant); RelocationEntry RE(SectionID, StubTargetAddr - Section.Address, ELF::R_PPC64_ADDR64, Value.Addend); // Generates the 64-bits address loads as exemplified in section - // 4.5.1 in PPC64 ELF ABI. - RelocationEntry REhst(SectionID, - StubTargetAddr - Section.Address + 2, + // 4.5.1 in PPC64 ELF ABI. Note that the relocations need to + // apply to the low part of the instructions, so we have to update + // the offset according to the target endianness. + uint64_t StubRelocOffset = StubTargetAddr - Section.Address; + if (!IsTargetLittleEndian) + StubRelocOffset += 2; + + RelocationEntry REhst(SectionID, StubRelocOffset + 0, ELF::R_PPC64_ADDR16_HIGHEST, Value.Addend); - RelocationEntry REhr(SectionID, - StubTargetAddr - Section.Address + 6, + RelocationEntry REhr(SectionID, StubRelocOffset + 4, ELF::R_PPC64_ADDR16_HIGHER, Value.Addend); - RelocationEntry REh(SectionID, - StubTargetAddr - Section.Address + 14, + RelocationEntry REh(SectionID, StubRelocOffset + 12, ELF::R_PPC64_ADDR16_HI, Value.Addend); - RelocationEntry REl(SectionID, - StubTargetAddr - Section.Address + 18, + RelocationEntry REl(SectionID, StubRelocOffset + 16, ELF::R_PPC64_ADDR16_LO, Value.Addend); if (Value.SymbolName) { addRelocationForSymbol(REhst, Value.SymbolName); - addRelocationForSymbol(REhr, Value.SymbolName); - addRelocationForSymbol(REh, Value.SymbolName); - addRelocationForSymbol(REl, Value.SymbolName); + addRelocationForSymbol(REhr, Value.SymbolName); + addRelocationForSymbol(REh, Value.SymbolName); + addRelocationForSymbol(REl, Value.SymbolName); } else { addRelocationForSection(REhst, Value.SectionID); - addRelocationForSection(REhr, Value.SectionID); - addRelocationForSection(REh, Value.SectionID); - addRelocationForSection(REl, Value.SectionID); + addRelocationForSection(REhr, Value.SectionID); + addRelocationForSection(REh, Value.SectionID); + addRelocationForSection(REl, Value.SectionID); } resolveRelocation(Section, Offset, (uint64_t)Section.Address + Section.StubOffset, RelType, 0); - if (SymType == SymbolRef::ST_Unknown) - // Restore the TOC for external calls - writeInt32BE(Target+4, 0xE8410028); // ld r2,40(r1) Section.StubOffset += getMaxStubSize(); } + if (SymType == SymbolRef::ST_Unknown) { + // Restore the TOC for external calls + if (AbiVariant == 2) + writeInt32BE(Target + 4, 0xE8410018); // ld r2,28(r1) + else + writeInt32BE(Target + 4, 0xE8410028); // ld r2,40(r1) + } + } + } else if (RelType == ELF::R_PPC64_TOC16 || + RelType == ELF::R_PPC64_TOC16_DS || + RelType == ELF::R_PPC64_TOC16_LO || + RelType == ELF::R_PPC64_TOC16_LO_DS || + RelType == ELF::R_PPC64_TOC16_HI || + RelType == ELF::R_PPC64_TOC16_HA) { + // These relocations are supposed to subtract the TOC address from + // the final value. This does not fit cleanly into the RuntimeDyld + // scheme, since there may be *two* sections involved in determining + // the relocation value (the section of the symbol refered to by the + // relocation, and the TOC section associated with the current module). + // + // Fortunately, these relocations are currently only ever generated + // refering to symbols that themselves reside in the TOC, which means + // that the two sections are actually the same. Thus they cancel out + // and we can immediately resolve the relocation right now. + switch (RelType) { + case ELF::R_PPC64_TOC16: RelType = ELF::R_PPC64_ADDR16; break; + case ELF::R_PPC64_TOC16_DS: RelType = ELF::R_PPC64_ADDR16_DS; break; + case ELF::R_PPC64_TOC16_LO: RelType = ELF::R_PPC64_ADDR16_LO; break; + case ELF::R_PPC64_TOC16_LO_DS: RelType = ELF::R_PPC64_ADDR16_LO_DS; break; + case ELF::R_PPC64_TOC16_HI: RelType = ELF::R_PPC64_ADDR16_HI; break; + case ELF::R_PPC64_TOC16_HA: RelType = ELF::R_PPC64_ADDR16_HA; break; + default: llvm_unreachable("Wrong relocation type."); } + + RelocationValueRef TOCValue; + findPPC64TOCSection(Obj, ObjSectionToID, TOCValue); + if (Value.SymbolName || Value.SectionID != TOCValue.SectionID) + llvm_unreachable("Unsupported TOC relocation."); + Value.Addend -= TOCValue.Addend; + resolveRelocation(Sections[SectionID], Offset, Value.Addend, RelType, 0); } else { + // There are two ways to refer to the TOC address directly: either + // via a ELF::R_PPC64_TOC relocation (where both symbol and addend are + // ignored), or via any relocation that refers to the magic ".TOC." + // symbols (in which case the addend is respected). + if (RelType == ELF::R_PPC64_TOC) { + RelType = ELF::R_PPC64_ADDR64; + findPPC64TOCSection(Obj, ObjSectionToID, Value); + } else if (TargetName == ".TOC.") { + findPPC64TOCSection(Obj, ObjSectionToID, Value); + Value.Addend += Addend; + } + RelocationEntry RE(SectionID, Offset, RelType, Value.Addend); - // Extra check to avoid relocation againt empty symbols (usually - // the R_PPC64_TOC). - if (SymType != SymbolRef::ST_Unknown && TargetName.empty()) - Value.SymbolName = NULL; if (Value.SymbolName) addRelocationForSymbol(RE, Value.SymbolName); Index: llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h =================================================================== --- llvm-suse.orig/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h +++ llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h @@ -106,7 +106,9 @@ class RuntimeDyldELF : public RuntimeDyl return 1; } - uint64_t findPPC64TOC() const; + void findPPC64TOCSection(ObjectImage &Obj, + ObjSectionToIDMap &LocalSections, + RelocationValueRef &Rel); void findOPDEntrySection(ObjectImage &Obj, ObjSectionToIDMap &LocalSections, RelocationValueRef &Rel); Index: llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h =================================================================== --- llvm-suse.orig/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h +++ llvm-suse/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h @@ -284,7 +284,7 @@ protected: /// \brief Emits long jump instruction to Addr. /// \return Pointer to the memory area for emitting target address. - uint8_t* createStubFunction(uint8_t *Addr); + uint8_t* createStubFunction(uint8_t *Addr, unsigned AbiVariant = 0); /// \brief Resolves relocations from Relocs list with address from Value. void resolveRelocationList(const RelocationList &Relocs, uint64_t Value); Index: llvm-suse/lib/MC/MCELF.cpp =================================================================== --- llvm-suse.orig/lib/MC/MCELF.cpp +++ llvm-suse/lib/MC/MCELF.cpp @@ -61,7 +61,7 @@ void MCELF::SetVisibility(MCSymbolData & SD.setFlags(OtherFlags | (Visibility << ELF_STV_Shift)); } -unsigned MCELF::GetVisibility(MCSymbolData &SD) { +unsigned MCELF::GetVisibility(const MCSymbolData &SD) { unsigned Visibility = (SD.getFlags() & (0x3 << ELF_STV_Shift)) >> ELF_STV_Shift; assert(Visibility == ELF::STV_DEFAULT || Visibility == ELF::STV_INTERNAL || @@ -76,7 +76,7 @@ void MCELF::setOther(MCSymbolData &SD, u SD.setFlags(OtherFlags | (Other << ELF_Other_Shift)); } -unsigned MCELF::getOther(MCSymbolData &SD) { +unsigned MCELF::getOther(const MCSymbolData &SD) { unsigned Other = (SD.getFlags() & (0x3f << ELF_Other_Shift)) >> ELF_Other_Shift; return Other; Index: llvm-suse/lib/Support/Host.cpp =================================================================== --- llvm-suse.orig/lib/Support/Host.cpp +++ llvm-suse/lib/Support/Host.cpp @@ -564,6 +564,8 @@ std::string sys::getHostCPUName() { .Case("A2", "a2") .Case("POWER6", "pwr6") .Case("POWER7", "pwr7") + .Case("POWER8", "pwr8") + .Case("POWER8E", "pwr8") .Default(generic); } #elif defined(__linux__) && defined(__arm__) Index: llvm-suse/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ llvm-suse/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -9,8 +9,10 @@ #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCMCExpr.h" +#include "PPCTargetStreamer.h" #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" @@ -201,6 +203,8 @@ class PPCAsmParser : public MCTargetAsmP bool ParseDirectiveWord(unsigned Size, SMLoc L); bool ParseDirectiveTC(unsigned Size, SMLoc L); bool ParseDirectiveMachine(SMLoc L); + bool ParseDirectiveAbiVersion(SMLoc L); + bool ParseDirectiveLocalEntry(SMLoc L); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, @@ -1269,6 +1273,10 @@ bool PPCAsmParser::ParseDirective(AsmTok return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); if (IDVal == ".machine") return ParseDirectiveMachine(DirectiveID.getLoc()); + if (IDVal == ".abiversion") + return ParseDirectiveAbiVersion(DirectiveID.getLoc()); + if (IDVal == ".localentry") + return ParseDirectiveLocalEntry(DirectiveID.getLoc()); return true; } @@ -1338,6 +1346,64 @@ bool PPCAsmParser::ParseDirectiveMachine return false; } +/// ParseDirectiveAbiVersion +/// ::= .abiversion constant-expression +bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { + int64_t AbiVersion; + if (getParser().parseAbsoluteExpression(AbiVersion)){ + Error(L, "expected constant expression"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + Error(L, "unexpected token in directive"); + return false; + } + + PPCTargetStreamer &TStreamer = + static_cast<PPCTargetStreamer &>( + getParser().getStreamer().getTargetStreamer()); + TStreamer.emitAbiVersion(AbiVersion); + + return false; +} + +/// ParseDirectiveLocalEntry +/// ::= .localentry symbol, expression +bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { + StringRef Name; + if (getParser().parseIdentifier(Name)) { + Error(L, "expected identifier in directive"); + return false; + } + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + if (getLexer().isNot(AsmToken::Comma)) { + Error(L, "unexpected token in directive"); + return false; + } + Lex(); + + const MCExpr *Expr; + if (getParser().parseExpression(Expr)) { + Error(L, "expected expression"); + return false; + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) { + Error(L, "unexpected token in directive"); + return false; + } + + PPCTargetStreamer &TStreamer = + static_cast<PPCTargetStreamer &>( + getParser().getStreamer().getTargetStreamer()); + TStreamer.emitLocalEntry(Sym, Expr); + + return false; +} + + + /// Force static initialization. extern "C" void LLVMInitializePowerPCAsmParser() { RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -9,7 +9,9 @@ #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCFixupKinds.h" +#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCELF.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCMachObjectWriter.h" @@ -71,14 +73,16 @@ static unsigned getFixupKindNumBytes(uns namespace { class PPCAsmBackend : public MCAsmBackend { -const Target &TheTarget; + const Target &TheTarget; + bool IsLittleEndian; public: - PPCAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {} + PPCAsmBackend(const Target &T, bool isLittle) : MCAsmBackend(), TheTarget(T), + IsLittleEndian(isLittle) {} unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { - const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = { + const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = { // name offset bits flags { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, @@ -88,13 +92,23 @@ public: { "fixup_ppc_half16ds", 0, 14, 0 }, { "fixup_ppc_nofixup", 0, 0, 0 } }; + const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = { + // name offset bits flags + { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_ppc_br24abs", 2, 24, 0 }, + { "fixup_ppc_brcond14abs", 2, 14, 0 }, + { "fixup_ppc_half16", 0, 16, 0 }, + { "fixup_ppc_half16ds", 2, 14, 0 }, + { "fixup_ppc_nofixup", 0, 0, 0 } + }; if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); - return Infos[Kind - FirstTargetFixupKind]; + return (IsLittleEndian? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; } void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, @@ -108,8 +122,34 @@ public: // For each byte of the fragment that the fixup touches, mask in the bits // from the fixup value. The Value has been "split up" into the appropriate // bitfields above. - for (unsigned i = 0; i != NumBytes; ++i) - Data[Offset + i] |= uint8_t((Value >> ((NumBytes - i - 1)*8)) & 0xff); + for (unsigned i = 0; i != NumBytes; ++i) { + unsigned Idx = IsLittleEndian ? i : (NumBytes - 1 - i); + Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); + } + } + + void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, + const MCFixup &Fixup, const MCFragment *DF, + MCValue &Target, uint64_t &Value, + bool &IsResolved) { + switch ((PPC::Fixups)Fixup.getKind()) { + default: break; + case PPC::fixup_ppc_br24: + case PPC::fixup_ppc_br24abs: + // If the target symbol has a local entry point we must not attempt + // to resolve the fixup directly. Emit a relocation and leave + // resolution of the final target address to the linker. + if (const MCSymbolRefExpr *A = Target.getSymA()) { + const MCSymbolData &Data = Asm.getSymbolData(A->getSymbol()); + // The "other" values are stored in the last 6 bits of the second byte. + // The traditional defines for STO values assume the full byte and thus + // the shift to pack it. + unsigned Other = MCELF::getOther(Data) << 2; + if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0) + IsResolved = false; + } + break; + } } bool mayNeedRelaxation(const MCInst &Inst) const { @@ -152,6 +192,10 @@ public: assert(Name == "ppc32" && "Unknown target name!"); return 4; } + + bool isLittleEndian() const { + return IsLittleEndian; + } }; } // end anonymous namespace @@ -160,7 +204,7 @@ public: namespace { class DarwinPPCAsmBackend : public PPCAsmBackend { public: - DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { } + DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, false) { } MCObjectWriter *createObjectWriter(raw_ostream &OS) const { bool is64 = getPointerSize() == 8; @@ -179,13 +223,13 @@ namespace { class ELFPPCAsmBackend : public PPCAsmBackend { uint8_t OSABI; public: - ELFPPCAsmBackend(const Target &T, uint8_t OSABI) : - PPCAsmBackend(T), OSABI(OSABI) { } + ELFPPCAsmBackend(const Target &T, bool IsLittleEndian, uint8_t OSABI) : + PPCAsmBackend(T, IsLittleEndian), OSABI(OSABI) { } MCObjectWriter *createObjectWriter(raw_ostream &OS) const { bool is64 = getPointerSize() == 8; - return createPPCELFObjectWriter(OS, is64, OSABI); + return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI); } virtual bool doesSectionRequireSymbols(const MCSection &Section) const { @@ -202,5 +246,6 @@ MCAsmBackend *llvm::createPPCAsmBackend( return new DarwinPPCAsmBackend(T); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); - return new ELFPPCAsmBackend(T, OSABI); + bool IsLittleEndian = Triple(TT).getArch() == Triple::ppc64le; + return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI); } Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -10,6 +10,8 @@ #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCFixupKinds.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCELF.h" #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCValue.h" @@ -371,7 +373,7 @@ const MCSymbol *PPCELFObjectWriter::Expl MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); - bool EmitThisSym; + bool EmitThisSym = false; switch (Modifier) { // GOT references always need a relocation, even if the // target symbol is local. @@ -382,7 +384,25 @@ const MCSymbol *PPCELFObjectWriter::Expl EmitThisSym = true; break; default: - EmitThisSym = false; + switch ((PPC::Fixups)Fixup.getKind()) { + case PPC::fixup_ppc_br24: + case PPC::fixup_ppc_br24abs: + // If the target symbol has a local entry point we must not attempt + // to resolve the fixup directly. Emit a relocation and leave + // resolution of the final target address to the linker. + if (const MCSymbolRefExpr *A = Target.getSymA()) { + const MCSymbolData &Data = Asm.getSymbolData(A->getSymbol()); + // The "other" values are stored in the last 6 bits of the second byte. + // The traditional defines for STO values assume the full byte and thus + // the shift to pack it. + unsigned Other = MCELF::getOther(Data) << 2; + if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0) + EmitThisSym = true; + } + break; + default: + break; + } break; } @@ -413,7 +433,8 @@ const MCSymbol *PPCELFObjectWriter::unde MCObjectWriter *llvm::createPPCELFObjectWriter(raw_ostream &OS, bool Is64Bit, + bool IsLittleEndian, uint8_t OSABI) { MCELFObjectTargetWriter *MOTW = new PPCELFObjectWriter(Is64Bit, OSABI); - return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false); + return createELFObjectWriter(MOTW, OS, IsLittleEndian); } Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -36,11 +36,11 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(b void PPCLinuxMCAsmInfo::anchor() { } -PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) { +PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, const Triple& T) { if (is64Bit) { PointerSize = CalleeSaveStackSlotSize = 8; } - IsLittleEndian = false; + IsLittleEndian = T.getArch() == Triple::ppc64le; // ".comm align is in bytes but .align is pow-2." AlignmentIsInBytes = false; Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -29,7 +29,7 @@ class Triple; class PPCLinuxMCAsmInfo : public MCAsmInfoELF { virtual void anchor(); public: - explicit PPCLinuxMCAsmInfo(bool is64Bit); + explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&); }; } // namespace llvm Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -33,14 +33,13 @@ class PPCMCCodeEmitter : public MCCodeEm PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION; void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION; - const MCSubtargetInfo &STI; + const MCInstrInfo &MCII; const MCContext &CTX; - Triple TT; + bool IsLittleEndian; public: - PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, - MCContext &ctx) - : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) { + PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool isLittle) + : MCII(mcii), CTX(ctx), IsLittleEndian(isLittle) { } ~PPCMCCodeEmitter() {} @@ -92,11 +91,46 @@ public: Opcode == PPC::BL8_NOP_TLS) Size = 8; - // Output the constant in big endian byte order. - int ShiftValue = (Size * 8) - 8; - for (unsigned i = 0; i != Size; ++i) { - OS << (char)(Bits >> ShiftValue); - Bits <<= 8; + // Output the constant in big/little endian byte order. + switch (Size) { + case 4: + if (IsLittleEndian) { + OS << (char)(Bits); + OS << (char)(Bits >> 8); + OS << (char)(Bits >> 16); + OS << (char)(Bits >> 24); + } else { + OS << (char)(Bits >> 24); + OS << (char)(Bits >> 16); + OS << (char)(Bits >> 8); + OS << (char)(Bits); + } + break; + case 8: + // If we emit a pair of instructions, the first one is + // always in the top 32 bits, even on little-endian. + if (IsLittleEndian) { + OS << (char)(Bits >> 32); + OS << (char)(Bits >> 40); + OS << (char)(Bits >> 48); + OS << (char)(Bits >> 56); + OS << (char)(Bits); + OS << (char)(Bits >> 8); + OS << (char)(Bits >> 16); + OS << (char)(Bits >> 24); + } else { + OS << (char)(Bits >> 56); + OS << (char)(Bits >> 48); + OS << (char)(Bits >> 40); + OS << (char)(Bits >> 32); + OS << (char)(Bits >> 24); + OS << (char)(Bits >> 16); + OS << (char)(Bits >> 8); + OS << (char)(Bits); + } + break; + default: + llvm_unreachable ("Invalid instruction size"); } ++MCNumEmitted; // Keep track of the # of mi's emitted. @@ -110,7 +144,9 @@ MCCodeEmitter *llvm::createPPCMCCodeEmit const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) { - return new PPCMCCodeEmitter(MCII, STI, Ctx); + Triple TT(STI.getTargetTriple()); + bool IsLittleEndian = TT.getArch() == Triple::ppc64le; + return new PPCMCCodeEmitter(MCII, Ctx, IsLittleEndian); } unsigned PPCMCCodeEmitter:: @@ -166,7 +202,7 @@ unsigned PPCMCCodeEmitter::getImm16Encod if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); // Add a fixup for the immediate field. - Fixups.push_back(MCFixup::Create(2, MO.getExpr(), + Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_half16)); return 0; } @@ -183,7 +219,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncod return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; // Add a fixup for the displacement field. - Fixups.push_back(MCFixup::Create(2, MO.getExpr(), + Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_half16)); return RegBits; } @@ -201,7 +237,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEnco return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits; // Add a fixup for the displacement field. - Fixups.push_back(MCFixup::Create(2, MO.getExpr(), + Fixups.push_back(MCFixup::Create(IsLittleEndian? 0 : 2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_half16ds)); return RegBits; } Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -16,12 +16,16 @@ #include "PPCMCAsmInfo.h" #include "PPCTargetStreamer.h" #include "llvm/MC/MCCodeGenInfo.h" +#include "llvm/MC/MCELF.h" +#include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MachineLocation.h" +#include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -74,7 +78,7 @@ static MCAsmInfo *createPPCMCAsmInfo(con if (TheTriple.isOSDarwin()) MAI = new PPCMCAsmInfoDarwin(isPPC64); else - MAI = new PPCLinuxMCAsmInfo(isPPC64); + MAI = new PPCLinuxMCAsmInfo(isPPC64, TheTriple); // Initial state of the frame pointer is R1. unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; @@ -120,13 +124,55 @@ public: OS << S.getName(); OS << '\n'; } + virtual void emitAbiVersion(int AbiVersion) { + OS << "\t.abiversion " << AbiVersion << '\n'; + } + virtual void emitLocalEntry(MCSymbol *S, const MCExpr *LocalOffset) { + OS << "\t.localentry\t" << *S << ", " << *LocalOffset << '\n'; + } }; class PPCTargetELFStreamer : public PPCTargetStreamer { + MCELFStreamer &getStreamer() { + return *static_cast<MCELFStreamer *>(Streamer); + } virtual void emitTCEntry(const MCSymbol &S) { // Creates a R_PPC64_TOC relocation Streamer->EmitSymbolValue(&S, 8); } + virtual void emitAbiVersion(int AbiVersion) { + MCAssembler &MCA = getStreamer().getAssembler(); + unsigned Flags = MCA.getELFHeaderEFlags(); + Flags &= ~ELF::EF_PPC64_ABI; + Flags |= (AbiVersion & ELF::EF_PPC64_ABI); + MCA.setELFHeaderEFlags(Flags); + } + virtual void emitLocalEntry(MCSymbol *S, const MCExpr *LocalOffset) { + MCAssembler &MCA = getStreamer().getAssembler(); + MCSymbolData &Data = getStreamer().getOrCreateSymbolData(S); + + int64_t Res; + if (!LocalOffset->EvaluateAsAbsolute(Res, MCA)) + report_fatal_error(".localentry expression must be absolute."); + + unsigned Encoded = ELF::encodePPC64LocalEntryOffset(Res); + if (Res != ELF::decodePPC64LocalEntryOffset(Encoded)) + report_fatal_error(".localentry expression cannot be encoded."); + + // The "other" values are stored in the last 6 bits of the second byte. + // The traditional defines for STO values assume the full byte and thus + // the shift to pack it. + unsigned Other = MCELF::getOther(Data) << 2; + Other &= ~ELF::STO_PPC64_LOCAL_MASK; + Other |= Encoded; + MCELF::setOther(Data, Other >> 2); + + // For GAS compatibility, unless we already saw a .abiversion directive, + // set e_flags to indicate ELFv2 ABI. + unsigned Flags = MCA.getELFHeaderEFlags(); + if ((Flags & ELF::EF_PPC64_ABI) == 0) + MCA.setELFHeaderEFlags(Flags | 2); + } }; } Index: llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ llvm-suse/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -46,6 +46,7 @@ MCAsmBackend *createPPCAsmBackend(const /// createPPCELFObjectWriter - Construct an PPC ELF object writer. MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS, bool Is64Bit, + bool IsLittleEndian, uint8_t OSABI); /// createPPCELFObjectWriter - Construct a PPC Mach-O object writer. MCObjectWriter *createPPCMachObjectWriter(raw_ostream &OS, bool Is64Bit, Index: llvm-suse/lib/Target/PowerPC/PPC.td =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPC.td +++ llvm-suse/lib/Target/PowerPC/PPC.td @@ -46,6 +46,7 @@ def DirectivePwr5x: SubtargetFeature<"", def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; +def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; @@ -259,6 +260,15 @@ def : ProcessorModel<"pwr7", G5Model, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, + FeatureFPRND, FeatureFPCVT, FeatureISEL, + FeaturePOPCNTD, FeatureLDBRX, + Feature64Bit /*, Feature64BitRegs */, + DeprecatedMFTB, DeprecatedDST]>; +def : ProcessorModel<"pwr8", G5Model, + [DirectivePwr8, FeatureAltivec, + FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, + FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, + FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, Index: llvm-suse/lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ llvm-suse/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -33,6 +33,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/DebugInfo.h" #include "llvm/IR/Constants.h" @@ -100,9 +101,11 @@ namespace { } bool doFinalization(Module &M); + void EmitStartOfAsmFile(Module &M); virtual void EmitFunctionEntryLabel(); + void EmitFunctionBodyStart(); void EmitFunctionBodyEnd(); }; @@ -726,9 +729,20 @@ void PPCAsmPrinter::EmitInstruction(cons OutStreamer.EmitInstruction(TmpInst); } +void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) { + if (Subtarget.isELFv2ABI()) { + PPCTargetStreamer &TS = + static_cast<PPCTargetStreamer &>(OutStreamer.getTargetStreamer()); + + TS.emitAbiVersion(2); + } +} + void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { if (!Subtarget.isPPC64()) // linux/ppc32 - Normal entry label. return AsmPrinter::EmitFunctionEntryLabel(); + if (Subtarget.isELFv2ABI()) // ELFv2 ABI - Normal entry label. + return AsmPrinter::EmitFunctionEntryLabel(); // Emit an official procedure descriptor. MCSectionSubPair Current = OutStreamer.getCurrentSection(); @@ -804,6 +818,67 @@ bool PPCLinuxAsmPrinter::doFinalization( return AsmPrinter::doFinalization(M); } +/// EmitFunctionBodyStart - Emit a global entry point prefix for ELFv2. +void PPCLinuxAsmPrinter::EmitFunctionBodyStart() { + // In the ELFv2 ABI, in functions that use the TOC register, we need to + // provide two entry points. The ABI guarantees that when calling the + // local entry point, r2 is set up by the caller to contain the TOC base + // for this function, and when calling the global entry point, r12 is set + // up by the caller to hold the address of the global entry point. We + // thus emit a prefix sequence along the following lines: + // + // func: + // # global entry point + // addis r2,r12,(.TOC.-func)@ha + // addi r2,r2,(.TOC.-func)@l + // .localentry func, .-func + // # local entry point, followed by function body + // + // This ensures we have r2 set up correctly while executing the function + // body, no matter which entry point is called. + if (Subtarget.isELFv2ABI() + // Only do all that if the function uses r2 in the first place. + && !MF->getRegInfo().use_empty(PPC::X2)) { + + MCSymbol *GlobalEntryLabel = OutContext.CreateTempSymbol(); + OutStreamer.EmitLabel(GlobalEntryLabel); + const MCSymbolRefExpr *GlobalEntryLabelExp = + MCSymbolRefExpr::Create(GlobalEntryLabel, OutContext); + + MCSymbol *TOCSymbol = OutContext.GetOrCreateSymbol(StringRef(".TOC.")); + const MCExpr *TOCDeltaExpr = + MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(TOCSymbol, OutContext), + GlobalEntryLabelExp, OutContext); + + const MCExpr *TOCDeltaHi = + PPCMCExpr::CreateHa(TOCDeltaExpr, false, OutContext); + OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS) + .addReg(PPC::X2) + .addReg(PPC::X12) + .addExpr(TOCDeltaHi)); + + const MCExpr *TOCDeltaLo = + PPCMCExpr::CreateLo(TOCDeltaExpr, false, OutContext); + OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI) + .addReg(PPC::X2) + .addReg(PPC::X2) + .addExpr(TOCDeltaLo)); + + MCSymbol *LocalEntryLabel = OutContext.CreateTempSymbol(); + OutStreamer.EmitLabel(LocalEntryLabel); + const MCSymbolRefExpr *LocalEntryLabelExp = + MCSymbolRefExpr::Create(LocalEntryLabel, OutContext); + const MCExpr *LocalOffsetExp = + MCBinaryExpr::CreateSub(LocalEntryLabelExp, + GlobalEntryLabelExp, OutContext); + + PPCTargetStreamer &TS = + static_cast<PPCTargetStreamer &>(OutStreamer.getTargetStreamer()); + + TS.emitLocalEntry(CurrentFnSym, LocalOffsetExp); + } +} + /// EmitFunctionBodyEnd - Print the traceback table before the .size /// directive. /// @@ -1140,4 +1215,5 @@ static AsmPrinter *createPPCAsmPrinterPa extern "C" void LLVMInitializePowerPCAsmPrinter() { TargetRegistry::RegisterAsmPrinter(ThePPC32Target, createPPCAsmPrinterPass); TargetRegistry::RegisterAsmPrinter(ThePPC64Target, createPPCAsmPrinterPass); + TargetRegistry::RegisterAsmPrinter(ThePPC64LETarget, createPPCAsmPrinterPass); } Index: llvm-suse/lib/Target/PowerPC/PPCCallingConv.td =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCCallingConv.td +++ llvm-suse/lib/Target/PowerPC/PPCCallingConv.td @@ -29,11 +29,15 @@ def RetCC_PPC : CallingConv<[ CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, - CCIfType<[f32], CCAssignToReg<[F1, F2]>>, - CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, + // Floating point types returned as "direct" go into F1 .. F8; note that + // only the ELFv2 ABI fully utilizes all these registers. + CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, + CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, - // Vector types are always returned in V2. - CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> + // Vector types returned as "direct" go into V2 .. V9; note that only the + // ELFv2 ABI fully utilizes all these registers. + CCIfType<[v16i8, v8i16, v4i32, v4f32], + CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>> ]>; @@ -63,9 +67,10 @@ def RetCC_PPC64_ELF_FIS : CallingConv<[ CCIfType<[i32], CCPromoteToType<i64>>, CCIfType<[i64], CCAssignToReg<[X3, X4]>>, CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, - CCIfType<[f32], CCAssignToReg<[F1, F2]>>, - CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, - CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> + CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, + CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, + CCIfType<[v16i8, v8i16, v4i32, v4f32], + CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>> ]>; //===----------------------------------------------------------------------===// Index: llvm-suse/lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCFastISel.cpp +++ llvm-suse/lib/Target/PowerPC/PPCFastISel.cpp @@ -1026,6 +1026,10 @@ bool PPCFastISel::SelectFPToI(const Inst if (DstVT != MVT::i32 && DstVT != MVT::i64) return false; + // If we don't have FCTIDUZ and we need it, punt to SelectionDAG. + if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget.hasFPCVT()) + return false; + Value *Src = I->getOperand(0); Type *SrcTy = Src->getType(); if (!isTypeLegal(SrcTy, SrcVT)) @@ -1191,6 +1195,13 @@ bool PPCFastISel::processCallArgs(SmallV bool IsVarArg) { SmallVector<CCValAssign, 16> ArgLocs; CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context); + + // Reserve space for the linkage area on the stack. + bool isELFv2ABI = PPCSubTarget.isELFv2ABI(); + unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false, + isELFv2ABI); + CCInfo.AllocateStack(LinkageSize, 8); + CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS); // Bail out if we can't handle any of the arguments. @@ -1212,6 +1223,14 @@ bool PPCFastISel::processCallArgs(SmallV // Get a count of how many bytes are to be pushed onto the stack. NumBytes = CCInfo.getNextStackOffset(); + // The prolog code of the callee may store up to 8 GPR argument registers to + // the stack, allowing va_start to index over them in memory if its varargs. + // Because we cannot tell if this is needed on the caller side, we have to + // conservatively assume that it is needed. As such, make sure we have at + // least enough stack space for the caller to store the 8 GPRs. + // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area. + NumBytes = std::max(NumBytes, LinkageSize + 64); + // Issue CALLSEQ_START. BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TII.getCallFrameSetupOpcode())) @@ -1476,6 +1495,10 @@ bool PPCFastISel::SelectCall(const Instr for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) MIB.addReg(RegArgs[II], RegState::Implicit); + // Direct calls in the ELFv2 ABI need the TOC register live into the call. + if (PPCSubTarget.isELFv2ABI()) + MIB.addReg(PPC::X2, RegState::Implicit); + // Add a register mask with the call-preserved registers. Proper // defs for return values will be added by setPhysRegsDeadExcept(). MIB.addRegMask(TRI.getCallPreservedMask(CC)); Index: llvm-suse/lib/Target/PowerPC/PPCFrameLowering.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCFrameLowering.cpp +++ llvm-suse/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -236,9 +236,10 @@ unsigned PPCFrameLowering::determineFram // Get the maximum call frame size of all the calls. unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); - // Maximum call frame needs to be at least big enough for linkage and 8 args. - unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), - Subtarget.isDarwinABI()); + // Maximum call frame needs to be at least big enough for linkage area. + unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(), + Subtarget.isDarwinABI(), + Subtarget.isELFv2ABI()); maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); // If we have dynamic alloca then maxCallFrameSize needs to be aligned so @@ -350,6 +351,7 @@ void PPCFrameLowering::emitPrologue(Mach // Get the ABI. bool isDarwinABI = Subtarget.isDarwinABI(); bool isSVR4ABI = Subtarget.isSVR4ABI(); + bool isELFv2ABI = Subtarget.isELFv2ABI(); assert((isDarwinABI || isSVR4ABI) && "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); @@ -463,6 +465,9 @@ void PPCFrameLowering::emitPrologue(Mach "Prologue CR saving supported only in 64-bit mode"); if (!MustSaveCRs.empty()) { // will only occur for PPC64 + // FIXME: In the ELFv2 ABI, we are not required to save all CR fields. + // If only one or two CR fields are clobbered, it could be more + // efficient to use mfocrf to selectively save just those fields. MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) @@ -631,8 +636,12 @@ void PPCFrameLowering::emitPrologue(Mach // For 64-bit SVR4 when we have spilled CRs, the spill location // is SP+8, not a frame-relative slot. if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { + // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for + // the whole CR word. In the ELFv2 ABI, every CR that was + // actually saved gets its own CFI record. + unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; MMI.addFrameInst(MCCFIInstruction::createOffset( - Label, MRI->getDwarfRegNum(PPC::CR2, true), 8)); + Label, MRI->getDwarfRegNum(CRReg, true), 8)); continue; } Index: llvm-suse/lib/Target/PowerPC/PPCFrameLowering.h =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCFrameLowering.h +++ llvm-suse/lib/Target/PowerPC/PPCFrameLowering.h @@ -79,6 +79,12 @@ public: return isPPC64 ? 16 : 4; } + /// getTOCSaveOffset - Return the previous frame offset to save the + /// TOC register -- 64-bit SVR4 ABI only. + static unsigned getTOCSaveOffset(bool isELFv2ABI) { + return isELFv2ABI ? 24 : 40; + } + /// getFramePointerSaveOffset - Return the previous frame offset to save the /// frame pointer. static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { @@ -106,39 +112,15 @@ public: /// getLinkageSize - Return the size of the PowerPC ABI linkage area. /// - static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) { + static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, + bool isELFv2ABI) { if (isDarwinABI || isPPC64) - return 6 * (isPPC64 ? 8 : 4); + return (isELFv2ABI ? 4 : 6) * (isPPC64 ? 8 : 4); // SVR4 ABI: return 8; } - /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI - /// argument area. - static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) { - // For the Darwin ABI / 64-bit SVR4 ABI: - // The prolog code of the callee may store up to 8 GPR argument registers to - // the stack, allowing va_start to index over them in memory if its varargs. - // Because we cannot tell if this is needed on the caller side, we have to - // conservatively assume that it is needed. As such, make sure we have at - // least enough stack space for the caller to store the 8 GPRs. - if (isDarwinABI || isPPC64) - return 8 * (isPPC64 ? 8 : 4); - - // 32-bit SVR4 ABI: - // There is no default stack allocated for the 8 first GPR arguments. - return 0; - } - - /// getMinCallFrameSize - Return the minimum size a call frame can be using - /// the PowerPC ABI. - static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) { - // The call frame needs to be at least big enough for linkage and 8 args. - return getLinkageSize(isPPC64, isDarwinABI) + - getMinCallArgumentsSize(isPPC64, isDarwinABI); - } - // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const { Index: llvm-suse/lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ llvm-suse/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -629,81 +629,99 @@ static unsigned getCRIdxForSetCC(ISD::Co // getVCmpInst: return the vector compare instruction for the specified // vector type and condition code. Since this is for altivec specific code, // only support the altivec types (v16i8, v8i16, v4i32, and v4f32). -static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { - switch (CC) { - case ISD::SETEQ: - case ISD::SETUEQ: - case ISD::SETNE: - case ISD::SETUNE: - if (VecVT == MVT::v16i8) - return PPC::VCMPEQUB; - else if (VecVT == MVT::v8i16) - return PPC::VCMPEQUH; - else if (VecVT == MVT::v4i32) - return PPC::VCMPEQUW; - // v4f32 != v4f32 could be translate to unordered not equal - else if (VecVT == MVT::v4f32) - return PPC::VCMPEQFP; - break; - case ISD::SETLT: - case ISD::SETGT: - case ISD::SETLE: - case ISD::SETGE: - if (VecVT == MVT::v16i8) - return PPC::VCMPGTSB; - else if (VecVT == MVT::v8i16) - return PPC::VCMPGTSH; - else if (VecVT == MVT::v4i32) - return PPC::VCMPGTSW; - else if (VecVT == MVT::v4f32) - return PPC::VCMPGTFP; - break; - case ISD::SETULT: - case ISD::SETUGT: - case ISD::SETUGE: - case ISD::SETULE: - if (VecVT == MVT::v16i8) - return PPC::VCMPGTUB; - else if (VecVT == MVT::v8i16) - return PPC::VCMPGTUH; - else if (VecVT == MVT::v4i32) - return PPC::VCMPGTUW; - break; - case ISD::SETOEQ: - if (VecVT == MVT::v4f32) - return PPC::VCMPEQFP; - break; - case ISD::SETOLT: - case ISD::SETOGT: - case ISD::SETOLE: - if (VecVT == MVT::v4f32) - return PPC::VCMPGTFP; - break; - case ISD::SETOGE: - if (VecVT == MVT::v4f32) - return PPC::VCMPGEFP; - break; - default: - break; - } - llvm_unreachable("Invalid integer vector compare condition"); -} +static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, + bool &Swap, bool &Negate) { + Swap = false; + Negate = false; -// getVCmpEQInst: return the equal compare instruction for the specified vector -// type. Since this is for altivec specific code, only support the altivec -// types (v16i8, v8i16, v4i32, and v4f32). -static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) { - switch (VecVT) { - case MVT::v16i8: - return PPC::VCMPEQUB; - case MVT::v8i16: - return PPC::VCMPEQUH; - case MVT::v4i32: - return PPC::VCMPEQUW; - case MVT::v4f32: - return PPC::VCMPEQFP; - default: - llvm_unreachable("Invalid integer vector compare condition"); + if (VecVT.isFloatingPoint()) { + /* Handle some cases by swapping input operands. */ + switch (CC) { + case ISD::SETLE: CC = ISD::SETGE; Swap = true; break; + case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; + case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; + case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; + case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; + case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; + default: break; + } + /* Handle some cases by negating the result. */ + switch (CC) { + case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; + case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break; + case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; + case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; + default: break; + } + /* We have instructions implementing the remaining cases. */ + switch (CC) { + case ISD::SETEQ: + case ISD::SETOEQ: + if (VecVT == MVT::v4f32) + return PPC::VCMPEQFP; + break; + case ISD::SETGT: + case ISD::SETOGT: + if (VecVT == MVT::v4f32) + return PPC::VCMPGTFP; + break; + case ISD::SETGE: + case ISD::SETOGE: + if (VecVT == MVT::v4f32) + return PPC::VCMPGEFP; + break; + default: + break; + } + llvm_unreachable("Invalid floating-point vector compare condition"); + } else { + /* Handle some cases by swapping input operands. */ + switch (CC) { + case ISD::SETGE: CC = ISD::SETLE; Swap = true; break; + case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; + case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; + case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; + default: break; + } + /* Handle some cases by negating the result. */ + switch (CC) { + case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; + case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; + case ISD::SETLE: CC = ISD::SETGT; Negate = true; break; + case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; + default: break; + } + /* We have instructions implementing the remaining cases. */ + switch (CC) { + case ISD::SETEQ: + case ISD::SETUEQ: + if (VecVT == MVT::v16i8) + return PPC::VCMPEQUB; + else if (VecVT == MVT::v8i16) + return PPC::VCMPEQUH; + else if (VecVT == MVT::v4i32) + return PPC::VCMPEQUW; + break; + case ISD::SETGT: + if (VecVT == MVT::v16i8) + return PPC::VCMPGTSB; + else if (VecVT == MVT::v8i16) + return PPC::VCMPGTSH; + else if (VecVT == MVT::v4i32) + return PPC::VCMPGTSW; + break; + case ISD::SETUGT: + if (VecVT == MVT::v16i8) + return PPC::VCMPGTUB; + else if (VecVT == MVT::v8i16) + return PPC::VCMPGTUH; + else if (VecVT == MVT::v4i32) + return PPC::VCMPGTUW; + break; + default: + break; + } + llvm_unreachable("Invalid integer vector compare condition"); } } @@ -795,54 +813,17 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN // vector compare operations return the same type as the operands. if (LHS.getValueType().isVector()) { EVT VecVT = LHS.getValueType(); - MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; - unsigned int VCmpInst = getVCmpInst(VT, CC); - - switch (CC) { - case ISD::SETEQ: - case ISD::SETOEQ: - case ISD::SETUEQ: - return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); - case ISD::SETNE: - case ISD::SETONE: - case ISD::SETUNE: { - SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); - return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); - } - case ISD::SETLT: - case ISD::SETOLT: - case ISD::SETULT: - return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS); - case ISD::SETGT: - case ISD::SETOGT: - case ISD::SETUGT: - return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); - case ISD::SETGE: - case ISD::SETOGE: - case ISD::SETUGE: { - // Small optimization: Altivec provides a 'Vector Compare Greater Than - // or Equal To' instruction (vcmpgefp), so in this case there is no - // need for extra logic for the equal compare. - if (VecVT.getSimpleVT().isFloatingPoint()) { - return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); - } else { - SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); - unsigned int VCmpEQInst = getVCmpEQInst(VT); - SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); - return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ); - } - } - case ISD::SETLE: - case ISD::SETOLE: - case ISD::SETULE: { - SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0); - unsigned int VCmpEQInst = getVCmpEQInst(VT); - SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); - return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ); - } - default: - llvm_unreachable("Invalid vector compare type: should be expanded by legalize"); + bool Swap, Negate; + unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC, Swap, Negate); + if (Swap) + std::swap(LHS, RHS); + + if (Negate) { + SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); + return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); } + + return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); } bool Inv; Index: llvm-suse/lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCISelLowering.cpp +++ llvm-suse/lib/Target/PowerPC/PPCISelLowering.cpp @@ -413,6 +413,8 @@ PPCTargetLowering::PPCTargetLowering(PPC setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); setOperationAction(ISD::BUILD_VECTOR, VT, Expand); + setOperationAction(ISD::MULHU, VT, Expand); + setOperationAction(ISD::MULHS, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand); setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::UDIVREM, VT, Expand); @@ -484,11 +486,6 @@ PPCTargetLowering::PPCTargetLowering(PPC // Altivec does not contain unordered floating-point compare instructions setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); - setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand); - setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); - setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); - setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); - setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); } @@ -637,7 +634,6 @@ const char *PPCTargetLowering::getTarget case PPCISD::Hi: return "PPCISD::Hi"; case PPCISD::Lo: return "PPCISD::Lo"; case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; - case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; case PPCISD::LOAD: return "PPCISD::LOAD"; case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; @@ -717,15 +713,29 @@ static bool isConstantOrUndef(int Op, in /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUHUM instruction. -bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { - if (!isUnary) { +/// The ShuffleKind distinguishes between big-endian operations with +/// two different inputs (0), either-endian operations with two identical +/// inputs (1), and little-endian operantion with two different inputs (2). +/// For the latter, the input operands are swapped (see PPCInstrAltivec.td). +bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, + SelectionDAG &DAG) { + if (ShuffleKind == 0) { + if (DAG.getTarget().getDataLayout()->isLittleEndian()) + return false; for (unsigned i = 0; i != 16; ++i) - if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) + if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) return false; - } else { + } else if (ShuffleKind == 2) { + if (!DAG.getTarget().getDataLayout()->isLittleEndian()) + return false; + for (unsigned i = 0; i != 16; ++i) + if (!isConstantOrUndef(N->getMaskElt(i), i*2)) + return false; + } else if (ShuffleKind == 1) { + unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1; for (unsigned i = 0; i != 8; ++i) - if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || - !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) + if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) || + !isConstantOrUndef(N->getMaskElt(i+8), i*2+j)) return false; } return true; @@ -733,18 +743,33 @@ bool PPC::isVPKUHUMShuffleMask(ShuffleVe /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUWUM instruction. -bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { - if (!isUnary) { +/// The ShuffleKind distinguishes between big-endian operations with +/// two different inputs (0), either-endian operations with two identical +/// inputs (1), and little-endian operantion with two different inputs (2). +/// For the latter, the input operands are swapped (see PPCInstrAltivec.td). +bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, + SelectionDAG &DAG) { + if (ShuffleKind == 0) { + if (DAG.getTarget().getDataLayout()->isLittleEndian()) + return false; for (unsigned i = 0; i != 16; i += 2) if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) return false; - } else { + } else if (ShuffleKind == 2) { + if (!DAG.getTarget().getDataLayout()->isLittleEndian()) + return false; + for (unsigned i = 0; i != 16; i += 2) + if (!isConstantOrUndef(N->getMaskElt(i ), i*2) || + !isConstantOrUndef(N->getMaskElt(i+1), i*2+1)) + return false; + } else if (ShuffleKind == 1) { + unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 2; for (unsigned i = 0; i != 8; i += 2) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || - !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || - !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) + if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) || + !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) || + !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) || + !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1)) return false; } return true; @@ -771,27 +796,64 @@ static bool isVMerge(ShuffleVectorSDNode } /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for -/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). +/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes). +/// The ShuffleKind distinguishes between big-endian merges with two +/// different inputs (0), either-endian merges with two identical inputs (1), +/// and little-endian merges with two different inputs (2). For the latter, +/// the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, - bool isUnary) { - if (!isUnary) - return isVMerge(N, UnitSize, 8, 24); - return isVMerge(N, UnitSize, 8, 8); + unsigned ShuffleKind, SelectionDAG &DAG) { + if (DAG.getTarget().getDataLayout()->isLittleEndian()) { + if (ShuffleKind == 1) // unary + return isVMerge(N, UnitSize, 0, 0); + else if (ShuffleKind == 2) // swapped + return isVMerge(N, UnitSize, 0, 16); + else + return false; + } else { + if (ShuffleKind == 1) // unary + return isVMerge(N, UnitSize, 8, 8); + else if (ShuffleKind == 0) // normal + return isVMerge(N, UnitSize, 8, 24); + else + return false; + } } /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for -/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). +/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes). +/// The ShuffleKind distinguishes between big-endian merges with two +/// different inputs (0), either-endian merges with two identical inputs (1), +/// and little-endian merges with two different inputs (2). For the latter, +/// the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, - bool isUnary) { - if (!isUnary) - return isVMerge(N, UnitSize, 0, 16); - return isVMerge(N, UnitSize, 0, 0); + unsigned ShuffleKind, SelectionDAG &DAG) { + if (DAG.getTarget().getDataLayout()->isLittleEndian()) { + if (ShuffleKind == 1) // unary + return isVMerge(N, UnitSize, 8, 8); + else if (ShuffleKind == 2) // swapped + return isVMerge(N, UnitSize, 8, 24); + else + return false; + } else { + if (ShuffleKind == 1) // unary + return isVMerge(N, UnitSize, 0, 0); + else if (ShuffleKind == 0) // normal + return isVMerge(N, UnitSize, 0, 16); + else + return false; + } } /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. -int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { +/// The ShuffleKind distinguishes between big-endian operations with two +/// different inputs (0), either-endian operations with two identical inputs +/// (1), and little-endian operations with two different inputs (2). For the +/// latter, the input operands are swapped (see PPCInstrAltivec.td). +int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, + SelectionDAG &DAG) { assert(N->getValueType(0) == MVT::v16i8 && "PPC only supports shuffles by bytes!"); @@ -808,19 +870,26 @@ int PPC::isVSLDOIShuffleMask(SDNode *N, // numbered from this value. unsigned ShiftAmt = SVOp->getMaskElt(i); if (ShiftAmt < i) return -1; + ShiftAmt -= i; + bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian(); - if (!isUnary) { + if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) { // Check the rest of the elements to see if they are consecutive. for (++i; i != 16; ++i) if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) return -1; - } else { + } else if (ShuffleKind == 1) { // Check the rest of the elements to see if they are consecutive. for (++i; i != 16; ++i) if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) return -1; - } + } else + return -1; + + if (ShuffleKind == 2 && isLE) + ShiftAmt = 16 - ShiftAmt; + return ShiftAmt; } @@ -872,10 +941,14 @@ bool PPC::isAllNegativeZeroVector(SDNode /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. -unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { +unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize, + SelectionDAG &DAG) { ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); assert(isSplatShuffleMask(SVOp, EltSize)); - return SVOp->getMaskElt(0) / EltSize; + if (DAG.getTarget().getDataLayout()->isLittleEndian()) + return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize); + else + return SVOp->getMaskElt(0) / EltSize; } /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed @@ -1148,7 +1221,13 @@ bool PPCTargetLowering::SelectAddressReg if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't // carry. - Base = N.getOperand(0); + if (FrameIndexSDNode *FI = + dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { + Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); + fixupFuncForFI(DAG, FI->getIndex(), N.getValueType()); + } else { + Base = N.getOperand(0); + } Disp = DAG.getTargetConstant(imm, N.getValueType()); return true; } @@ -1925,11 +2004,114 @@ static unsigned CalculateStackSlotSize(E unsigned ArgSize = ArgVT.getSizeInBits()/8; if (Flags.isByVal()) ArgSize = Flags.getByValSize(); - ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + + // Round up to multiples of the pointer size, except for array members, + // which are always packed. + if (!Flags.isInConsecutiveRegs()) + ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; return ArgSize; } +/// CalculateStackSlotAlignment - Calculates the alignment of this argument +/// on the stack. +static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, + ISD::ArgFlagsTy Flags, + unsigned PtrByteSize) { + unsigned Align = PtrByteSize; + + // Altivec parameters are padded to a 16 byte boundary. + if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || + ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8) + Align = 16; + + // ByVal parameters are aligned as requested. + if (Flags.isByVal()) { + unsigned BVAlign = Flags.getByValAlign(); + if (BVAlign > PtrByteSize) { + if (BVAlign % PtrByteSize != 0) + llvm_unreachable( + "ByVal alignment is not a multiple of the pointer size"); + + Align = BVAlign; + } + } + + // Array members are always packed to their original alignment. + if (Flags.isInConsecutiveRegs()) { + // If the array member was split into multiple registers, the first + // needs to be aligned to the size of the full type. (Except for + // ppcf128, which is only aligned as its f64 components.) + if (Flags.isSplit() && OrigVT != MVT::ppcf128) + Align = OrigVT.getStoreSize(); + else + Align = ArgVT.getStoreSize(); + } + + return Align; +} + +/// CalculateStackSlotUsed - Return whether this argument will use its +/// stack slot (instead of being passed in registers). ArgOffset, +/// AvailableFPRs, and AvailableVRs must hold the current argument +/// position, and will be updated to account for this argument. +static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, + ISD::ArgFlagsTy Flags, + unsigned PtrByteSize, + unsigned LinkageSize, + unsigned ParamAreaSize, + unsigned &ArgOffset, + unsigned &AvailableFPRs, + unsigned &AvailableVRs) { + bool UseMemory = false; + + // Respect alignment of argument on the stack. + unsigned Align = + CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); + ArgOffset = ((ArgOffset + Align - 1) / Align) * Align; + // If there's no space left in the argument save area, we must + // use memory (this check also catches zero-sized arguments). + if (ArgOffset >= LinkageSize + ParamAreaSize) + UseMemory = true; + + // Allocate argument on the stack. + ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); + if (Flags.isInConsecutiveRegsLast()) + ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + // If we overran the argument save area, we must use memory + // (this check catches arguments passed partially in memory) + if (ArgOffset > LinkageSize + ParamAreaSize) + UseMemory = true; + + // However, if the argument is actually passed in an FPR or a VR, + // we don't use memory after all. + if (!Flags.isByVal()) { + if (ArgVT == MVT::f32 || ArgVT == MVT::f64) + if (AvailableFPRs > 0) { + --AvailableFPRs; + return false; + } + if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || + ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8) + if (AvailableVRs > 0) { + --AvailableVRs; + return false; + } + } + + return UseMemory; +} + +/// EnsureStackAlignment - Round stack frame size up from NumBytes to +/// ensure minimum alignment required for target. +static unsigned EnsureStackAlignment(const TargetMachine &Target, + unsigned NumBytes) { + unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment(); + unsigned AlignMask = TargetAlign - 1; + NumBytes = (NumBytes + AlignMask) & ~AlignMask; + return NumBytes; +} + SDValue PPCTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, @@ -2005,7 +2187,8 @@ PPCTargetLowering::LowerFormalArguments_ getTargetMachine(), ArgLocs, *DAG.getContext()); // Reserve space for the linkage area on the stack. - CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); + unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false); + CCInfo.AllocateStack(LinkageSize, PtrByteSize); CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4); @@ -2072,23 +2255,14 @@ PPCTargetLowering::LowerFormalArguments_ // Area that is at least reserved in the caller of this function. unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); + MinReservedArea = std::max(MinReservedArea, LinkageSize); // Set the size that is at least reserved in caller of this function. Tail // call optimized function's reserved stack space needs to be aligned so that // taking the difference between two stack areas will result in an aligned // stack. - PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); - - MinReservedArea = - std::max(MinReservedArea, - PPCFrameLowering::getMinCallFrameSize(false, false)); - - unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> - getStackAlignment(); - unsigned AlignMask = TargetAlign-1; - MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; - - FI->setMinReservedArea(MinReservedArea); + MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea); + FuncInfo->setMinReservedArea(MinReservedArea); SmallVector<SDValue, 8> MemOps; @@ -2185,32 +2359,6 @@ PPCTargetLowering::extendArgForPPC64(ISD return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); } -// Set the size that is at least reserved in caller of this function. Tail -// call optimized functions' reserved stack space needs to be aligned so that -// taking the difference between two stack areas will result in an aligned -// stack. -void -PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, - unsigned nAltivecParamsAtEnd, - unsigned MinReservedArea, - bool isPPC64) const { - PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); - // Add the Altivec parameters at the end, if needed. - if (nAltivecParamsAtEnd) { - MinReservedArea = ((MinReservedArea+15)/16)*16; - MinReservedArea += 16*nAltivecParamsAtEnd; - } - MinReservedArea = - std::max(MinReservedArea, - PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); - unsigned TargetAlign - = DAG.getMachineFunction().getTarget().getFrameLowering()-> - getStackAlignment(); - unsigned AlignMask = TargetAlign-1; - MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; - FI->setMinReservedArea(MinReservedArea); -} - SDValue PPCTargetLowering::LowerFormalArguments_64SVR4( SDValue Chain, @@ -2221,6 +2369,8 @@ PPCTargetLowering::LowerFormalArguments_ SmallVectorImpl<SDValue> &InVals) const { // TODO: add description of PPC stack frame format, or at least some docs. // + bool isELFv2ABI = PPCSubTarget.isELFv2ABI(); + bool isLittleEndian = PPCSubTarget.isLittleEndian(); MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); @@ -2231,9 +2381,8 @@ PPCTargetLowering::LowerFormalArguments_ (CallConv == CallingConv::Fast)); unsigned PtrByteSize = 8; - unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); - // Area that is at least reserved in caller of this function. - unsigned MinReservedArea = ArgOffset; + unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false, + isELFv2ABI); static const uint16_t GPR[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, @@ -2251,43 +2400,52 @@ PPCTargetLowering::LowerFormalArguments_ const unsigned Num_FPR_Regs = 13; const unsigned Num_VR_Regs = array_lengthof(VR); - unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; + // Do a first pass over the arguments to determine whether the ABI + // guarantees that our caller has allocated the parameter save area + // on its stack frame. In the ELFv1 ABI, this is always the case; + // in the ELFv2 ABI, it is true if this is a vararg function or if + // any parameter is located in a stack slot. + + bool HasParameterArea = !isELFv2ABI || isVarArg; + unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize; + unsigned NumBytes = LinkageSize; + unsigned AvailableFPRs = Num_FPR_Regs; + unsigned AvailableVRs = Num_VR_Regs; + for (unsigned i = 0, e = Ins.size(); i != e; ++i) + if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags, + PtrByteSize, LinkageSize, ParamAreaSize, + NumBytes, AvailableFPRs, AvailableVRs)) + HasParameterArea = true; // Add DAG nodes to load the arguments or copy them out of registers. On // entry to a function on PPC, the arguments start after the linkage area, // although the first ones are often in registers. + unsigned ArgOffset = LinkageSize; + unsigned GPR_idx, FPR_idx = 0, VR_idx = 0; SmallVector<SDValue, 8> MemOps; - unsigned nAltivecParamsAtEnd = 0; Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); unsigned CurArgIdx = 0; for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { SDValue ArgVal; bool needsLoad = false; EVT ObjectVT = Ins[ArgNo].VT; + EVT OrigVT = Ins[ArgNo].ArgVT; unsigned ObjSize = ObjectVT.getSizeInBits()/8; unsigned ArgSize = ObjSize; ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx); CurArgIdx = Ins[ArgNo].OrigArgIndex; + /* Respect alignment of argument on the stack. */ + unsigned Align = + CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); + ArgOffset = ((ArgOffset + Align - 1) / Align) * Align; unsigned CurArgOffset = ArgOffset; - // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. - if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || - ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { - if (isVarArg) { - MinReservedArea = ((MinReservedArea+15)/16)*16; - MinReservedArea += CalculateStackSlotSize(ObjectVT, - Flags, - PtrByteSize); - } else - nAltivecParamsAtEnd++; - } else - // Calculate min reserved area. - MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, - Flags, - PtrByteSize); + /* Compute GPR index associated with argument offset. */ + GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize; + GPR_idx = std::min(GPR_idx, Num_GPR_Regs); // FIXME the codegen can be much improved in some cases. // We do not have to keep everything in memory. @@ -2309,21 +2467,31 @@ PPCTargetLowering::LowerFormalArguments_ continue; } - unsigned BVAlign = Flags.getByValAlign(); - if (BVAlign > 8) { - ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign; - CurArgOffset = ArgOffset; - } - - // All aggregates smaller than 8 bytes must be passed right-justified. - if (ObjSize < PtrByteSize) - CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize); - // The value of the object is its address. - int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); + // Create a stack object covering all stack doublewords occupied + // by the argument. If the argument is (fully or partially) on + // the stack, or if the argument is fully in registers but the + // caller has allocated the parameter save anyway, we can refer + // directly to the caller's stack frame. Otherwise, create a + // local copy in our own frame. + int FI; + if (HasParameterArea || + ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize) + FI = MFI->CreateFixedObject(ArgSize, ArgOffset, true); + else + FI = MFI->CreateStackObject(ArgSize, Align, false); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - InVals.push_back(FIN); - if (ObjSize < 8) { + // Handle aggregates smaller than 8 bytes. + if (ObjSize < PtrByteSize) { + // The value of the object is its address, which differs from the + // address of the enclosing doubleword on big-endian systems. + SDValue Arg = FIN; + if (!isLittleEndian) { + SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT); + Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff); + } + InVals.push_back(Arg); + if (GPR_idx != Num_GPR_Regs) { unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); @@ -2332,25 +2500,19 @@ PPCTargetLowering::LowerFormalArguments_ if (ObjSize==1 || ObjSize==2 || ObjSize==4) { EVT ObjType = (ObjSize == 1 ? MVT::i8 : (ObjSize == 2 ? MVT::i16 : MVT::i32)); - Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, + Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg, MachinePointerInfo(FuncArg), ObjType, false, false, 0); } else { // For sizes that don't fit a truncating store (3, 5, 6, 7), // store the whole register as-is to the parameter save area - // slot. The address of the parameter was already calculated - // above (InVals.push_back(FIN)) to be the right-justified - // offset within the slot. For this store, we need a new - // frame index that points at the beginning of the slot. - int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); - SDValue FIN = DAG.getFrameIndex(FI, PtrVT); + // slot. Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo(FuncArg), false, false, 0); } MemOps.push_back(Store); - ++GPR_idx; } // Whether we copied from a register or not, advance the offset // into the parameter save area by a full doubleword. @@ -2358,27 +2520,29 @@ PPCTargetLowering::LowerFormalArguments_ continue; } + // The value of the object is its address, which is the address of + // its first stack doubleword. + InVals.push_back(FIN); + + // Store whatever pieces of the object are in registers to memory. for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { - // Store whatever pieces of the object are in registers - // to memory. ArgOffset will be the address of the beginning - // of the object. - if (GPR_idx != Num_GPR_Regs) { - unsigned VReg; - VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); - int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); - SDValue FIN = DAG.getFrameIndex(FI, PtrVT); - SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); - SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, - MachinePointerInfo(FuncArg, j), - false, false, 0); - MemOps.push_back(Store); - ++GPR_idx; - ArgOffset += PtrByteSize; - } else { - ArgOffset += ArgSize - j; + if (GPR_idx == Num_GPR_Regs) break; + + unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); + SDValue Addr = FIN; + if (j) { + SDValue Off = DAG.getConstant(j, PtrVT); + Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off); } + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr, + MachinePointerInfo(FuncArg, j), + false, false, 0); + MemOps.push_back(Store); + ++GPR_idx; } + ArgOffset += ArgSize; continue; } @@ -2386,6 +2550,9 @@ PPCTargetLowering::LowerFormalArguments_ default: llvm_unreachable("Unhandled argument type!"); case MVT::i32: case MVT::i64: + // These can be scalar arguments or elements of an integer array type + // passed directly. Clang may use those instead of "byval" aggregate + // types to avoid forcing arguments to memory unnecessarily. if (GPR_idx != Num_GPR_Regs) { unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); @@ -2394,8 +2561,6 @@ PPCTargetLowering::LowerFormalArguments_ // PPC64 passes i8, i16, and i32 values in i64 registers. Promote // value to MVT::i64 and then truncate to the correct register size. ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); - - ++GPR_idx; } else { needsLoad = true; ArgSize = PtrByteSize; @@ -2405,11 +2570,9 @@ PPCTargetLowering::LowerFormalArguments_ case MVT::f32: case MVT::f64: - // Every 8 bytes of argument space consumes one of the GPRs available for - // argument passing. - if (GPR_idx != Num_GPR_Regs) { - ++GPR_idx; - } + // These can be scalar arguments or elements of a float array type + // passed directly. The latter are used to implement ELFv2 homogenous + // float aggregates. if (FPR_idx != Num_FPR_Regs) { unsigned VReg; @@ -2420,48 +2583,57 @@ PPCTargetLowering::LowerFormalArguments_ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); ++FPR_idx; + } else if (GPR_idx != Num_GPR_Regs) { + // This can only ever happen in the presence of f32 array types, + // since otherwise we never run out of FPRs before running out + // of GPRs. + unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); + ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); + + if (ObjectVT == MVT::f32) { + if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0)) + ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal, + DAG.getConstant(32, MVT::i32)); + ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); + } + + ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal); } else { needsLoad = true; - ArgSize = PtrByteSize; } - ArgOffset += 8; + // When passing an array of floats, the array occupies consecutive + // space in the argument area; only round up to the next doubleword + // at the end of the array. Otherwise, each float takes 8 bytes. + ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; + ArgOffset += ArgSize; + if (Flags.isInConsecutiveRegsLast()) + ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; break; case MVT::v4f32: case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: - // Note that vector arguments in registers don't reserve stack space, - // except in varargs functions. + // These can be scalar arguments or elements of a vector array type + // passed directly. The latter are used to implement ELFv2 homogenous + // vector aggregates. if (VR_idx != Num_VR_Regs) { unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); - if (isVarArg) { - while ((ArgOffset % 16) != 0) { - ArgOffset += PtrByteSize; - if (GPR_idx != Num_GPR_Regs) - GPR_idx++; - } - ArgOffset += 16; - GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? - } ++VR_idx; } else { - // Vectors are aligned. - ArgOffset = ((ArgOffset+15)/16)*16; - CurArgOffset = ArgOffset; - ArgOffset += 16; needsLoad = true; } + ArgOffset += 16; break; } // We need to load the argument to a virtual register if we determined // above that we ran out of physical registers of the appropriate type. if (needsLoad) { - int FI = MFI->CreateFixedObject(ObjSize, - CurArgOffset + (ArgSize - ObjSize), - isImmutable); + if (ObjSize < ArgSize && !isLittleEndian) + CurArgOffset += ArgSize - ObjSize; + int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), false, false, false, 0); @@ -2470,11 +2642,19 @@ PPCTargetLowering::LowerFormalArguments_ InVals.push_back(ArgVal); } + // Area that is at least reserved in the caller of this function. + unsigned MinReservedArea; + if (HasParameterArea) + MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize); + else + MinReservedArea = LinkageSize; + // Set the size that is at least reserved in caller of this function. Tail // call optimized functions' reserved stack space needs to be aligned so that // taking the difference between two stack areas will result in an aligned // stack. - setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true); + MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea); + FuncInfo->setMinReservedArea(MinReservedArea); // If the function takes variable number of arguments, make a frame index for // the start of the first vararg value... for expansion of llvm.va_start. @@ -2488,7 +2668,8 @@ PPCTargetLowering::LowerFormalArguments_ // If this function is vararg, store any remaining integer argument regs // to their spots on the stack so that they may be loaded by deferencing the // result of va_next. - for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { + for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize; + GPR_idx < Num_GPR_Regs; ++GPR_idx) { unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, @@ -2528,7 +2709,9 @@ PPCTargetLowering::LowerFormalArguments_ (CallConv == CallingConv::Fast)); unsigned PtrByteSize = isPPC64 ? 8 : 4; - unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); + unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true, + false); + unsigned ArgOffset = LinkageSize; // Area that is at least reserved in caller of this function. unsigned MinReservedArea = ArgOffset; @@ -2813,11 +2996,21 @@ PPCTargetLowering::LowerFormalArguments_ InVals.push_back(ArgVal); } + // Allow for Altivec parameters at the end, if needed. + if (nAltivecParamsAtEnd) { + MinReservedArea = ((MinReservedArea+15)/16)*16; + MinReservedArea += 16*nAltivecParamsAtEnd; + } + + // Area that is at least reserved in the caller of this function. + MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize); + // Set the size that is at least reserved in caller of this function. Tail // call optimized functions' reserved stack space needs to be aligned so that // taking the difference between two stack areas will result in an aligned // stack. - setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64); + MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea); + FuncInfo->setMinReservedArea(MinReservedArea); // If the function takes variable number of arguments, make a frame index for // the start of the first vararg value... for expansion of llvm.va_start. @@ -2857,74 +3050,6 @@ PPCTargetLowering::LowerFormalArguments_ return Chain; } -/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus -/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. -static unsigned -CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, - bool isPPC64, - bool isVarArg, - unsigned CC, - const SmallVectorImpl<ISD::OutputArg> - &Outs, - const SmallVectorImpl<SDValue> &OutVals, - unsigned &nAltivecParamsAtEnd) { - // Count how many bytes are to be pushed on the stack, including the linkage - // area, and parameter passing area. We start with 24/48 bytes, which is - // prereserved space for [SP][CR][LR][3 x unused]. - unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); - unsigned NumOps = Outs.size(); - unsigned PtrByteSize = isPPC64 ? 8 : 4; - - // Add up all the space actually used. - // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually - // they all go in registers, but we must reserve stack space for them for - // possible use by the caller. In varargs or 64-bit calls, parameters are - // assigned stack space in order, with padding so Altivec parameters are - // 16-byte aligned. - nAltivecParamsAtEnd = 0; - for (unsigned i = 0; i != NumOps; ++i) { - ISD::ArgFlagsTy Flags = Outs[i].Flags; - EVT ArgVT = Outs[i].VT; - // Varargs Altivec parameters are padded to a 16 byte boundary. - if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || - ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { - if (!isVarArg && !isPPC64) { - // Non-varargs Altivec parameters go after all the non-Altivec - // parameters; handle those later so we know how much padding we need. - nAltivecParamsAtEnd++; - continue; - } - // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. - NumBytes = ((NumBytes+15)/16)*16; - } - NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); - } - - // Allow for Altivec parameters at the end, if needed. - if (nAltivecParamsAtEnd) { - NumBytes = ((NumBytes+15)/16)*16; - NumBytes += 16*nAltivecParamsAtEnd; - } - - // The prolog code of the callee may store up to 8 GPR argument registers to - // the stack, allowing va_start to index over them in memory if its varargs. - // Because we cannot tell if this is needed on the caller side, we have to - // conservatively assume that it is needed. As such, make sure we have at - // least enough stack space for the caller to store the 8 GPRs. - NumBytes = std::max(NumBytes, - PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); - - // Tail call needs the stack to be aligned. - if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ - unsigned TargetAlign = DAG.getMachineFunction().getTarget(). - getFrameLowering()->getStackAlignment(); - unsigned AlignMask = TargetAlign-1; - NumBytes = (NumBytes + AlignMask) & ~AlignMask; - } - - return NumBytes; -} - /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be /// adjusted to accommodate the arguments for the tailcall. static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, @@ -3194,6 +3319,7 @@ unsigned PrepareCall(SelectionDAG &DAG, bool isPPC64 = PPCSubTarget.isPPC64(); bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); + bool isELFv2ABI = PPCSubTarget.isELFv2ABI(); EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); NodeTys.push_back(MVT::Other); // Returns a chain @@ -3202,11 +3328,12 @@ unsigned PrepareCall(SelectionDAG &DAG, unsigned CallOpc = PPCISD::CALL; bool needIndirectCall = true; - if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { - // If this is an absolute destination address, use the munged value. - Callee = SDValue(Dest, 0); - needIndirectCall = false; - } + if (!isSVR4ABI || !isPPC64) + if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { + // If this is an absolute destination address, use the munged value. + Callee = SDValue(Dest, 0); + needIndirectCall = false; + } if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 @@ -3257,7 +3384,7 @@ unsigned PrepareCall(SelectionDAG &DAG, // to do the call, we can't use PPCISD::CALL. SDValue MTCTROps[] = {Chain, Callee, InFlag}; - if (isSVR4ABI && isPPC64) { + if (isSVR4ABI && isPPC64 && !isELFv2ABI) { // Function pointers in the 64-bit SVR4 ABI do not point to the function // entry point, but to the function descriptor (the function entry point // address is part of the function descriptor though). @@ -3314,8 +3441,10 @@ unsigned PrepareCall(SelectionDAG &DAG, // additional register being allocated and an unnecessary move instruction // being generated. VTs = DAG.getVTList(MVT::Other, MVT::Glue); + SDValue TOCOff = DAG.getIntPtrConstant(8); + SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff); SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, - Callee, InFlag); + AddTOC, InFlag); Chain = LoadTOCPtr.getValue(0); InFlag = LoadTOCPtr.getValue(1); @@ -3335,7 +3464,7 @@ unsigned PrepareCall(SelectionDAG &DAG, CallOpc = PPCISD::BCTRL; Callee.setNode(0); // Add use of X11 (holding environment pointer) - if (isSVR4ABI && isPPC64) + if (isSVR4ABI && isPPC64 && !isELFv2ABI) Ops.push_back(DAG.getRegister(PPC::X11, PtrVT)); // Add CTR register as callee so a bctr can be emitted later. if (isTailCall) @@ -3357,6 +3486,10 @@ unsigned PrepareCall(SelectionDAG &DAG, Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); + // Direct calls in the ELFv2 ABI need the TOC register live into the call. + if (Callee.getNode() && isELFv2ABI) + Ops.push_back(DAG.getRegister(PPC::X2, PtrVT)); + return CallOpc; } @@ -3426,6 +3559,8 @@ PPCTargetLowering::FinishCall(CallingCon int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const { + + bool isELFv2ABI = PPCSubTarget.isELFv2ABI(); std::vector<EVT> NodeTys; SmallVector<SDValue, 8> Ops; unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, @@ -3499,7 +3634,12 @@ PPCTargetLowering::FinishCall(CallingCon if (needsTOCRestore) { SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); - Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT); + unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI); + SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset); + SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff); + Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag); InFlag = Chain.getValue(1); } @@ -3585,7 +3725,8 @@ PPCTargetLowering::LowerCall_32SVR4(SDVa getTargetMachine(), ArgLocs, *DAG.getContext()); // Reserve space for the linkage area on the stack. - CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); + CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false), + PtrByteSize); if (isVarArg) { // Handle fixed and variable vector arguments differently. @@ -3792,6 +3933,8 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { + bool isELFv2ABI = PPCSubTarget.isELFv2ABI(); + bool isLittleEndian = PPCSubTarget.isLittleEndian(); unsigned NumOps = Outs.size(); EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -3808,16 +3951,44 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa CallConv == CallingConv::Fast) MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); - unsigned nAltivecParamsAtEnd = 0; - // Count how many bytes are to be pushed on the stack, including the linkage - // area, and parameter passing area. We start with at least 48 bytes, which - // is reserved space for [SP][CR][LR][3 x unused]. - // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result - // of this call. - unsigned NumBytes = - CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv, - Outs, OutVals, nAltivecParamsAtEnd); + // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes + // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage + // area is 32 bytes reserved space for [SP][CR][LR][TOC]. + unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false, + isELFv2ABI); + unsigned NumBytes = LinkageSize; + + // Add up all the space actually used. + for (unsigned i = 0; i != NumOps; ++i) { + ISD::ArgFlagsTy Flags = Outs[i].Flags; + EVT ArgVT = Outs[i].VT; + EVT OrigVT = Outs[i].ArgVT; + + /* Respect alignment of argument on the stack. */ + unsigned Align = + CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); + NumBytes = ((NumBytes + Align - 1) / Align) * Align; + + NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); + if (Flags.isInConsecutiveRegsLast()) + NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + } + + unsigned NumBytesActuallyUsed = NumBytes; + + // The prolog code of the callee may store up to 8 GPR argument registers to + // the stack, allowing va_start to index over them in memory if its varargs. + // Because we cannot tell if this is needed on the caller side, we have to + // conservatively assume that it is needed. As such, make sure we have at + // least enough stack space for the caller to store the 8 GPRs. + // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area. + NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize); + + // Tail call needs the stack to be aligned. + if (getTargetMachine().Options.GuaranteedTailCallOpt && + CallConv == CallingConv::Fast) + NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes); // Calculate by how many bytes the stack has to be adjusted in case of tail // call optimization. @@ -3849,8 +4020,8 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa // memory. Also, if this is a vararg function, floating point operations // must be stored to our stack, and loaded into integer regs as well, if // any integer regs are available for argument passing. - unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); - unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; + unsigned ArgOffset = LinkageSize; + unsigned GPR_idx, FPR_idx = 0, VR_idx = 0; static const uint16_t GPR[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, @@ -3873,6 +4044,17 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa for (unsigned i = 0; i != NumOps; ++i) { SDValue Arg = OutVals[i]; ISD::ArgFlagsTy Flags = Outs[i].Flags; + EVT ArgVT = Outs[i].VT; + EVT OrigVT = Outs[i].ArgVT; + + /* Respect alignment of argument on the stack. */ + unsigned Align = + CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); + ArgOffset = ((ArgOffset + Align - 1) / Align) * Align; + + /* Compute GPR index associated with argument offset. */ + GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize; + GPR_idx = std::min(GPR_idx, NumGPRs); // PtrOff will be used to store the current argument to the stack if a // register cannot be found for it. @@ -3905,15 +4087,6 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa if (Size == 0) continue; - unsigned BVAlign = Flags.getByValAlign(); - if (BVAlign > 8) { - if (BVAlign % PtrByteSize != 0) - llvm_unreachable( - "ByVal alignment is not a multiple of the pointer size"); - - ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign; - } - // All aggregates smaller than 8 bytes must be passed right-justified. if (Size==1 || Size==2 || Size==4) { EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); @@ -3922,7 +4095,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa MachinePointerInfo(), VT, false, false, 0); MemOpChains.push_back(Load.getValue(1)); - RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); + RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load)); ArgOffset += PtrByteSize; continue; @@ -3930,9 +4103,12 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa } if (GPR_idx == NumGPRs && Size < 8) { - SDValue Const = DAG.getConstant(PtrByteSize - Size, - PtrOff.getValueType()); - SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); + SDValue AddPtr = PtrOff; + if (!isLittleEndian) { + SDValue Const = DAG.getConstant(PtrByteSize - Size, + PtrOff.getValueType()); + AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); + } Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, CallSeqStart, Flags, DAG, dl); @@ -3967,8 +4143,11 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa // small aggregates, particularly for packed ones. // FIXME: It would be preferable to use the slot in the // parameter save area instead of a new local variable. - SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); - SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); + SDValue AddPtr = PtrOff; + if (!isLittleEndian) { + SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); + AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); + } Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, CallSeqStart, Flags, DAG, dl); @@ -3978,7 +4157,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa MachinePointerInfo(), false, false, false, 0); MemOpChains.push_back(Load.getValue(1)); - RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); + RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load)); // Done with this argument. ArgOffset += PtrByteSize; @@ -4009,8 +4188,11 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i32: case MVT::i64: + // These can be scalar arguments or elements of an integer array type + // passed directly. Clang may use those instead of "byval" aggregate + // types to avoid forcing arguments to memory unnecessarily. if (GPR_idx != NumGPRs) { - RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); + RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg)); } else { LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, true, isTailCall, false, MemOpChains, @@ -4019,40 +4201,70 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa ArgOffset += PtrByteSize; break; case MVT::f32: - case MVT::f64: - if (FPR_idx != NumFPRs) { - RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); + case MVT::f64: { + // These can be scalar arguments or elements of a float array type + // passed directly. The latter are used to implement ELFv2 homogenous + // float aggregates. + + // Named arguments go into FPRs first, and once they overflow, the + // remaining arguments go into GPRs and then the parameter save area. + // Unnamed arguments for vararg functions always go to GPRs and + // then the parameter save area. For now, put all arguments to vararg + // routines always in both locations (FPR *and* GPR or stack slot). + bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs; - if (isVarArg) { - // A single float or an aggregate containing only a single float - // must be passed right-justified in the stack doubleword, and - // in the GPR, if one is available. - SDValue StoreOff; - if (Arg.getSimpleValueType().SimpleTy == MVT::f32) { - SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); - StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); - } else - StoreOff = PtrOff; + // First load the argument into the next available FPR. + if (FPR_idx != NumFPRs) + RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); - SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff, - MachinePointerInfo(), false, false, 0); - MemOpChains.push_back(Store); + // Next, load the argument into GPR or stack slot if needed. + if (!NeedGPROrStack) + ; + else if (GPR_idx != NumGPRs) { + // In the non-vararg case, this can only ever happen in the + // presence of f32 array types, since otherwise we never run + // out of FPRs before running out of GPRs. + SDValue ArgVal; + + // Double values are always passed in a single GPR. + if (Arg.getValueType() != MVT::f32) { + ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); + + // Non-array float values are extended and passed in a GPR. + } else if (!Flags.isInConsecutiveRegs()) { + ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); + ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); + + // If we have an array of floats, we collect every odd element + // together with its predecessor into one GPR. + } else if (ArgOffset % PtrByteSize != 0) { + SDValue Lo, Hi; + Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]); + Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); + if (!isLittleEndian) + std::swap(Lo, Hi); + ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + + // The final element, if even, goes into the first half of a GPR. + } else if (Flags.isInConsecutiveRegsLast()) { + ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); + ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); + if (!isLittleEndian) + ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, + DAG.getConstant(32, MVT::i32)); + + // Non-final even elements are skipped; they will be handled + // together the with subsequent argument on the next go-around. + } else + ArgVal = SDValue(); - // Float varargs are always shadowed in available integer registers - if (GPR_idx != NumGPRs) { - SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, - MachinePointerInfo(), false, false, - false, 0); - MemOpChains.push_back(Load.getValue(1)); - RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); - } - } else if (GPR_idx != NumGPRs) - // If we have any FPRs remaining, we may also have GPRs remaining. - ++GPR_idx; + if (ArgVal.getNode()) + RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal)); } else { // Single-precision floating-point values are mapped to the // second (rightmost) word of the stack doubleword. - if (Arg.getValueType() == MVT::f32) { + if (Arg.getValueType() == MVT::f32 && + !isLittleEndian && !Flags.isInConsecutiveRegs()) { SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); } @@ -4061,27 +4273,30 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa true, isTailCall, false, MemOpChains, TailCallArguments, dl); } - ArgOffset += 8; + // When passing an array of floats, the array occupies consecutive + // space in the argument area; only round up to the next doubleword + // at the end of the array. Otherwise, each float takes 8 bytes. + ArgOffset += (Arg.getValueType() == MVT::f32 && + Flags.isInConsecutiveRegs()) ? 4 : 8; + if (Flags.isInConsecutiveRegsLast()) + ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; break; + } case MVT::v4f32: case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: + // These can be scalar arguments or elements of a vector array type + // passed directly. The latter are used to implement ELFv2 homogenous + // vector aggregates. + + // For a varargs call, named arguments go into VRs or on the stack as + // usual; unnamed arguments always go to the stack or the corresponding + // GPRs when within range. For now, we always put the value in both + // locations (or even all three). if (isVarArg) { - // These go aligned on the stack, or in the corresponding R registers - // when within range. The Darwin PPC ABI doc claims they also go in - // V registers; in fact gcc does this only for arguments that are - // prototyped, not for those that match the ... We do it for all - // arguments, seems to work. - while (ArgOffset % 16 !=0) { - ArgOffset += PtrByteSize; - if (GPR_idx != NumGPRs) - GPR_idx++; - } // We could elide this store in the case where the object fits // entirely in R registers. Maybe later. - PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, - DAG.getConstant(ArgOffset, PtrVT)); SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), false, false, 0); MemOpChains.push_back(Store); @@ -4106,21 +4321,22 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa break; } - // Non-varargs Altivec params generally go in registers, but have - // stack space allocated at the end. + // Non-varargs Altivec params go into VRs or on the stack. if (VR_idx != NumVRs) { - // Doesn't have GPR space allocated. RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); } else { LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, true, isTailCall, true, MemOpChains, TailCallArguments, dl); - ArgOffset += 16; } + ArgOffset += 16; break; } } + assert(NumBytesActuallyUsed == ArgOffset); + (void)NumBytesActuallyUsed; + if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); @@ -4130,19 +4346,20 @@ PPCTargetLowering::LowerCall_64SVR4(SDVa // pointers in the 64-bit SVR4 ABI. if (!isTailCall && !dyn_cast<GlobalAddressSDNode>(Callee) && - !dyn_cast<ExternalSymbolSDNode>(Callee) && - !isBLACompatibleAddress(Callee, DAG)) { + !dyn_cast<ExternalSymbolSDNode>(Callee)) { // Load r2 into a virtual register and store it to the TOC save area. SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); // TOC save area offset. - SDValue PtrOff = DAG.getIntPtrConstant(40); + unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI); + SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset); SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), false, false, 0); - // R12 must contain the address of an indirect callee. This does not - // mean the MTCTR instruction must use R12; it's easier to model this - // as an extra parameter, so do that. - RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); + // In the ELFv2 ABI, R12 must contain the address of an indirect callee. + // This does not mean the MTCTR instruction must use R12; it's easier + // to model this as an extra parameter, so do that. + if (isELFv2ABI) + RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); } // Build a sequence of copy-to-reg nodes chained together with token chain @@ -4190,15 +4407,55 @@ PPCTargetLowering::LowerCall_Darwin(SDVa CallConv == CallingConv::Fast) MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); - unsigned nAltivecParamsAtEnd = 0; - // Count how many bytes are to be pushed on the stack, including the linkage // area, and parameter passing area. We start with 24/48 bytes, which is // prereserved space for [SP][CR][LR][3 x unused]. - unsigned NumBytes = - CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, - Outs, OutVals, - nAltivecParamsAtEnd); + unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true, + false); + unsigned NumBytes = LinkageSize; + + // Add up all the space actually used. + // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually + // they all go in registers, but we must reserve stack space for them for + // possible use by the caller. In varargs or 64-bit calls, parameters are + // assigned stack space in order, with padding so Altivec parameters are + // 16-byte aligned. + unsigned nAltivecParamsAtEnd = 0; + for (unsigned i = 0; i != NumOps; ++i) { + ISD::ArgFlagsTy Flags = Outs[i].Flags; + EVT ArgVT = Outs[i].VT; + // Varargs Altivec parameters are padded to a 16 byte boundary. + if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || + ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8) { + if (!isVarArg && !isPPC64) { + // Non-varargs Altivec parameters go after all the non-Altivec + // parameters; handle those later so we know how much padding we need. + nAltivecParamsAtEnd++; + continue; + } + // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. + NumBytes = ((NumBytes+15)/16)*16; + } + NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); + } + + // Allow for Altivec parameters at the end, if needed. + if (nAltivecParamsAtEnd) { + NumBytes = ((NumBytes+15)/16)*16; + NumBytes += 16*nAltivecParamsAtEnd; + } + + // The prolog code of the callee may store up to 8 GPR argument registers to + // the stack, allowing va_start to index over them in memory if its varargs. + // Because we cannot tell if this is needed on the caller side, we have to + // conservatively assume that it is needed. As such, make sure we have at + // least enough stack space for the caller to store the 8 GPRs. + NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize); + + // Tail call needs the stack to be aligned. + if (getTargetMachine().Options.GuaranteedTailCallOpt && + CallConv == CallingConv::Fast) + NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes); // Calculate by how many bytes the stack has to be adjusted in case of tail // call optimization. @@ -4234,7 +4491,7 @@ PPCTargetLowering::LowerCall_Darwin(SDVa // memory. Also, if this is a vararg function, floating point operations // must be stored to our stack, and loaded into integer regs as well, if // any integer regs are available for argument passing. - unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); + unsigned ArgOffset = LinkageSize; unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; static const uint16_t GPR_32[] = { // 32-bit registers. @@ -5271,10 +5528,14 @@ SDValue PPCTargetLowering::LowerBUILD_VE // we convert to a pseudo that will be expanded later into one of // the above forms. SDValue Elt = DAG.getConstant(SextVal, MVT::i32); - EVT VT = Op.getValueType(); - int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4); - SDValue EltSize = DAG.getConstant(Size, MVT::i32); - return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); + EVT VT = (SplatSize == 1 ? MVT::v16i8 : + (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); + SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32); + SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); + if (VT == Op.getValueType()) + return RetVal; + else + return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal); } // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is @@ -5293,6 +5554,22 @@ SDValue PPCTargetLowering::LowerBUILD_VE return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } + // The remaining cases assume either big endian element order or + // a splat-size that equates to the element size of the vector + // to be built. An example that doesn't work for little endian is + // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits + // and a vector element size of 16 bits. The code below will + // produce the vector in big endian element order, which for little + // endian is {-1, 0, -1, 0, -1, 0, -1, 0}. + + // For now, just avoid these optimizations in that case. + // FIXME: Develop correct optimizations for LE with mismatched + // splat and element sizes. + + if (PPCSubTarget.isLittleEndian() && + SplatSize != Op.getValueType().getVectorElementType().getSizeInBits()) + return SDValue(); + // Check to see if this is a wide variety of vsplti*, binop self cases. static const signed char SplatCsts[] = { -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, @@ -5461,6 +5738,7 @@ SDValue PPCTargetLowering::LowerVECTOR_S SDValue V2 = Op.getOperand(1); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); EVT VT = Op.getValueType(); + bool isLittleEndian = PPCSubTarget.isLittleEndian(); // Cases that are handled by instructions that take permute immediates // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be @@ -5469,15 +5747,15 @@ SDValue PPCTargetLowering::LowerVECTOR_S if (PPC::isSplatShuffleMask(SVOp, 1) || PPC::isSplatShuffleMask(SVOp, 2) || PPC::isSplatShuffleMask(SVOp, 4) || - PPC::isVPKUWUMShuffleMask(SVOp, true) || - PPC::isVPKUHUMShuffleMask(SVOp, true) || - PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || - PPC::isVMRGLShuffleMask(SVOp, 1, true) || - PPC::isVMRGLShuffleMask(SVOp, 2, true) || - PPC::isVMRGLShuffleMask(SVOp, 4, true) || - PPC::isVMRGHShuffleMask(SVOp, 1, true) || - PPC::isVMRGHShuffleMask(SVOp, 2, true) || - PPC::isVMRGHShuffleMask(SVOp, 4, true)) { + PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) || + PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) || + PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 || + PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) || + PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) || + PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) || + PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) || + PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) || + PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) { return Op; } } @@ -5485,15 +5763,16 @@ SDValue PPCTargetLowering::LowerVECTOR_S // Altivec has a variety of "shuffle immediates" that take two vector inputs // and produce a fixed permutation. If any of these match, do not lower to // VPERM. - if (PPC::isVPKUWUMShuffleMask(SVOp, false) || - PPC::isVPKUHUMShuffleMask(SVOp, false) || - PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || - PPC::isVMRGLShuffleMask(SVOp, 1, false) || - PPC::isVMRGLShuffleMask(SVOp, 2, false) || - PPC::isVMRGLShuffleMask(SVOp, 4, false) || - PPC::isVMRGHShuffleMask(SVOp, 1, false) || - PPC::isVMRGHShuffleMask(SVOp, 2, false) || - PPC::isVMRGHShuffleMask(SVOp, 4, false)) + unsigned int ShuffleKind = isLittleEndian ? 2 : 0; + if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) || + PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) || + PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 || + PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) || + PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) || + PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) || + PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) || + PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) || + PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG)) return Op; // Check to see if this is a shuffle of 4-byte values. If so, we can use our @@ -5527,7 +5806,9 @@ SDValue PPCTargetLowering::LowerVECTOR_S // If this shuffle can be expressed as a shuffle of 4-byte elements, use the // perfect shuffle vector to determine if it is cost effective to do this as // discrete instructions, or whether we should use a vperm. - if (isFourElementShuffle) { + // For now, we skip this for little endian until such time as we have a + // little-endian perfect shuffle table. + if (isFourElementShuffle && !isLittleEndian) { // Compute the index in the perfect shuffle table. unsigned PFTableIndex = PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; @@ -5556,6 +5837,11 @@ SDValue PPCTargetLowering::LowerVECTOR_S // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except // that it is in input element units, not in bytes. Convert now. + + // For little endian, the order of the input vectors is reversed, and + // the permutation mask is complemented with respect to 31. This is + // necessary to produce proper semantics with the big-endian-biased vperm + // instruction. EVT EltVT = V1.getValueType().getVectorElementType(); unsigned BytesPerElement = EltVT.getSizeInBits()/8; @@ -5564,13 +5850,22 @@ SDValue PPCTargetLowering::LowerVECTOR_S unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; for (unsigned j = 0; j != BytesPerElement; ++j) - ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, - MVT::i32)); + if (isLittleEndian) + ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j), + MVT::i32)); + else + ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, + MVT::i32)); } SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, &ResultMask[0], ResultMask.size()); - return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); + if (isLittleEndian) + return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), + V2, V1, VPermMask); + else + return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), + V1, V2, VPermMask); } /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an @@ -5739,6 +6034,7 @@ SDValue PPCTargetLowering::LowerMUL(SDVa LHS, RHS, Zero, DAG, dl); } else if (Op.getValueType() == MVT::v16i8) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); + bool isLittleEndian = PPCSubTarget.isLittleEndian(); // Multiply the even 8-bit parts, producing 16-bit sums. SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, @@ -5750,13 +6046,24 @@ SDValue PPCTargetLowering::LowerMUL(SDVa LHS, RHS, DAG, dl, MVT::v8i16); OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); - // Merge the results together. + // Merge the results together. Because vmuleub and vmuloub are + // instructions with a big-endian bias, we must reverse the + // element numbering and reverse the meaning of "odd" and "even" + // when generating little endian code. int Ops[16]; for (unsigned i = 0; i != 8; ++i) { - Ops[i*2 ] = 2*i+1; - Ops[i*2+1] = 2*i+1+16; + if (isLittleEndian) { + Ops[i*2 ] = 2*i; + Ops[i*2+1] = 2*i+16; + } else { + Ops[i*2 ] = 2*i+1; + Ops[i*2+1] = 2*i+1+16; + } } - return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); + if (isLittleEndian) + return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops); + else + return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); } else { llvm_unreachable("Unknown mul to lower!"); } @@ -6458,13 +6765,13 @@ PPCTargetLowering::EmitInstrWithCustomIn BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) - BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); + BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND); else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) - BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); + BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND); else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) - BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); + BB = EmitAtomicBinary(MI, BB, false, PPC::NAND); else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) - BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); + BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8); else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); @@ -7188,6 +7495,7 @@ SDValue PPCTargetLowering::PerformDAGCom // This is a type-legal unaligned Altivec load. SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); + bool isLittleEndian = PPCSubTarget.isLittleEndian(); // This implements the loading of unaligned vectors as described in // the venerable Apple Velocity Engine overview. Specifically: @@ -7195,25 +7503,28 @@ SDValue PPCTargetLowering::PerformDAGCom // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html // // The general idea is to expand a sequence of one or more unaligned - // loads into a alignment-based permutation-control instruction (lvsl), - // a series of regular vector loads (which always truncate their - // input address to an aligned address), and a series of permutations. - // The results of these permutations are the requested loaded values. - // The trick is that the last "extra" load is not taken from the address - // you might suspect (sizeof(vector) bytes after the last requested - // load), but rather sizeof(vector) - 1 bytes after the last - // requested vector. The point of this is to avoid a page fault if the - // base address happend to be aligned. This works because if the base - // address is aligned, then adding less than a full vector length will - // cause the last vector in the sequence to be (re)loaded. Otherwise, - // the next vector will be fetched as you might suspect was necessary. + // loads into an alignment-based permutation-control instruction (lvsl + // or lvsr), a series of regular vector loads (which always truncate + // their input address to an aligned address), and a series of + // permutations. The results of these permutations are the requested + // loaded values. The trick is that the last "extra" load is not taken + // from the address you might suspect (sizeof(vector) bytes after the + // last requested load), but rather sizeof(vector) - 1 bytes after the + // last requested vector. The point of this is to avoid a page fault if + // the base address happened to be aligned. This works because if the + // base address is aligned, then adding less than a full vector length + // will cause the last vector in the sequence to be (re)loaded. + // Otherwise, the next vector will be fetched as you might suspect was + // necessary. // We might be able to reuse the permutation generation from // a different base address offset from this one by an aligned amount. // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this // optimization later. - SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr, - DAG, dl, MVT::v16i8); + Intrinsic::ID Intr = (isLittleEndian ? + Intrinsic::ppc_altivec_lvsr : + Intrinsic::ppc_altivec_lvsl); + SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8); // Refine the alignment of the original load (a "new" load created here // which was identical to the first except for the alignment would be @@ -7262,8 +7573,18 @@ SDValue PPCTargetLowering::PerformDAGCom if (ExtraLoad.getValueType() != MVT::v4i32) ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad); - SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm, - BaseLoad, ExtraLoad, PermCntl, DAG, dl); + // Because vperm has a big-endian bias, we must reverse the order + // of the input vectors and complement the permute control vector + // when generating little endian code. We have already handled the + // latter by using lvsr instead of lvsl, so just reverse BaseLoad + // and ExtraLoad here. + SDValue Perm; + if (isLittleEndian) + Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm, + ExtraLoad, BaseLoad, PermCntl, DAG, dl); + else + Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm, + BaseLoad, ExtraLoad, PermCntl, DAG, dl); if (VT != MVT::v4i32) Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm); @@ -7303,9 +7624,12 @@ SDValue PPCTargetLowering::PerformDAGCom } } break; - case ISD::INTRINSIC_WO_CHAIN: - if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == - Intrinsic::ppc_altivec_lvsl && + case ISD::INTRINSIC_WO_CHAIN: { + bool isLittleEndian = PPCSubTarget.isLittleEndian(); + Intrinsic::ID Intr = (isLittleEndian ? + Intrinsic::ppc_altivec_lvsr : + Intrinsic::ppc_altivec_lvsl); + if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr && N->getOperand(1)->getOpcode() == ISD::ADD) { SDValue Add = N->getOperand(1); @@ -7317,8 +7641,8 @@ SDValue PPCTargetLowering::PerformDAGCom UE = BasePtr->use_end(); UI != UE; ++UI) { if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN && cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == - Intrinsic::ppc_altivec_lvsl) { - // We've found another LVSL, and this address if an aligned + Intr) { + // We've found another LVSL/LVSR, and this address is an aligned // multiple of that one. The results will be the same, so use the // one we've just found instead. @@ -7327,6 +7651,7 @@ SDValue PPCTargetLowering::PerformDAGCom } } } + } break; case ISD::BSWAP: Index: llvm-suse/lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCISelLowering.h +++ llvm-suse/lib/Target/PowerPC/PPCISelLowering.h @@ -71,19 +71,14 @@ namespace llvm { TOC_ENTRY, - /// The following three target-specific nodes are used for calls through + /// The following two target-specific nodes are used for calls through /// function pointers in the 64-bit SVR4 ABI. - /// Restore the TOC from the TOC save area of the current stack frame. - /// This is basically a hard coded load instruction which additionally - /// takes/produces a flag. - TOC_RESTORE, - /// Like a regular LOAD but additionally taking/producing a flag. LOAD, - /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is - /// a hard coded load instruction. + /// Like LOAD (taking/producing a flag), but using r2 as hard-coded + /// destination. LOAD_TOC, /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) @@ -293,25 +288,28 @@ namespace llvm { namespace PPC { /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUHUM instruction. - bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); + bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, + SelectionDAG &DAG); /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUWUM instruction. - bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); + bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, + SelectionDAG &DAG); /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, - bool isUnary); + unsigned ShuffleKind, SelectionDAG &DAG); /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, - bool isUnary); + unsigned ShuffleKind, SelectionDAG &DAG); - /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift - /// amount, otherwise return -1. - int isVSLDOIShuffleMask(SDNode *N, bool isUnary); + /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the + /// shift amount, otherwise return -1. + int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, + SelectionDAG &DAG); /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element that is suitable for input to @@ -324,7 +322,7 @@ namespace llvm { /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. - unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); + unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); /// get_VSPLTI_elt - If this is a build_vector of constants which can be /// formed by using a vspltis[bhw] instruction of the specified element @@ -470,6 +468,20 @@ namespace llvm { virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const; + /// \brief Returns true if an argument of type Ty needs to be passed in a + /// contiguous block of registers in calling convention CallConv. + virtual bool functionArgumentNeedsConsecutiveRegisters( + Type *Ty, CallingConv::ID CallConv, bool isVarArg) const { + // We support any array type as "consecutive" block in the parameter + // save area. The element type defines the alignment requirement and + // whether the argument should go in GPRs, FPRs, or VRs if available. + // + // Note that clang uses this capability both to implement the ELFv2 + // homogeneous float/vector aggregate ABI, and to avoid having to use + // "byval" when passing aggregates that might fully fit in registers. + return Ty->isArrayTy(); + } + private: SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; @@ -566,11 +578,6 @@ namespace llvm { extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, SDLoc dl) const; - void - setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, - unsigned nAltivecParamsAtEnd, - unsigned MinReservedArea, bool isPPC64) const; - SDValue LowerFormalArguments_Darwin(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, Index: llvm-suse/lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCInstr64Bit.td +++ llvm-suse/lib/Target/PowerPC/PPCInstr64Bit.td @@ -751,17 +751,11 @@ def LDtocCPT: Pseudo<(outs g8rc:$rD), (i [(set i64:$rD, (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; -let hasSideEffects = 1, isCodeGenOnly = 1 in { -let RST = 2, DS = 2 in -def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), - "ld 2, 8($reg)", LdStLD, - [(PPCload_toc i64:$reg)]>, isPPC64; - -let RST = 2, DS = 10, RA = 1 in -def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), - "ld 2, 40(1)", LdStLD, - [(PPCtoc_restore)]>, isPPC64; -} +let hasSideEffects = 1, isCodeGenOnly = 1, RST = 2 in +def LDinto_toc: DSForm_1<58, 0, (outs), (ins memrix:$src), + "ld 2, $src", LdStLD, + [(PPCload_toc ixaddr:$src)]>, isPPC64; + def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), "ldx $rD, $src", LdStLD, [(set i64:$rD, (load xaddr:$src))]>, isPPC64; Index: llvm-suse/lib/Target/PowerPC/PPCInstrAltivec.td =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCInstrAltivec.td +++ llvm-suse/lib/Target/PowerPC/PPCInstrAltivec.td @@ -22,111 +22,160 @@ def vnot_ppc : PatFrag<(ops node:$in), def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); + return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); }]>; def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); + return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); }]>; def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); + return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); }]>; def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); + return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); }]>; +// These fragments are provided for little-endian, where the inputs must be +// swapped for correct semantics. +def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); +}]>; +def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); +}]>; def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); }]>; def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); }]>; def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); }]>; def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); }]>; def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); }]>; def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); }]>; def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ - return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); }]>; def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); }]>; def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); }]>; def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); }]>; def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); }]>; def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); +}]>; + + +// These fragments are provided for little-endian, where the inputs must be +// swapped for correct semantics. +def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); +}]>; +def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); +}]>; +def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); +}]>; +def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); +}]>; +def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); +}]>; +def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); }]>; def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ - return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); + return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG)); }]>; def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVSLDOIShuffleMask(N, false) != -1; + return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; }], VSLDOI_get_imm>; /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into /// vector_shuffle(X,undef,mask) by the dag combiner. def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ - return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); + return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG)); }]>; def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ - return PPC::isVSLDOIShuffleMask(N, true) != -1; + return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; }], VSLDOI_unary_get_imm>; +/// VSLDOI_swapped* - These fragments are provided for little-endian, where +/// the inputs must be swapped for correct semantics. +def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ + return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG)); +}]>; +def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; +}], VSLDOI_get_imm>; + + // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ - return getI32Imm(PPC::getVSPLTImmediate(N, 1)); + return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG)); }]>; def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); }], VSPLTB_get_imm>; def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ - return getI32Imm(PPC::getVSPLTImmediate(N, 2)); + return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG)); }]>; def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); }], VSPLTH_get_imm>; def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ - return getI32Imm(PPC::getVSPLTImmediate(N, 4)); + return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG)); }]>; def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), (vector_shuffle node:$lhs, node:$rhs), [{ @@ -761,6 +810,16 @@ def:Pat<(vpkuwum_unary_shuffle v16i8:$vA def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), (VPKUHUM $vA, $vA)>; +// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. +// These fragments are matched for little-endian, where the inputs must +// be swapped for correct semantics. +def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), + (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; +def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VPKUWUM $vB, $vA)>; +def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VPKUHUM $vB, $vA)>; + // Match vmrg*(x,x) def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), (VMRGLB $vA, $vA)>; @@ -775,6 +834,22 @@ def:Pat<(vmrghh_unary_shuffle v16i8:$vA, def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), (VMRGHW $vA, $vA)>; +// Match vmrg*(y,x), i.e., swapped operands. These fragments +// are matched for little-endian, where the inputs must be +// swapped for correct semantics. +def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VMRGLB $vB, $vA)>; +def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VMRGLH $vB, $vA)>; +def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VMRGLW $vB, $vA)>; +def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VMRGHB $vB, $vA)>; +def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VMRGHH $vB, $vA)>; +def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), + (VMRGHW $vB, $vA)>; + // Logical Operations def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; Index: llvm-suse/lib/Target/PowerPC/PPCInstrFormats.td =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCInstrFormats.td +++ llvm-suse/lib/Target/PowerPC/PPCInstrFormats.td @@ -334,20 +334,6 @@ class DSForm_1<bits<6> opcode, bits<2> x let Inst{30-31} = xo; } -class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin, list<dag> pattern> - : I<opcode, OOL, IOL, asmstr, itin> { - bits<5> RST; - bits<14> DS; - bits<5> RA; - - let Pattern = pattern; - - let Inst{6-10} = RST; - let Inst{11-15} = RA; - let Inst{16-29} = DS; - let Inst{30-31} = xo; -} // 1.7.6 X-Form class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, Index: llvm-suse/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-suse/lib/Target/PowerPC/PPCInstrInfo.td @@ -139,9 +139,6 @@ def PPCload : SDNode<"PPCISD::LOAD", S def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, [SDNPHasChain, SDNPSideEffect, SDNPInGlue, SDNPOutGlue]>; -def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, - [SDNPHasChain, SDNPSideEffect, - SDNPInGlue, SDNPOutGlue]>; def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, Index: llvm-suse/lib/Target/PowerPC/PPCJITInfo.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCJITInfo.cpp +++ llvm-suse/lib/Target/PowerPC/PPCJITInfo.cpp @@ -214,6 +214,10 @@ asm( ".text\n" ".align 2\n" ".globl PPC64CompilationCallback\n" +#if _CALL_ELF == 2 + ".type PPC64CompilationCallback,@function\n" +"PPC64CompilationCallback:\n" +#else ".section \".opd\",\"aw\",@progbits\n" ".align 3\n" "PPC64CompilationCallback:\n" @@ -223,6 +227,7 @@ asm( ".align 4\n" ".type PPC64CompilationCallback,@function\n" ".L.PPC64CompilationCallback:\n" +#endif # else asm( ".text\n" Index: llvm-suse/lib/Target/PowerPC/PPCRegisterInfo.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ llvm-suse/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -737,16 +737,6 @@ bool PPCRegisterInfo:: needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { assert(Offset < 0 && "Local offset must be negative"); - unsigned FIOperandNum = 0; - while (!MI->getOperand(FIOperandNum).isFI()) { - ++FIOperandNum; - assert(FIOperandNum < MI->getNumOperands() && - "Instr doesn't have FrameIndex operand!"); - } - - unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); - Offset += MI->getOperand(OffsetOperandNo).getImm(); - // It's the load/store FI references that cause issues, as it can be difficult // to materialize the offset if it won't fit in the literal field. Estimate // based on the size of the local frame and some conservative assumptions @@ -828,10 +818,28 @@ PPCRegisterInfo::resolveFrameIndex(Machi unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); Offset += MI.getOperand(OffsetOperandNo).getImm(); MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); + + MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const MCInstrDesc &MCID = MI.getDesc(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + MRI.constrainRegClass(BaseReg, + TII.getRegClass(MCID, FIOperandNum, this, MF)); } bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const { + unsigned FIOperandNum = 0; + while (!MI->getOperand(FIOperandNum).isFI()) { + ++FIOperandNum; + assert(FIOperandNum < MI->getNumOperands() && + "Instr doesn't have FrameIndex operand!"); + } + + unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); + Offset += MI->getOperand(OffsetOperandNo).getImm(); + return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); } Index: llvm-suse/lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm-suse/lib/Target/PowerPC/PPCSubtarget.cpp @@ -144,6 +144,11 @@ void PPCSubtarget::resetSubtargetFeature // Determine endianness. IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); + + // FIXME: For now, we disable VSX in little-endian mode until endian + // issues in those instructions can be addressed. + if (IsLittleEndian) + HasVSX = false; } /// hasLazyResolverStub - Return true if accesses to the specified global have Index: llvm-suse/lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCSubtarget.h +++ llvm-suse/lib/Target/PowerPC/PPCSubtarget.h @@ -50,6 +50,7 @@ namespace PPC { DIR_PWR6, DIR_PWR6X, DIR_PWR7, + DIR_PWR8, DIR_64 }; } @@ -191,6 +192,9 @@ public: bool isDarwinABI() const { return isDarwin(); } bool isSVR4ABI() const { return !isDarwin(); } + /// FIXME: Should use a command-line option. + bool isELFv2ABI() const { return isPPC64() && isSVR4ABI() && + isLittleEndian(); } /// enablePostRAScheduler - True at 'More' optimization. bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, Index: llvm-suse/lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCTargetMachine.cpp +++ llvm-suse/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -35,10 +35,13 @@ extern "C" void LLVMInitializePowerPCTar /// Return the datalayout string of a subtarget. static std::string getDataLayoutString(const PPCSubtarget &ST) { - const Triple &T = ST.getTargetTriple(); + std::string Ret; - // PPC is big endian - std::string Ret = "E"; + // Most PPC* platforms are big endian, PPC64LE is little endian. + if (ST.isLittleEndian()) + Ret = "e"; + else + Ret = "E"; // PPC64 has 64 bit pointers, PPC32 has 32 bit pointers. if (ST.isPPC64()) Index: llvm-suse/lib/Target/PowerPC/PPCTargetStreamer.h =================================================================== --- llvm-suse.orig/lib/Target/PowerPC/PPCTargetStreamer.h +++ llvm-suse/lib/Target/PowerPC/PPCTargetStreamer.h @@ -17,6 +17,8 @@ class PPCTargetStreamer : public MCTarge public: virtual ~PPCTargetStreamer(); virtual void emitTCEntry(const MCSymbol &S) = 0; + virtual void emitAbiVersion(int AbiVersion) = 0; + virtual void emitLocalEntry(MCSymbol *S, const MCExpr *LocalOffset) = 0; }; } Index: llvm-suse/lib/Transforms/InstCombine/InstCombineCalls.cpp =================================================================== --- llvm-suse.orig/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ llvm-suse/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -578,6 +578,11 @@ Instruction *InstCombiner::visitCallInst case Intrinsic::ppc_altivec_vperm: // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. + // Note that ppc_altivec_vperm has a big-endian bias, so when creating + // a vectorshuffle for little endian, we must undo the transformation + // performed on vec_perm in altivec.h. That is, we must complement + // the permutation mask with respect to 31 and reverse the order of + // V1 and V2. if (Constant *Mask = dyn_cast<Constant>(II->getArgOperand(2))) { assert(Mask->getType()->getVectorNumElements() == 16 && "Bad type for intrinsic!"); @@ -611,10 +616,14 @@ Instruction *InstCombiner::visitCallInst unsigned Idx = cast<ConstantInt>(Mask->getAggregateElement(i))->getZExtValue(); Idx &= 31; // Match the hardware behavior. + if (TD && TD->isLittleEndian()) + Idx = 31 - Idx; if (ExtractedElts[Idx] == 0) { + Value *Op0ToUse = (TD && TD->isLittleEndian()) ? Op1 : Op0; + Value *Op1ToUse = (TD && TD->isLittleEndian()) ? Op0 : Op1; ExtractedElts[Idx] = - Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1, + Builder->CreateExtractElement(Idx < 16 ? Op0ToUse : Op1ToUse, Builder->getInt32(Idx&15)); } Index: llvm-suse/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll +++ llvm-suse/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vadduhm ; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubuhm -; XFAIL: * define <4 x i32> @test() nounwind { ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722> Index: llvm-suse/test/CodeGen/PowerPC/Frames-alloca.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/Frames-alloca.ll +++ llvm-suse/test/CodeGen/PowerPC/Frames-alloca.ll @@ -12,15 +12,15 @@ ; CHECK-PPC32-NOFP: stw r31, -4(r1) ; CHECK-PPC32-NOFP: lwz r1, 0(r1) ; CHECK-PPC32-NOFP: lwz r31, -4(r1) -; CHECK-PPC32-RS: stwu r1, -80(r1) -; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1) +; CHECK-PPC32-RS: stwu r1, -48(r1) +; CHECK-PPC32-RS-NOFP: stwu r1, -48(r1) ; CHECK-PPC64: std r31, -8(r1) -; CHECK-PPC64: stdu r1, -128(r1) +; CHECK-PPC64: stdu r1, -64(r1) ; CHECK-PPC64: ld r1, 0(r1) ; CHECK-PPC64: ld r31, -8(r1) ; CHECK-PPC64-NOFP: std r31, -8(r1) -; CHECK-PPC64-NOFP: stdu r1, -128(r1) +; CHECK-PPC64-NOFP: stdu r1, -64(r1) ; CHECK-PPC64-NOFP: ld r1, 0(r1) ; CHECK-PPC64-NOFP: ld r31, -8(r1) Index: llvm-suse/test/CodeGen/PowerPC/Frames-large.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/Frames-large.ll +++ llvm-suse/test/CodeGen/PowerPC/Frames-large.ll @@ -15,9 +15,9 @@ define i32* @f1() nounwind { ; PPC32-NOFP: _f1: ; PPC32-NOFP: lis r0, -1 -; PPC32-NOFP: ori r0, r0, 32704 +; PPC32-NOFP: ori r0, r0, 32736 ; PPC32-NOFP: stwux r1, r1, r0 -; PPC32-NOFP: addi r3, r1, 68 +; PPC32-NOFP: addi r3, r1, 36 ; PPC32-NOFP: lwz r1, 0(r1) ; PPC32-NOFP: blr @@ -25,10 +25,10 @@ define i32* @f1() nounwind { ; PPC32-FP: _f1: ; PPC32-FP: lis r0, -1 ; PPC32-FP: stw r31, -4(r1) -; PPC32-FP: ori r0, r0, 32704 +; PPC32-FP: ori r0, r0, 32736 ; PPC32-FP: stwux r1, r1, r0 ; PPC32-FP: mr r31, r1 -; PPC32-FP: addi r3, r31, 64 +; PPC32-FP: addi r3, r31, 32 ; PPC32-FP: lwz r1, 0(r1) ; PPC32-FP: lwz r31, -4(r1) ; PPC32-FP: blr @@ -36,9 +36,9 @@ define i32* @f1() nounwind { ; PPC64-NOFP: _f1: ; PPC64-NOFP: lis r0, -1 -; PPC64-NOFP: ori r0, r0, 32656 +; PPC64-NOFP: ori r0, r0, 32720 ; PPC64-NOFP: stdux r1, r1, r0 -; PPC64-NOFP: addi r3, r1, 116 +; PPC64-NOFP: addi r3, r1, 52 ; PPC64-NOFP: ld r1, 0(r1) ; PPC64-NOFP: blr @@ -46,10 +46,10 @@ define i32* @f1() nounwind { ; PPC64-FP: _f1: ; PPC64-FP: lis r0, -1 ; PPC64-FP: std r31, -8(r1) -; PPC64-FP: ori r0, r0, 32640 +; PPC64-FP: ori r0, r0, 32704 ; PPC64-FP: stdux r1, r1, r0 ; PPC64-FP: mr r31, r1 -; PPC64-FP: addi r3, r31, 124 +; PPC64-FP: addi r3, r31, 60 ; PPC64-FP: ld r1, 0(r1) ; PPC64-FP: ld r31, -8(r1) ; PPC64-FP: blr Index: llvm-suse/test/CodeGen/PowerPC/Frames-small.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/Frames-small.ll +++ llvm-suse/test/CodeGen/PowerPC/Frames-small.ll @@ -1,25 +1,25 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 ; RUN: not grep "stw r31, -4(r1)" %t1 -; RUN: grep "stwu r1, -16448(r1)" %t1 -; RUN: grep "addi r1, r1, 16448" %t1 +; RUN: grep "stwu r1, -16416(r1)" %t1 +; RUN: grep "addi r1, r1, 16416" %t1 ; RUN: llc < %s -march=ppc32 | \ ; RUN: not grep "lwz r31, -4(r1)" ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t2 ; RUN: grep "stw r31, -4(r1)" %t2 -; RUN: grep "stwu r1, -16448(r1)" %t2 -; RUN: grep "addi r1, r1, 16448" %t2 +; RUN: grep "stwu r1, -16416(r1)" %t2 +; RUN: grep "addi r1, r1, 16416" %t2 ; RUN: grep "lwz r31, -4(r1)" %t2 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 ; RUN: not grep "std r31, -8(r1)" %t3 -; RUN: grep "stdu r1, -16496(r1)" %t3 -; RUN: grep "addi r1, r1, 16496" %t3 +; RUN: grep "stdu r1, -16432(r1)" %t3 +; RUN: grep "addi r1, r1, 16432" %t3 ; RUN: not grep "ld r31, -8(r1)" %t3 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t4 ; RUN: grep "std r31, -8(r1)" %t4 -; RUN: grep "stdu r1, -16512(r1)" %t4 -; RUN: grep "addi r1, r1, 16512" %t4 +; RUN: grep "stdu r1, -16448(r1)" %t4 +; RUN: grep "addi r1, r1, 16448" %t4 ; RUN: grep "ld r31, -8(r1)" %t4 define i32* @f1() { Index: llvm-suse/test/CodeGen/PowerPC/anon_aggr.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/anon_aggr.ll +++ llvm-suse/test/CodeGen/PowerPC/anon_aggr.ll @@ -62,8 +62,7 @@ unequal: } ; CHECK-LABEL: func2: -; CHECK: addi [[REG1:[0-9]+]], 1, 64 -; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]]) +; CHECK: ld [[REG2:[0-9]+]], 72(1) ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]] ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] @@ -82,8 +81,7 @@ unequal: ; DARWIN32: lwz r3, -[[OFFSET2]] ; DARWIN64: _func2: -; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64 -; DARWIN64: ld r[[REG2:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: mr ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]] @@ -108,10 +106,8 @@ unequal: } ; CHECK-LABEL: func3: -; CHECK: addi [[REG1:[0-9]+]], 1, 64 -; CHECK: addi [[REG2:[0-9]+]], 1, 48 -; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) -; CHECK: ld [[REG4:[0-9]+]], 8([[REG2]]) +; CHECK: ld [[REG3:[0-9]+]], 72(1) +; CHECK: ld [[REG4:[0-9]+]], 56(1) ; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]] ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1) ; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1) @@ -130,10 +126,8 @@ unequal: ; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN64: _func3: -; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64 -; DARWIN64: addi r[[REG2:[0-9]+]], r1, 48 -; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]]) -; DARWIN64: ld r[[REG4:[0-9]+]], 8(r[[REG2]]) +; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1) +; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1) ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]] @@ -157,12 +151,11 @@ unequal: } ; CHECK-LABEL: func4: -; CHECK: addi [[REG1:[0-9]+]], 1, 128 +; CHECK: ld [[REG3:[0-9]+]], 136(1) ; CHECK: ld [[REG2:[0-9]+]], 120(1) -; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) ; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]] -; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) ; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) +; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) @@ -178,9 +171,8 @@ unequal: ; DARWIN32: lwz r[[REG1]], -[[OFFSET2]] ; DARWIN64: _func4: -; DARWIN64: addi r[[REG1:[0-9]+]], r1, 128 ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1) -; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1) ; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]] ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]] ; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] Index: llvm-suse/test/CodeGen/PowerPC/complex-return.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/complex-return.ll +++ llvm-suse/test/CodeGen/PowerPC/complex-return.ll @@ -26,8 +26,8 @@ entry: ; CHECK-LABEL: foo: ; CHECK: lfd 3 ; CHECK: lfd 4 -; CHECK: lfd 2 ; CHECK: lfd 1 +; CHECK: lfd 2 define { float, float } @oof() nounwind { entry: Index: llvm-suse/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll +++ llvm-suse/test/CodeGen/PowerPC/fast-isel-conversion-p5.ll @@ -116,18 +116,6 @@ entry: ret void } -define void @fptoui_float_i64(float %a) nounwind ssp { -entry: -; ELF64: fptoui_float_i64 - %b.addr = alloca i64, align 4 - %conv = fptoui float %a to i64 -; ELF64: fctiduz -; ELF64: stfd -; ELF64: ld - store i64 %conv, i64* %b.addr, align 4 - ret void -} - define void @fptoui_double_i32(double %a) nounwind ssp { entry: ; ELF64: fptoui_double_i32 @@ -140,14 +128,3 @@ entry: ret void } -define void @fptoui_double_i64(double %a) nounwind ssp { -entry: -; ELF64: fptoui_double_i64 - %b.addr = alloca i64, align 8 - %conv = fptoui double %a to i64 -; ELF64: fctiduz -; ELF64: stfd -; ELF64: ld - store i64 %conv, i64* %b.addr, align 8 - ret void -} Index: llvm-suse/test/CodeGen/PowerPC/fast-isel-conversion.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ llvm-suse/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -1,15 +1,24 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 | FileCheck %s --check-prefix=PPC970 + +;; Tests for 970 don't use -fast-isel-abort because we intentionally punt +;; to SelectionDAG in some cases. ; Test sitofp define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp { entry: ; ELF64: sitofp_single_i64 +; PPC970: sitofp_single_i64 %b.addr = alloca float, align 4 %conv = sitofp i64 %a to float ; ELF64: std ; ELF64: lfd ; ELF64: fcfids +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -17,11 +26,16 @@ entry: define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp { entry: ; ELF64: sitofp_single_i32 +; PPC970: sitofp_single_i32 %b.addr = alloca float, align 4 %conv = sitofp i32 %a to float ; ELF64: std ; ELF64: lfiwax ; ELF64: fcfids +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -29,12 +43,18 @@ entry: define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp { entry: ; ELF64: sitofp_single_i16 +; PPC970: sitofp_single_i16 %b.addr = alloca float, align 4 %conv = sitofp i16 %a to float ; ELF64: extsh ; ELF64: std ; ELF64: lfd ; ELF64: fcfids +; PPC970: extsh +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -42,12 +62,18 @@ entry: define void @sitofp_single_i8(i8 %a) nounwind ssp { entry: ; ELF64: sitofp_single_i8 +; PPC970: sitofp_single_i8 %b.addr = alloca float, align 4 %conv = sitofp i8 %a to float ; ELF64: extsb ; ELF64: std ; ELF64: lfd ; ELF64: fcfids +; PPC970: extsb +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -55,11 +81,15 @@ entry: define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i32 +; PPC970: sitofp_double_i32 %b.addr = alloca double, align 8 %conv = sitofp i32 %a to double ; ELF64: std ; ELF64: lfiwax ; ELF64: fcfid +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -67,11 +97,15 @@ entry: define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i64 +; PPC970: sitofp_double_i64 %b.addr = alloca double, align 8 %conv = sitofp i64 %a to double ; ELF64: std ; ELF64: lfd ; ELF64: fcfid +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -79,12 +113,17 @@ entry: define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i16 +; PPC970: sitofp_double_i16 %b.addr = alloca double, align 8 %conv = sitofp i16 %a to double ; ELF64: extsh ; ELF64: std ; ELF64: lfd ; ELF64: fcfid +; PPC970: extsh +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -92,12 +131,17 @@ entry: define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp { entry: ; ELF64: sitofp_double_i8 +; PPC970: sitofp_double_i8 %b.addr = alloca double, align 8 %conv = sitofp i8 %a to double ; ELF64: extsb ; ELF64: std ; ELF64: lfd ; ELF64: fcfid +; PPC970: extsb +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -107,11 +151,13 @@ entry: define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp { entry: ; ELF64: uitofp_single_i64 +; PPC970: uitofp_single_i64 %b.addr = alloca float, align 4 %conv = uitofp i64 %a to float ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus +; PPC970-NOT: fcfidus store float %conv, float* %b.addr, align 4 ret void } @@ -119,11 +165,14 @@ entry: define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp { entry: ; ELF64: uitofp_single_i32 +; PPC970: uitofp_single_i32 %b.addr = alloca float, align 4 %conv = uitofp i32 %a to float ; ELF64: std ; ELF64: lfiwzx ; ELF64: fcfidus +; PPC970-NOT: lfiwzx +; PPC970-NOT: fcfidus store float %conv, float* %b.addr, align 4 ret void } @@ -131,12 +180,18 @@ entry: define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp { entry: ; ELF64: uitofp_single_i16 +; PPC970: uitofp_single_i16 %b.addr = alloca float, align 4 %conv = uitofp i16 %a to float ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -144,12 +199,18 @@ entry: define void @uitofp_single_i8(i8 %a) nounwind ssp { entry: ; ELF64: uitofp_single_i8 +; PPC970: uitofp_single_i8 %b.addr = alloca float, align 4 %conv = uitofp i8 %a to float ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid +; PPC970: frsp store float %conv, float* %b.addr, align 4 ret void } @@ -157,11 +218,13 @@ entry: define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i64 +; PPC970: uitofp_double_i64 %b.addr = alloca double, align 8 %conv = uitofp i64 %a to double ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu +; PPC970-NOT: fcfidu store double %conv, double* %b.addr, align 8 ret void } @@ -169,11 +232,14 @@ entry: define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i32 +; PPC970: uitofp_double_i32 %b.addr = alloca double, align 8 %conv = uitofp i32 %a to double ; ELF64: std ; ELF64: lfiwzx ; ELF64: fcfidu +; PPC970-NOT: lfiwzx +; PPC970-NOT: fcfidu store double %conv, double* %b.addr, align 8 ret void } @@ -181,12 +247,17 @@ entry: define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i16 +; PPC970: uitofp_double_i16 %b.addr = alloca double, align 8 %conv = uitofp i16 %a to double ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -194,12 +265,17 @@ entry: define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp { entry: ; ELF64: uitofp_double_i8 +; PPC970: uitofp_double_i8 %b.addr = alloca double, align 8 %conv = uitofp i8 %a to double ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; PPC970: std +; PPC970: lfd +; PPC970: fcfid store double %conv, double* %b.addr, align 8 ret void } @@ -209,11 +285,15 @@ entry: define void @fptosi_float_i32(float %a) nounwind ssp { entry: ; ELF64: fptosi_float_i32 +; PPC970: fptosi_float_i32 %b.addr = alloca i32, align 4 %conv = fptosi float %a to i32 ; ELF64: fctiwz ; ELF64: stfd ; ELF64: lwa +; PPC970: fctiwz +; PPC970: stfd +; PPC970: lwa store i32 %conv, i32* %b.addr, align 4 ret void } @@ -221,11 +301,15 @@ entry: define void @fptosi_float_i64(float %a) nounwind ssp { entry: ; ELF64: fptosi_float_i64 +; PPC970: fptosi_float_i64 %b.addr = alloca i64, align 4 %conv = fptosi float %a to i64 ; ELF64: fctidz ; ELF64: stfd ; ELF64: ld +; PPC970: fctidz +; PPC970: stfd +; PPC970: ld store i64 %conv, i64* %b.addr, align 4 ret void } @@ -233,11 +317,15 @@ entry: define void @fptosi_double_i32(double %a) nounwind ssp { entry: ; ELF64: fptosi_double_i32 +; PPC970: fptosi_double_i32 %b.addr = alloca i32, align 8 %conv = fptosi double %a to i32 ; ELF64: fctiwz ; ELF64: stfd ; ELF64: lwa +; PPC970: fctiwz +; PPC970: stfd +; PPC970: lwa store i32 %conv, i32* %b.addr, align 8 ret void } @@ -245,11 +333,15 @@ entry: define void @fptosi_double_i64(double %a) nounwind ssp { entry: ; ELF64: fptosi_double_i64 +; PPC970: fptosi_double_i64 %b.addr = alloca i64, align 8 %conv = fptosi double %a to i64 ; ELF64: fctidz ; ELF64: stfd ; ELF64: ld +; PPC970: fctidz +; PPC970: stfd +; PPC970: ld store i64 %conv, i64* %b.addr, align 8 ret void } @@ -259,11 +351,15 @@ entry: define void @fptoui_float_i32(float %a) nounwind ssp { entry: ; ELF64: fptoui_float_i32 +; PPC970: fptoui_float_i32 %b.addr = alloca i32, align 4 %conv = fptoui float %a to i32 ; ELF64: fctiwuz ; ELF64: stfd ; ELF64: lwz +; PPC970: fctidz +; PPC970: stfd +; PPC970: lwz store i32 %conv, i32* %b.addr, align 4 ret void } @@ -271,11 +367,13 @@ entry: define void @fptoui_float_i64(float %a) nounwind ssp { entry: ; ELF64: fptoui_float_i64 +; PPC970: fptoui_float_i64 %b.addr = alloca i64, align 4 %conv = fptoui float %a to i64 ; ELF64: fctiduz ; ELF64: stfd ; ELF64: ld +; PPC970-NOT: fctiduz store i64 %conv, i64* %b.addr, align 4 ret void } @@ -283,11 +381,15 @@ entry: define void @fptoui_double_i32(double %a) nounwind ssp { entry: ; ELF64: fptoui_double_i32 +; PPC970: fptoui_double_i32 %b.addr = alloca i32, align 8 %conv = fptoui double %a to i32 ; ELF64: fctiwuz ; ELF64: stfd ; ELF64: lwz +; PPC970: fctidz +; PPC970: stfd +; PPC970: lwz store i32 %conv, i32* %b.addr, align 8 ret void } @@ -295,11 +397,13 @@ entry: define void @fptoui_double_i64(double %a) nounwind ssp { entry: ; ELF64: fptoui_double_i64 +; PPC970: fptoui_double_i64 %b.addr = alloca i64, align 8 %conv = fptoui double %a to i64 ; ELF64: fctiduz ; ELF64: stfd ; ELF64: ld +; PPC970-NOT: fctiduz store i64 %conv, i64* %b.addr, align 8 ret void } Index: llvm-suse/test/CodeGen/PowerPC/ppc64-altivec-abi.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64-altivec-abi.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=ppc64 -mattr=+altivec | FileCheck %s + +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Verify that in the 64-bit Linux ABI, vector arguments take up space +; in the parameter save area. + +define i64 @callee(i64 %a, <4 x i32> %b, i64 %c, <4 x i32> %d, i64 %e) { +entry: + ret i64 %e +} +; CHECK-LABEL: callee: +; CHECK: ld 3, 112(1) + +define void @caller(i64 %x, <4 x i32> %y) { +entry: + tail call void @test(i64 %x, <4 x i32> %y, i64 %x, <4 x i32> %y, i64 %x) + ret void +} +; CHECK-LABEL: caller: +; CHECK: std 3, 112(1) + +declare void @test(i64, <4 x i32>, i64, <4 x i32>, i64) + Index: llvm-suse/test/CodeGen/PowerPC/ppc64-byval-align.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64-byval-align.ll @@ -0,0 +1,55 @@ +; RUN: llc -O1 < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s + +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.test = type { i64, [8 x i8] } +%struct.pad = type { [8 x i64] } + +@gt = common global %struct.test zeroinitializer, align 16 +@gp = common global %struct.pad zeroinitializer, align 8 + +define signext i32 @callee1(i32 signext %x, %struct.test* byval align 16 nocapture readnone %y, i32 signext %z) { +entry: + ret i32 %z +} +; CHECK-LABEL: @callee1 +; CHECK: mr 3, 7 +; CHECK: blr + +declare signext i32 @test1(i32 signext, %struct.test* byval align 16, i32 signext) +define void @caller1(i32 signext %z) { +entry: + %call = tail call signext i32 @test1(i32 signext 0, %struct.test* byval align 16 @gt, i32 signext %z) + ret void +} +; CHECK-LABEL: @caller1 +; CHECK: mr [[REG:[0-9]+]], 3 +; CHECK: mr 7, [[REG]] +; CHECK: bl test1 + +define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) { +entry: + %x1 = getelementptr inbounds %struct.test* %z, i64 0, i32 0 + %0 = load i64* %x1, align 16 + ret i64 %0 +} +; CHECK-LABEL: @callee2 +; CHECK: ld 3, 128(1) +; CHECK: blr + +declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16) +define void @caller2(i64 %z) { +entry: + %tmp = alloca %struct.test, align 16 + %.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test* %tmp, i64 0, i32 0 + store i64 %z, i64* %.compoundliteral.sroa.0.0..sroa_idx, align 16 + %call = call i64 @test2(%struct.pad* byval @gp, i32 signext 0, %struct.test* byval align 16 %tmp) + ret void +} +; CHECK-LABEL: @caller2 +; CHECK: std 3, [[OFF:[0-9]+]](1) +; CHECK: ld [[REG:[0-9]+]], [[OFF]](1) +; CHECK: std [[REG]], 128(1) +; CHECK: bl test2 + Index: llvm-suse/test/CodeGen/PowerPC/ppc64-calls.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/ppc64-calls.ll +++ llvm-suse/test/CodeGen/PowerPC/ppc64-calls.ll @@ -42,12 +42,18 @@ define void @test_indirect(void ()* noca ret void } -; Absolute vales should be have the TOC restore 'nop' +; Absolute values must use the regular indirect call sequence +; The main purpose of this test is to ensure that BLA is not +; used on 64-bit SVR4 (as e.g. on Darwin). define void @test_abs() nounwind { ; CHECK-LABEL: test_abs: tail call void inttoptr (i64 1024 to void ()*)() nounwind -; CHECK: bla 1024 -; CHECK-NEXT: nop +; CHECK: ld [[FP:[0-9]+]], 1024(0) +; CHECK: ld 11, 1040(0) +; CHECK: ld 2, 1032(0) +; CHECK-NEXT: mtctr [[FP]] +; CHECK-NEXT: bctrl +; CHECK-NEXT: ld 2, 40(1) ret void } Index: llvm-suse/test/CodeGen/PowerPC/ppc64-smallarg.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64-smallarg.ll @@ -0,0 +1,59 @@ +; Verify that small structures and float arguments are passed in the +; least significant part of a stack slot doubleword. + +; RUN: llc < %s | FileCheck %s + +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.large_arg = type { [8 x i64] } +%struct.small_arg = type { i16, i8 } + +@gl = common global %struct.large_arg zeroinitializer, align 8 +@gs = common global %struct.small_arg zeroinitializer, align 2 +@gf = common global float 0.000000e+00, align 4 + +define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) { +entry: + %0 = bitcast %struct.small_arg* %x to i32* + %1 = bitcast %struct.small_arg* %agg.result to i32* + %2 = load i32* %0, align 2 + store i32 %2, i32* %1, align 2 + ret void +} +; CHECK: @callee1 +; CHECK: lwz {{[0-9]+}}, 124(1) +; CHECK: blr + +define void @caller1() { +entry: + %tmp = alloca %struct.small_arg, align 2 + call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs) + ret void +} +; CHECK: @caller1 +; CHECK: stw {{[0-9]+}}, 124(1) +; CHECK: bl test1 + +declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval) + +define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) { +entry: + ret float %x +} +; CHECK: @callee2 +; CHECK: lfs {{[0-9]+}}, 156(1) +; CHECK: blr + +define void @caller2() { +entry: + %0 = load float* @gf, align 4 + %call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0) + ret void +} +; CHECK: @caller2 +; CHECK: stfs {{[0-9]+}}, 156(1) +; CHECK: bl test2 + +declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float) + Index: llvm-suse/test/CodeGen/PowerPC/ppc64le-aggregates.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -0,0 +1,329 @@ +; RUN: llc < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec | FileCheck %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; +; Verify use of registers for float/vector aggregate return. +; + +define [8 x float] @return_float([8 x float] %x) { +entry: + ret [8 x float] %x +} +; CHECK-LABEL: @return_float +; CHECK: %entry +; CHECK-NEXT: blr + +define [8 x double] @return_double([8 x double] %x) { +entry: + ret [8 x double] %x +} +; CHECK-LABEL: @return_double +; CHECK: %entry +; CHECK-NEXT: blr + +define [4 x ppc_fp128] @return_ppcf128([4 x ppc_fp128] %x) { +entry: + ret [4 x ppc_fp128] %x +} +; CHECK-LABEL: @return_ppcf128 +; CHECK: %entry +; CHECK-NEXT: blr + +define [8 x <4 x i32>] @return_v4i32([8 x <4 x i32>] %x) { +entry: + ret [8 x <4 x i32>] %x +} +; CHECK-LABEL: @return_v4i32 +; CHECK: %entry +; CHECK-NEXT: blr + + +; +; Verify amount of space taken up by aggregates in the parameter save area. +; + +define i64 @callee_float([7 x float] %a, [7 x float] %b, i64 %c) { +entry: + ret i64 %c +} +; CHECK-LABEL: @callee_float +; CHECK: ld 3, 96(1) +; CHECK: blr + +define void @caller_float(i64 %x, [7 x float] %y) { +entry: + tail call void @test_float([7 x float] %y, [7 x float] %y, i64 %x) + ret void +} +; CHECK-LABEL: @caller_float +; CHECK: std 3, 96(1) +; CHECK: bl test_float + +declare void @test_float([7 x float], [7 x float], i64) + +define i64 @callee_double(i64 %a, [7 x double] %b, i64 %c) { +entry: + ret i64 %c +} +; CHECK-LABEL: @callee_double +; CHECK: ld 3, 96(1) +; CHECK: blr + +define void @caller_double(i64 %x, [7 x double] %y) { +entry: + tail call void @test_double(i64 %x, [7 x double] %y, i64 %x) + ret void +} +; CHECK-LABEL: @caller_double +; CHECK: std 3, 96(1) +; CHECK: bl test_double + +declare void @test_double(i64, [7 x double], i64) + +define i64 @callee_ppcf128(i64 %a, [4 x ppc_fp128] %b, i64 %c) { +entry: + ret i64 %c +} +; CHECK-LABEL: @callee_ppcf128 +; CHECK: ld 3, 104(1) +; CHECK: blr + +define void @caller_ppcf128(i64 %x, [4 x ppc_fp128] %y) { +entry: + tail call void @test_ppcf128(i64 %x, [4 x ppc_fp128] %y, i64 %x) + ret void +} +; CHECK-LABEL: @caller_ppcf128 +; CHECK: std 3, 104(1) +; CHECK: bl test_ppcf128 + +declare void @test_ppcf128(i64, [4 x ppc_fp128], i64) + +define i64 @callee_i64(i64 %a, [7 x i64] %b, i64 %c) { +entry: + ret i64 %c +} +; CHECK-LABEL: @callee_i64 +; CHECK: ld 3, 96(1) +; CHECK: blr + +define void @caller_i64(i64 %x, [7 x i64] %y) { +entry: + tail call void @test_i64(i64 %x, [7 x i64] %y, i64 %x) + ret void +} +; CHECK-LABEL: @caller_i64 +; CHECK: std 3, 96(1) +; CHECK: bl test_i64 + +declare void @test_i64(i64, [7 x i64], i64) + +define i64 @callee_i128(i64 %a, [4 x i128] %b, i64 %c) { +entry: + ret i64 %c +} +; CHECK-LABEL: @callee_i128 +; CHECK: ld 3, 112(1) +; CHECK: blr + +define void @caller_i128(i64 %x, [4 x i128] %y) { +entry: + tail call void @test_i128(i64 %x, [4 x i128] %y, i64 %x) + ret void +} +; CHECK-LABEL: @caller_i128 +; CHECK: std 3, 112(1) +; CHECK: bl test_i128 + +declare void @test_i128(i64, [4 x i128], i64) + +define i64 @callee_v4i32(i64 %a, [4 x <4 x i32>] %b, i64 %c) { +entry: + ret i64 %c +} +; CHECK-LABEL: @callee_v4i32 +; CHECK: ld 3, 112(1) +; CHECK: blr + +define void @caller_v4i32(i64 %x, [4 x <4 x i32>] %y) { +entry: + tail call void @test_v4i32(i64 %x, [4 x <4 x i32>] %y, i64 %x) + ret void +} +; CHECK-LABEL: @caller_v4i32 +; CHECK: std 3, 112(1) +; CHECK: bl test_v4i32 + +declare void @test_v4i32(i64, [4 x <4 x i32>], i64) + + +; +; Verify handling of floating point arguments in GPRs +; + +%struct.float8 = type { [8 x float] } +%struct.float5 = type { [5 x float] } +%struct.float2 = type { [2 x float] } + +@g8 = common global %struct.float8 zeroinitializer, align 4 +@g5 = common global %struct.float5 zeroinitializer, align 4 +@g2 = common global %struct.float2 zeroinitializer, align 4 + +define float @callee0([7 x float] %a, [7 x float] %b) { +entry: + %b.extract = extractvalue [7 x float] %b, 6 + ret float %b.extract +} +; CHECK-LABEL: @callee0 +; CHECK: stw 10, [[OFF:.*]](1) +; CHECK: lfs 1, [[OFF]](1) +; CHECK: blr + +define void @caller0([7 x float] %a) { +entry: + tail call void @test0([7 x float] %a, [7 x float] %a) + ret void +} +; CHECK-LABEL: @caller0 +; CHECK-DAG: fmr 8, 1 +; CHECK-DAG: fmr 9, 2 +; CHECK-DAG: fmr 10, 3 +; CHECK-DAG: fmr 11, 4 +; CHECK-DAG: fmr 12, 5 +; CHECK-DAG: fmr 13, 6 +; CHECK-DAG: stfs 7, [[OFF:[0-9]+]](1) +; CHECK-DAG: lwz 10, [[OFF]](1) +; CHECK: bl test0 + +declare void @test0([7 x float], [7 x float]) + +define float @callee1([8 x float] %a, [8 x float] %b) { +entry: + %b.extract = extractvalue [8 x float] %b, 7 + ret float %b.extract +} +; CHECK-LABEL: @callee1 +; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32 +; CHECK: stw [[REG]], [[OFF:.*]](1) +; CHECK: lfs 1, [[OFF]](1) +; CHECK: blr + +define void @caller1([8 x float] %a) { +entry: + tail call void @test1([8 x float] %a, [8 x float] %a) + ret void +} +; CHECK-LABEL: @caller1 +; CHECK-DAG: fmr 9, 1 +; CHECK-DAG: fmr 10, 2 +; CHECK-DAG: fmr 11, 3 +; CHECK-DAG: fmr 12, 4 +; CHECK-DAG: fmr 13, 5 +; CHECK-DAG: stfs 5, [[OFF0:[0-9]+]](1) +; CHECK-DAG: stfs 6, [[OFF1:[0-9]+]](1) +; CHECK-DAG: stfs 7, [[OFF2:[0-9]+]](1) +; CHECK-DAG: stfs 8, [[OFF3:[0-9]+]](1) +; CHECK-DAG: lwz [[REG0:[0-9]+]], [[OFF0]](1) +; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1) +; CHECK-DAG: lwz [[REG2:[0-9]+]], [[OFF2]](1) +; CHECK-DAG: lwz [[REG3:[0-9]+]], [[OFF3]](1) +; CHECK-DAG: sldi [[REG1]], [[REG1]], 32 +; CHECK-DAG: sldi [[REG3]], [[REG3]], 32 +; CHECK-DAG: or 9, [[REG0]], [[REG1]] +; CHECK-DAG: or 10, [[REG2]], [[REG3]] +; CHECK: bl test1 + +declare void @test1([8 x float], [8 x float]) + +define float @callee2([8 x float] %a, [5 x float] %b, [2 x float] %c) { +entry: + %c.extract = extractvalue [2 x float] %c, 1 + ret float %c.extract +} +; CHECK-LABEL: @callee2 +; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32 +; CHECK: stw [[REG]], [[OFF:.*]](1) +; CHECK: lfs 1, [[OFF]](1) +; CHECK: blr + +define void @caller2() { +entry: + %0 = load [8 x float]* getelementptr inbounds (%struct.float8* @g8, i64 0, i32 0), align 4 + %1 = load [5 x float]* getelementptr inbounds (%struct.float5* @g5, i64 0, i32 0), align 4 + %2 = load [2 x float]* getelementptr inbounds (%struct.float2* @g2, i64 0, i32 0), align 4 + tail call void @test2([8 x float] %0, [5 x float] %1, [2 x float] %2) + ret void +} +; CHECK-LABEL: @caller2 +; CHECK: ld [[REGA:[0-9]+]], .LC +; CHECK-DAG: lwz [[REG1:[0-9]+]], 4([[REGA]]) +; CHECK: ld [[REGC:[0-9]+]], .LC +; CHECK: ld [[REGB:[0-9]+]], .LC +; CHECK-DAG: lwz [[REG0:[0-9]+]], 0([[REGA]]) +; CHECK-DAG: sldi [[REG1]], [[REG1]], 32 +; CHECK-DAG: lfs 1, 0([[REGB]]) +; CHECK-DAG: lfs 2, 4([[REGB]]) +; CHECK-DAG: lfs 3, 8([[REGB]]) +; CHECK-DAG: lfs 4, 12([[REGB]]) +; CHECK-DAG: lfs 5, 16([[REGB]]) +; CHECK-DAG: lfs 6, 20([[REGB]]) +; CHECK-DAG: lfs 7, 24([[REGB]]) +; CHECK-DAG: lfs 8, 28([[REGB]]) +; CHECK-DAG: lfs 9, 0([[REGC]]) +; CHECK-DAG: lfs 10, 4([[REGC]]) +; CHECK-DAG: lfs 11, 8([[REGC]]) +; CHECK-DAG: lfs 12, 12([[REGC]]) +; CHECK-DAG: lfs 13, 16([[REGC]]) +; CHECK-DAG: or 10, [[REG0]], [[REG1]] +; CHECK: bl test2 + +declare void @test2([8 x float], [5 x float], [2 x float]) + +define double @callee3([8 x float] %a, [5 x float] %b, double %c) { +entry: + ret double %c +} +; CHECK-LABEL: @callee3 +; CHECK: std 10, [[OFF:.*]](1) +; CHECK: lfd 1, [[OFF]](1) +; CHECK: blr + +define void @caller3(double %d) { +entry: + %0 = load [8 x float]* getelementptr inbounds (%struct.float8* @g8, i64 0, i32 0), align 4 + %1 = load [5 x float]* getelementptr inbounds (%struct.float5* @g5, i64 0, i32 0), align 4 + tail call void @test3([8 x float] %0, [5 x float] %1, double %d) + ret void +} +; CHECK-LABEL: @caller3 +; CHECK: stfd 1, [[OFF:.*]](1) +; CHECK: ld 10, [[OFF]](1) +; CHECK: bl test3 + +declare void @test3([8 x float], [5 x float], double) + +define float @callee4([8 x float] %a, [5 x float] %b, float %c) { +entry: + ret float %c +} +; CHECK-LABEL: @callee4 +; CHECK: stw 10, [[OFF:.*]](1) +; CHECK: lfs 1, [[OFF]](1) +; CHECK: blr + +define void @caller4(float %f) { +entry: + %0 = load [8 x float]* getelementptr inbounds (%struct.float8* @g8, i64 0, i32 0), align 4 + %1 = load [5 x float]* getelementptr inbounds (%struct.float5* @g5, i64 0, i32 0), align 4 + tail call void @test4([8 x float] %0, [5 x float] %1, float %f) + ret void +} +; CHECK-LABEL: @caller4 +; CHECK: stfs 1, [[OFF:.*]](1) +; CHECK: lwz 10, [[OFF]](1) +; CHECK: bl test4 + +declare void @test4([8 x float], [5 x float], float) + Index: llvm-suse/test/CodeGen/PowerPC/ppc64le-calls.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64le-calls.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; Indirect calls requires a full stub creation +define void @test_indirect(void ()* nocapture %fp) { +; CHECK-LABEL: @test_indirect + tail call void %fp() +; CHECK-DAG: std 2, 24(1) +; CHECK-DAG: mr 12, 3 +; CHECK-DAG: mtctr 3 +; CHECK: bctrl +; CHECK-NEXT: ld 2, 24(1) + ret void +} + Index: llvm-suse/test/CodeGen/PowerPC/ppc64le-crsave.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64le-crsave.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@_ZTIi = external constant i8* +declare i8* @__cxa_allocate_exception(i64) +declare void @__cxa_throw(i8*, i8*, i8*) + +define void @crsave() { +entry: + call void asm sideeffect "", "~{cr2}"() + call void asm sideeffect "", "~{cr3}"() + call void asm sideeffect "", "~{cr4}"() + + %exception = call i8* @__cxa_allocate_exception(i64 4) + %0 = bitcast i8* %exception to i32* + store i32 0, i32* %0 + call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) + unreachable + +return: ; No predecessors! + ret void +} +; CHECK-LABEL: @crsave +; CHECK: .cfi_offset cr2, 8 +; CHECK: .cfi_offset cr3, 8 +; CHECK: .cfi_offset cr4, 8 + Index: llvm-suse/test/CodeGen/PowerPC/ppc64le-localentry.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64le-localentry.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -march=ppc64le -mcpu=pwr8 -O0 < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@number64 = global i64 10, align 8 + +; CHECK: .abiversion 2 + +define i64 @use_toc(i64 %a) nounwind { +entry: +; CHECK-LABEL: @use_toc +; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]: +; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha +; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l +; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]: +; CHECK-NEXT: .localentry use_toc, .Ltmp[[TMP2]]-.Ltmp[[TMP1]] +; CHECK-NEXT: %entry + %0 = load i64* @number64, align 8 + %cmp = icmp eq i64 %0, %a + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +declare void @callee() +define void @use_toc_implicit() nounwind { +entry: +; CHECK-LABEL: @use_toc_implicit +; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]: +; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha +; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l +; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]: +; CHECK-NEXT: .localentry use_toc_implicit, .Ltmp[[TMP2]]-.Ltmp[[TMP1]] +; CHECK-NEXT: %entry + call void @callee() + ret void +} + +define i64 @no_toc(i64 %a) nounwind { +entry: +; CHECK-LABEL: @no_toc +; CHECK-NEXT: %entry + ret i64 %a +} + Index: llvm-suse/test/CodeGen/PowerPC/ppc64le-smallarg.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppc64le-smallarg.ll @@ -0,0 +1,59 @@ +; Verify that small structures and float arguments are passed in the +; least significant part of a stack slot doubleword. + +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +%struct.large_arg = type { [8 x i64] } +%struct.small_arg = type { i16, i8 } + +@gl = common global %struct.large_arg zeroinitializer, align 8 +@gs = common global %struct.small_arg zeroinitializer, align 2 +@gf = common global float 0.000000e+00, align 4 + +define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) { +entry: + %0 = bitcast %struct.small_arg* %x to i32* + %1 = bitcast %struct.small_arg* %agg.result to i32* + %2 = load i32* %0, align 2 + store i32 %2, i32* %1, align 2 + ret void +} +; CHECK: @callee1 +; CHECK: lwz {{[0-9]+}}, 104(1) +; CHECK: blr + +define void @caller1() { +entry: + %tmp = alloca %struct.small_arg, align 2 + call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs) + ret void +} +; CHECK: @caller1 +; CHECK: stw {{[0-9]+}}, 104(1) +; CHECK: bl test1 + +declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval) + +define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) { +entry: + ret float %x +} +; CHECK: @callee2 +; CHECK: lfs {{[0-9]+}}, 136(1) +; CHECK: blr + +define void @caller2() { +entry: + %0 = load float* @gf, align 4 + %call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0) + ret void +} +; CHECK: @caller2 +; CHECK: stfs {{[0-9]+}}, 136(1) +; CHECK: bl test2 + +declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float) + Index: llvm-suse/test/CodeGen/PowerPC/ppcf128-endian.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -0,0 +1,154 @@ +; RUN: llc -mcpu=pwr7 -mattr=+altivec < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 + +define void @callee(ppc_fp128 %x) { +entry: + %x.addr = alloca ppc_fp128, align 16 + store ppc_fp128 %x, ppc_fp128* %x.addr, align 16 + %0 = load ppc_fp128* %x.addr, align 16 + store ppc_fp128 %0, ppc_fp128* @g, align 16 + ret void +} +; CHECK: @callee +; CHECK: ld [[REG:[0-9]+]], .LC +; CHECK: stfd 2, 8([[REG]]) +; CHECK: stfd 1, 0([[REG]]) +; CHECK: blr + +define void @caller() { +entry: + %0 = load ppc_fp128* @g, align 16 + call void @test(ppc_fp128 %0) + ret void +} +; CHECK: @caller +; CHECK: ld [[REG:[0-9]+]], .LC +; CHECK: lfd 2, 8([[REG]]) +; CHECK: lfd 1, 0([[REG]]) +; CHECK: bl test + +declare void @test(ppc_fp128) + +define void @caller_const() { +entry: + call void @test(ppc_fp128 0xM3FF00000000000000000000000000000) + ret void +} +; CHECK: .LCPI[[LC:[0-9]+]]_0: +; CHECK: .long 1065353216 +; CHECK: .LCPI[[LC]]_1: +; CHECK: .long 0 +; CHECK: @caller_const +; CHECK: addi [[REG0:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_0 +; CHECK: lfs 1, 0([[REG0]]) +; CHECK: addi [[REG1:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_1 +; CHECK: lfs 2, 0([[REG1]]) +; CHECK: bl test + +define ppc_fp128 @result() { +entry: + %0 = load ppc_fp128* @g, align 16 + ret ppc_fp128 %0 +} +; CHECK: @result +; CHECK: ld [[REG:[0-9]+]], .LC +; CHECK: lfd 1, 0([[REG]]) +; CHECK: lfd 2, 8([[REG]]) +; CHECK: blr + +define void @use_result() { +entry: + %call = tail call ppc_fp128 @test_result() #3 + store ppc_fp128 %call, ppc_fp128* @g, align 16 + ret void +} +; CHECK: @use_result +; CHECK: ld [[REG:[0-9]+]], .LC +; CHECK: bl test_result +; CHECK: stfd 2, 8([[REG]]) +; CHECK: stfd 1, 0([[REG]]) +; CHECK: blr + +declare ppc_fp128 @test_result() + +define void @caller_result() { +entry: + %call = tail call ppc_fp128 @test_result() + tail call void @test(ppc_fp128 %call) + ret void +} +; CHECK: @caller_result +; CHECK: bl test_result +; CHECK-NEXT: nop +; CHECK-NEXT: bl test +; CHECK-NEXT: nop + +define i128 @convert_from(ppc_fp128 %x) { +entry: + %0 = bitcast ppc_fp128 %x to i128 + ret i128 %0 +} +; CHECK: @convert_from +; CHECK: stfd 1, [[OFF1:.*]](1) +; CHECK: stfd 2, [[OFF2:.*]](1) +; CHECK: ld 3, [[OFF1]](1) +; CHECK: ld 4, [[OFF2]](1) +; CHECK: blr + +define ppc_fp128 @convert_to(i128 %x) { +entry: + %0 = bitcast i128 %x to ppc_fp128 + ret ppc_fp128 %0 +} +; CHECK: @convert_to +; CHECK: std 3, [[OFF1:.*]](1) +; CHECK: std 4, [[OFF2:.*]](1) +; CHECK: lfd 1, [[OFF1]](1) +; CHECK: lfd 2, [[OFF2]](1) +; CHECK: blr + +define ppc_fp128 @convert_to2(i128 %x) { +entry: + %shl = shl i128 %x, 1 + %0 = bitcast i128 %shl to ppc_fp128 + ret ppc_fp128 %0 +} + +; CHECK: @convert_to +; CHECK: std 3, [[OFF1:.*]](1) +; CHECK: std 4, [[OFF2:.*]](1) +; CHECK: lfd 1, [[OFF1]](1) +; CHECK: lfd 2, [[OFF2]](1) +; CHECK: blr + +define double @convert_vector(<4 x i32> %x) { +entry: + %cast = bitcast <4 x i32> %x to ppc_fp128 + %conv = fptrunc ppc_fp128 %cast to double + ret double %conv +} +; CHECK: @convert_vector +; CHECK: addi [[REG:[0-9]+]], 1, [[OFF:.*]] +; CHECK: stvx 2, 0, [[REG]] +; CHECK: lfd 1, [[OFF]](1) +; CHECK: blr + +declare void @llvm.va_start(i8*) + +define double @vararg(i32 %a, ...) { +entry: + %va = alloca i8*, align 8 + %va1 = bitcast i8** %va to i8* + call void @llvm.va_start(i8* %va1) + %arg = va_arg i8** %va, ppc_fp128 + %conv = fptrunc ppc_fp128 %arg to double + ret double %conv +} +; CHECK: @vararg +; CHECK: lfd 1, 0({{[0-9]+}}) +; CHECK: blr + Index: llvm-suse/test/CodeGen/PowerPC/pr18663-2.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/pr18663-2.ll @@ -0,0 +1,153 @@ +; RUN: llc < %s -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu +; RUN: llc < %s -march=ppc64le -mtriple=powerpc64le-unknown-linux-gnu + +%"class.std::__1::locale::id.1580.4307.4610.8491" = type { %"struct.std::__1::once_flag.1579.4306.4609.8490", i32 } +%"struct.std::__1::once_flag.1579.4306.4609.8490" = type { i64 } +%"class.Foam::IOerror.1581.4308.4611.8505" = type { %"class.Foam::error.1535.4262.4565.8504", %"class.Foam::string.1530.4257.4560.8499", i32, i32 } +%"class.Foam::error.1535.4262.4565.8504" = type { %"class.std::exception.1523.4250.4553.8492", [36 x i8], %"class.Foam::string.1530.4257.4560.8499", %"class.Foam::string.1530.4257.4560.8499", i32, i8, i8, %"class.Foam::OStringStream.1534.4261.4564.8503"* } +%"class.std::exception.1523.4250.4553.8492" = type { i32 (...)** } +%"class.Foam::OStringStream.1534.4261.4564.8503" = type { %"class.Foam::OSstream.1533.4260.4563.8502" } +%"class.Foam::OSstream.1533.4260.4563.8502" = type { [50 x i8], %"class.Foam::fileName.1531.4258.4561.8500", %"class.std::__1::basic_ostream.1532.4259.4562.8501"* } +%"class.Foam::fileName.1531.4258.4561.8500" = type { %"class.Foam::string.1530.4257.4560.8499" } +%"class.std::__1::basic_ostream.1532.4259.4562.8501" = type { i32 (...)**, [148 x i8] } +%"class.Foam::string.1530.4257.4560.8499" = type { %"class.std::__1::basic_string.1529.4256.4559.8498" } +%"class.std::__1::basic_string.1529.4256.4559.8498" = type { %"class.std::__1::__compressed_pair.1528.4255.4558.8497" } +%"class.std::__1::__compressed_pair.1528.4255.4558.8497" = type { %"class.std::__1::__libcpp_compressed_pair_imp.1527.4254.4557.8496" } +%"class.std::__1::__libcpp_compressed_pair_imp.1527.4254.4557.8496" = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep.1526.4253.4556.8495" } +%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__rep.1526.4253.4556.8495" = type { %union.anon.1525.4252.4555.8494 } +%union.anon.1525.4252.4555.8494 = type { %"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long.1524.4251.4554.8493" } +%"struct.std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char> >::__long.1524.4251.4554.8493" = type { i64, i64, i8* } + +@.str3 = external unnamed_addr constant [16 x i8], align 1 +@_ZNSt3__15ctypeIcE2idE = external global %"class.std::__1::locale::id.1580.4307.4610.8491" +@_ZN4Foam12FatalIOErrorE = external global %"class.Foam::IOerror.1581.4308.4611.8505" +@.str204 = external unnamed_addr constant [18 x i8], align 1 +@.str205 = external unnamed_addr constant [34 x i8], align 1 + +declare void @_ZN4FoamlsERNS_7OstreamEPKc() #0 + +declare i32 @__gxx_personality_v0(...) + +declare void @_ZNKSt3__18ios_base6getlocEv() #0 + +declare void @_ZNKSt3__16locale9use_facetERNS0_2idE() #0 + +; Function Attrs: noreturn +declare void @_ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv() #1 align 2 + +declare void @_ZN4Foam6string6expandEb() #0 + +declare void @_ZN4Foam8IFstreamC1ERKNS_8fileNameENS_8IOstream12streamFormatENS4_13versionNumberE() #0 + +declare void @_ZN4Foam7IOerrorclEPKcS2_iRKNS_8IOstreamE() #0 + +declare void @_ZN4Foam7IOerror4exitEi() #0 + +; Function Attrs: inlinehint +declare void @_ZN4Foam8fileName12stripInvalidEv() #2 align 2 + +define void @_ZN4Foam3CSVINS_6VectorIdEEE4readEv() #0 align 2 { +entry: + invoke void @_ZN4Foam6string6expandEb() + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %entry + br i1 undef, label %if.then.i.i.i.i176, label %_ZN4Foam6stringC2ERKS0_.exit.i + +if.then.i.i.i.i176: ; preds = %invoke.cont + invoke void @_ZNKSt3__121__basic_string_commonILb1EE20__throw_length_errorEv() + to label %.noexc unwind label %lpad + +.noexc: ; preds = %if.then.i.i.i.i176 + unreachable + +_ZN4Foam6stringC2ERKS0_.exit.i: ; preds = %invoke.cont + invoke void @_ZN4Foam8fileName12stripInvalidEv() + to label %invoke.cont2 unwind label %lpad.i + +lpad.i: ; preds = %_ZN4Foam6stringC2ERKS0_.exit.i + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br label %ehcleanup142 + +invoke.cont2: ; preds = %_ZN4Foam6stringC2ERKS0_.exit.i + invoke void @_ZN4Foam8IFstreamC1ERKNS_8fileNameENS_8IOstream12streamFormatENS4_13versionNumberE() + to label %invoke.cont4 unwind label %lpad3 + +invoke.cont4: ; preds = %invoke.cont2 + br i1 undef, label %for.body, label %if.then + +if.then: ; preds = %invoke.cont4 + invoke void @_ZN4Foam7IOerrorclEPKcS2_iRKNS_8IOstreamE() + to label %invoke.cont8 unwind label %lpad5 + +invoke.cont8: ; preds = %if.then + invoke void @_ZN4FoamlsERNS_7OstreamEPKc() + to label %memptr.end.i unwind label %lpad5 + +memptr.end.i: ; preds = %invoke.cont8 + invoke void @_ZN4Foam7IOerror4exitEi() + to label %if.end unwind label %lpad5 + +lpad: ; preds = %if.then.i.i.i.i176, %entry + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br label %ehcleanup142 + +lpad3: ; preds = %invoke.cont2 + %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br label %ehcleanup142 + +lpad5: ; preds = %memptr.end.i, %invoke.cont8, %if.then + %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br label %ehcleanup142 + +if.end: ; preds = %memptr.end.i + br i1 undef, label %for.body, label %vector.body + +for.body: ; preds = %if.end, %invoke.cont4 + invoke void @_ZNKSt3__18ios_base6getlocEv() + to label %.noexc205 unwind label %lpad19 + +.noexc205: ; preds = %for.body + invoke void @_ZNKSt3__16locale9use_facetERNS0_2idE() + to label %invoke.cont.i.i.i unwind label %lpad.i.i.i + +invoke.cont.i.i.i: ; preds = %.noexc205 + unreachable + +lpad.i.i.i: ; preds = %.noexc205 + %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br label %ehcleanup142 + +lpad19: ; preds = %for.body + %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + br label %ehcleanup142 + +vector.body: ; preds = %vector.body, %if.end + %vec.phi = phi <8 x i32> [ %10, %vector.body ], [ undef, %if.end ] + %vec.phi1302 = phi <8 x i32> [ %11, %vector.body ], [ undef, %if.end ] + %vec.phi1303 = phi <8 x i32> [ %12, %vector.body ], [ undef, %if.end ] + %vec.phi1304 = phi <8 x i32> [ %13, %vector.body ], [ undef, %if.end ] + %6 = icmp sgt <8 x i32> undef, %vec.phi + %7 = icmp sgt <8 x i32> undef, %vec.phi1302 + %8 = icmp sgt <8 x i32> undef, %vec.phi1303 + %9 = icmp sgt <8 x i32> undef, %vec.phi1304 + %10 = select <8 x i1> %6, <8 x i32> undef, <8 x i32> %vec.phi + %11 = select <8 x i1> %7, <8 x i32> undef, <8 x i32> %vec.phi1302 + %12 = select <8 x i1> %8, <8 x i32> undef, <8 x i32> %vec.phi1303 + %13 = select <8 x i1> %9, <8 x i32> undef, <8 x i32> %vec.phi1304 + br label %vector.body + +ehcleanup142: ; preds = %lpad19, %lpad.i.i.i, %lpad5, %lpad3, %lpad, %lpad.i + resume { i8*, i32 } undef +} + +attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { noreturn "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { inlinehint "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + Index: llvm-suse/test/CodeGen/PowerPC/pr18663.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/pr18663.ll @@ -0,0 +1,298 @@ +; RUN: llc < %s -march=ppc64 -mtriple=powerpc64-unknown-linux-gnu +; RUN: llc < %s -march=ppc64le -mtriple=powerpc64le-unknown-linux-gnu + +%class.Point.1 = type { %class.Tensor.0 } +%class.Tensor.0 = type { [3 x double] } +%class.TriaObjectAccessor.57 = type { %class.TriaAccessor.56 } +%class.TriaAccessor.56 = type { i32, i32, %class.Triangulation.55* } +%class.Triangulation.55 = type { %class.Subscriptor, %"class.std::vector.46", %"class.std::vector", %"class.std::vector.3.8", [255 x %class.Boundary.50*], i32, %struct.TriaNumberCache.54 } +%class.Subscriptor = type { i32 (...)**, i32, %"class.std::type_info.2"* } +%"class.std::type_info.2" = type { i32 (...)**, i8* } +%"class.std::vector.46" = type { %"struct.std::_Vector_base.45" } +%"struct.std::_Vector_base.45" = type { %"struct.std::_Vector_base<TriangulationLevel<3> *, std::allocator<TriangulationLevel<3> *> >::_Vector_impl.44" } +%"struct.std::_Vector_base<TriangulationLevel<3> *, std::allocator<TriangulationLevel<3> *> >::_Vector_impl.44" = type { %class.TriangulationLevel.43**, %class.TriangulationLevel.43**, %class.TriangulationLevel.43** } +%class.TriangulationLevel.43 = type { %class.TriangulationLevel.0.37, %"struct.TriangulationLevel<3>::HexesData.42" } +%class.TriangulationLevel.0.37 = type { %class.TriangulationLevel.1.31, %"struct.TriangulationLevel<2>::QuadsData.36" } +%class.TriangulationLevel.1.31 = type { %class.TriangulationLevel, %"struct.TriangulationLevel<1>::LinesData.30" } +%class.TriangulationLevel = type { %"class.std::vector.3.8", %"class.std::vector.3.8", %"class.std::vector.7.12", %"class.std::vector.12.15" } +%"class.std::vector.7.12" = type { %"struct.std::_Vector_base" } +%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<std::pair<int, int>, std::allocator<std::pair<int, int> > >::_Vector_impl.10" } +%"struct.std::_Vector_base<std::pair<int, int>, std::allocator<std::pair<int, int> > >::_Vector_impl.10" = type { %"struct.std::pair.9"*, %"struct.std::pair.9"*, %"struct.std::pair.9"* } +%"struct.std::pair.9" = type opaque +%"class.std::vector.12.15" = type { %"struct.std::_Vector_base.13.14" } +%"struct.std::_Vector_base.13.14" = type { %"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int> >::_Vector_impl.13" } +%"struct.std::_Vector_base<unsigned int, std::allocator<unsigned int> >::_Vector_impl.13" = type { i32*, i32*, i32* } +%"struct.TriangulationLevel<1>::LinesData.30" = type { %"class.std::vector.17.20", %"class.std::vector.22.23", %"class.std::vector.3.8", %"class.std::vector.3.8", %"class.std::vector.27.26", %"class.std::vector.32.29" } +%"class.std::vector.17.20" = type { %"struct.std::_Vector_base.18.19" } +%"struct.std::_Vector_base.18.19" = type { %"struct.std::_Vector_base<Line, std::allocator<Line> >::_Vector_impl.18" } +%"struct.std::_Vector_base<Line, std::allocator<Line> >::_Vector_impl.18" = type { %class.Line.17*, %class.Line.17*, %class.Line.17* } +%class.Line.17 = type { [2 x i32] } +%"class.std::vector.22.23" = type { %"struct.std::_Vector_base.23.22" } +%"struct.std::_Vector_base.23.22" = type { %"struct.std::_Vector_base<int, std::allocator<int> >::_Vector_impl.21" } +%"struct.std::_Vector_base<int, std::allocator<int> >::_Vector_impl.21" = type { i32*, i32*, i32* } +%"class.std::vector.27.26" = type { %"struct.std::_Vector_base.28.25" } +%"struct.std::_Vector_base.28.25" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char> >::_Vector_impl.24" } +%"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char> >::_Vector_impl.24" = type { i8*, i8*, i8* } +%"class.std::vector.32.29" = type { %"struct.std::_Vector_base.33.28" } +%"struct.std::_Vector_base.33.28" = type { %"struct.std::_Vector_base<void *, std::allocator<void *> >::_Vector_impl.27" } +%"struct.std::_Vector_base<void *, std::allocator<void *> >::_Vector_impl.27" = type { i8**, i8**, i8** } +%"struct.TriangulationLevel<2>::QuadsData.36" = type { %"class.std::vector.37.35", %"class.std::vector.22.23", %"class.std::vector.3.8", %"class.std::vector.3.8", %"class.std::vector.27.26", %"class.std::vector.32.29" } +%"class.std::vector.37.35" = type { %"struct.std::_Vector_base.38.34" } +%"struct.std::_Vector_base.38.34" = type { %"struct.std::_Vector_base<Quad, std::allocator<Quad> >::_Vector_impl.33" } +%"struct.std::_Vector_base<Quad, std::allocator<Quad> >::_Vector_impl.33" = type { %class.Quad.32*, %class.Quad.32*, %class.Quad.32* } +%class.Quad.32 = type { [4 x i32] } +%"struct.TriangulationLevel<3>::HexesData.42" = type { %"class.std::vector.42.41", %"class.std::vector.22.23", %"class.std::vector.3.8", %"class.std::vector.3.8", %"class.std::vector.27.26", %"class.std::vector.32.29", %"class.std::vector.3.8" } +%"class.std::vector.42.41" = type { %"struct.std::_Vector_base.43.40" } +%"struct.std::_Vector_base.43.40" = type { %"struct.std::_Vector_base<Hexahedron, std::allocator<Hexahedron> >::_Vector_impl.39" } +%"struct.std::_Vector_base<Hexahedron, std::allocator<Hexahedron> >::_Vector_impl.39" = type { %class.Hexahedron.38*, %class.Hexahedron.38*, %class.Hexahedron.38* } +%class.Hexahedron.38= type { [6 x i32] } +%"class.std::vector" = type { %"struct.std::_Vector_base.48.48" } +%"struct.std::_Vector_base.48.48" = type { %"struct.std::_Vector_base<Point<3>, std::allocator<Point<3> > >::_Vector_impl.47" } +%"struct.std::_Vector_base<Point<3>, std::allocator<Point<3> > >::_Vector_impl.47" = type { %class.Point.1*, %class.Point.1*, %class.Point.1* } +%"class.std::vector.3.8" = type { %"struct.std::_Bvector_base.7" } +%"struct.std::_Bvector_base.7" = type { %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl.6" } +%"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl.6" = type { %"struct.std::_Bit_iterator.5", %"struct.std::_Bit_iterator.5", i64* } +%"struct.std::_Bit_iterator.5" = type { %"struct.std::_Bit_iterator_base.base.4", [4 x i8] } +%"struct.std::_Bit_iterator_base.base.4" = type <{ i64*, i32 }> +%class.Boundary.50 = type opaque +%struct.TriaNumberCache.54 = type { %struct.TriaNumberCache.52.52, i32, %"class.std::vector.12.15", i32, %"class.std::vector.12.15" } +%struct.TriaNumberCache.52.52 = type { %struct.TriaNumberCache.53.51, i32, %"class.std::vector.12.15", i32, %"class.std::vector.12.15" } +%struct.TriaNumberCache.53.51 = type { i32, %"class.std::vector.12.15", i32, %"class.std::vector.12.15" } + +define void @_ZNK18TriaObjectAccessorILi3ELi3EE10barycenterEv(%class.Point.1* noalias nocapture sret %agg.result, %class.TriaObjectAccessor.57* %this) #0 align 2 { +entry: + %0 = load double* null, align 8 + %1 = load double* undef, align 8 + %call18 = tail call %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 6) + %2 = load double* undef, align 8 + %call21 = tail call %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 7) + %3 = load double* undef, align 8 + %call33 = tail call %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 3) + %4 = load double* null, align 8 + %5 = load double* undef, align 8 + %call45 = tail call %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 7) + %6 = load double* undef, align 8 + %call48 = tail call %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 0) + %7 = load double* undef, align 8 + %call66 = tail call %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57* %this, i32 zeroext 6) + %8 = load double* undef, align 8 + %mul334 = fmul double undef, 2.000000e+00 + %mul579 = fmul double %2, %5 + %mul597 = fmul double undef, %mul579 + %mul679 = fmul double %2, %8 + %mul1307 = fmul double undef, %1 + %mul2092 = fmul double undef, %4 + %mul2679 = fmul double undef, undef + %mul2931 = fmul double undef, %3 + %mul3094 = fmul double undef, %3 + %mul3096 = fmul double %mul3094, %8 + %sub3097 = fsub double 0.000000e+00, %mul3096 + %add3105 = fadd double undef, %sub3097 + %add3113 = fadd double 0.000000e+00, %add3105 + %sub3121 = fsub double %add3113, undef + %sub3129 = fsub double %sub3121, undef + %add3137 = fadd double undef, %sub3129 + %add3145 = fadd double undef, %add3137 + %sub3153 = fsub double %add3145, undef + %sub3162 = fsub double %sub3153, 0.000000e+00 + %add3171 = fadd double undef, %sub3162 + %add3180 = fadd double undef, %add3171 + %add3189 = fadd double 0.000000e+00, %add3180 + %mul3197 = fmul double %4, %mul2679 + %sub3198 = fsub double %add3189, %mul3197 + %sub3207 = fsub double %sub3198, 0.000000e+00 + %mul3212 = fmul double %2, undef + %mul3214 = fmul double %mul3212, undef + %sub3215 = fsub double %sub3207, %mul3214 + %mul3222 = fmul double %5, 0.000000e+00 + %sub3223 = fsub double %sub3215, %mul3222 + %mul3228 = fmul double %2, undef + %mul3230 = fmul double %3, %mul3228 + %add3231 = fadd double %mul3230, %sub3223 + %mul3236 = fmul double undef, undef + %mul3238 = fmul double %mul3236, %8 + %add3239 = fadd double %mul3238, %add3231 + %mul3244 = fmul double %mul1307, %3 + %mul3246 = fmul double %mul3244, %7 + %sub3247 = fsub double %add3239, %mul3246 + %mul3252 = fmul double undef, undef + %mul3254 = fmul double %mul3252, %7 + %add3255 = fadd double %mul3254, %sub3247 + %sub3263 = fsub double %add3255, undef + %add3271 = fadd double 0.000000e+00, %sub3263 + %sub3279 = fsub double %add3271, undef + %sub3287 = fsub double %sub3279, undef + %mul3292 = fmul double %mul1307, %5 + %mul3294 = fmul double %mul3292, undef + %add3295 = fadd double %mul3294, %sub3287 + %add3303 = fadd double undef, %add3295 + %add3311 = fadd double 0.000000e+00, %add3303 + %mul3318 = fmul double undef, %7 + %sub3319 = fsub double %add3311, %mul3318 + %mul3326 = fmul double %4, %mul3228 + %sub3327 = fsub double %sub3319, %mul3326 + %mul3334 = fmul double undef, %8 + %sub3335 = fsub double %sub3327, %mul3334 + %add3343 = fadd double undef, %sub3335 + %mul3350 = fmul double %mul3212, %7 + %add3351 = fadd double %mul3350, %add3343 + %mul3358 = fmul double %mul2092, undef + %sub3359 = fsub double %add3351, %mul3358 + %mul3362 = fmul double undef, %1 + %mul3366 = fmul double 0.000000e+00, %8 + %add3367 = fadd double %mul3366, %sub3359 + %mul3372 = fmul double %mul3362, %5 + %sub3375 = fsub double %add3367, undef + %add3383 = fadd double undef, %sub3375 + %mul3389 = fmul double %2, 0.000000e+00 + %mul3391 = fmul double %4, %mul3389 + %sub3392 = fsub double %add3383, %mul3391 + %mul3396 = fmul double undef, 0.000000e+00 + %mul3400 = fmul double undef, %7 + %sub3401 = fsub double %sub3392, %mul3400 + %mul3407 = fmul double %mul3396, %4 + %mul3409 = fmul double %mul3407, %8 + %add3410 = fadd double %mul3409, %sub3401 + %add3419 = fadd double undef, %add3410 + %mul3423 = fmul double undef, %mul334 + %add3428 = fadd double undef, %add3419 + %add3437 = fadd double undef, %add3428 + %mul3443 = fmul double %mul3423, %3 + %mul3445 = fmul double %mul3443, %8 + %sub3446 = fsub double %add3437, %mul3445 + %mul3453 = fmul double %mul3372, undef + %add3454 = fadd double %mul3453, %sub3446 + %add3462 = fadd double 0.000000e+00, %add3454 + %mul3467 = fmul double %mul3362, %3 + %mul3469 = fmul double %mul3467, %8 + %sub3470 = fsub double %add3462, %mul3469 + %add3478 = fadd double 0.000000e+00, %sub3470 + %sub3486 = fsub double %add3478, undef + %mul3490 = fmul double %mul334, 0.000000e+00 + %mul3492 = fmul double %2, %mul3490 + %mul3494 = fmul double %mul3492, undef + %sub3495 = fsub double %sub3486, %mul3494 + %sub3503 = fsub double %sub3495, undef + %sub3512 = fsub double %sub3503, undef + %add3520 = fadd double undef, %sub3512 + %sub3528 = fsub double %add3520, undef + %add3537 = fadd double undef, %sub3528 + %add3545 = fadd double 0.000000e+00, %add3537 + %sub3553 = fsub double %add3545, undef + %add3561 = fadd double undef, %sub3553 + %sub3569 = fsub double %add3561, undef + %mul3574 = fmul double undef, undef + %mul3576 = fmul double %mul3574, %7 + %add3577 = fadd double %mul3576, %sub3569 + %sub3585 = fsub double %add3577, undef + %mul3592 = fmul double %4, undef + %sub3593 = fsub double %sub3585, %mul3592 + %mul3598 = fmul double %2, undef + %mul3600 = fmul double %mul3598, %7 + %add3601 = fadd double %mul3600, %sub3593 + %mul3608 = fmul double %mul3598, undef + %sub3609 = fsub double %add3601, %mul3608 + %sub3618 = fsub double %sub3609, undef + %add3627 = fadd double undef, %sub3618 + %add3635 = fadd double undef, %add3627 + %mul3638 = fmul double undef, %2 + %mul3640 = fmul double %mul3638, %5 + %mul3642 = fmul double %mul3640, %7 + %sub3643 = fsub double %add3635, %mul3642 + %mul3648 = fmul double %1, undef + %mul3650 = fmul double %mul3648, %8 + %sub3651 = fsub double %sub3643, %mul3650 + %mul3656 = fmul double %mul3638, %4 + %mul3658 = fmul double %mul3656, %8 + %add3659 = fadd double %mul3658, %sub3651 + %mul3666 = fmul double %5, 0.000000e+00 + %add3667 = fadd double %mul3666, %add3659 + %sub3675 = fsub double %add3667, undef + %mul3680 = fmul double %mul3638, %3 + %mul3682 = fmul double %mul3680, %8 + %sub3683 = fsub double %sub3675, %mul3682 + %add3692 = fadd double 0.000000e+00, %sub3683 + %mul3696 = fmul double undef, undef + %mul3698 = fmul double %mul3696, %4 + %mul3700 = fmul double %mul3698, %8 + %add3701 = fadd double %mul3700, %add3692 + %sub3710 = fsub double %add3701, undef + %mul3716 = fmul double undef, %3 + %mul3718 = fmul double %mul3716, %8 + %sub3719 = fsub double %sub3710, %mul3718 + %add3727 = fadd double undef, %sub3719 + %mul3734 = fmul double %mul3574, %8 + %add3735 = fadd double %mul3734, %add3727 + %sub3743 = fsub double %add3735, 0.000000e+00 + %add3751 = fadd double 0.000000e+00, %sub3743 + %mul3758 = fmul double %6, 0.000000e+00 + %sub3759 = fsub double %add3751, %mul3758 + %mul3764 = fmul double undef, %mul2931 + %mul3766 = fmul double %mul3764, undef + %sub3767 = fsub double %sub3759, %mul3766 + %add3775 = fadd double 0.000000e+00, %sub3767 + %add3783 = fadd double undef, %add3775 + %sub3791 = fsub double %add3783, 0.000000e+00 + %add3799 = fadd double undef, %sub3791 + %sub3807 = fsub double %add3799, undef + %mul3814 = fmul double 0.000000e+00, undef + %add3815 = fadd double %mul3814, %sub3807 + %mul3822 = fmul double %mul597, undef + %sub3823 = fsub double %add3815, %mul3822 + %add3831 = fadd double undef, %sub3823 + %mul3836 = fmul double undef, %mul679 + %mul3838 = fmul double %6, %mul3836 + %sub3839 = fsub double %add3831, %mul3838 + %add3847 = fadd double undef, %sub3839 + %add3855 = fadd double undef, %add3847 + %mul3858 = fmul double undef, %8 + %mul3860 = fmul double undef, %mul3858 + %mul3862 = fmul double %6, %mul3860 + %sub3863 = fsub double %add3855, %mul3862 + %add3872 = fadd double undef, %sub3863 + %sub3880 = fsub double %add3872, undef + %sub3889 = fsub double %sub3880, undef + %sub3898 = fsub double %sub3889, undef + %add3907 = fadd double undef, %sub3898 + %sub3915 = fsub double %add3907, 0.000000e+00 + %add3923 = fadd double undef, %sub3915 + %mul3930 = fmul double %3, undef + %add3931 = fadd double %mul3930, %add3923 + %add3940 = fadd double undef, %add3931 + %sub3949 = fsub double %add3940, undef + %mul3952 = fmul double %2, %3 + %sub3957 = fsub double %sub3949, undef + %sub3966 = fsub double %sub3957, undef + %add3975 = fadd double undef, %sub3966 + %add3983 = fadd double undef, %add3975 + %sub3992 = fsub double %add3983, undef + %mul3997 = fmul double undef, %mul3952 + %mul3999 = fmul double %mul3997, %8 + %add4000 = fadd double %mul3999, %sub3992 + %sub4008 = fsub double %add4000, undef + %add4017 = fadd double undef, %sub4008 + %add4026 = fadd double 0.000000e+00, %add4017 + %mul4034 = fmul double %6, undef + %sub4035 = fsub double %add4026, %mul4034 + %add4043 = fadd double undef, %sub4035 + %sub4051 = fsub double %add4043, 0.000000e+00 + %mul4916 = fmul double 0.000000e+00, %sub4051 + %mul4917 = fmul double %mul4916, 0x3FC5555555555555 + %mul7317 = fmul double 0.000000e+00, %3 + %mul7670 = fmul double %0, %mul7317 + %mul8882 = fmul double %0, 0.000000e+00 + %mul8884 = fmul double undef, %mul8882 + %sub8885 = fsub double 0.000000e+00, %mul8884 + %mul8892 = fmul double %mul7670, undef + %add8893 = fadd double %mul8892, %sub8885 + %mul8900 = fmul double undef, undef + %add8901 = fadd double %mul8900, %add8893 + %mul9767 = fmul double 0.000000e+00, %add8901 + %mul9768 = fmul double %mul9767, 0x3FC5555555555555 + store double %mul4917, double* undef, align 8 + store double %mul9768, double* undef, align 8 + ret void +} + +declare %class.Point.1* @_ZNK18TriaObjectAccessorILi3ELi3EE6vertexEj(%class.TriaObjectAccessor.57*, i32 zeroext) #0 + Index: llvm-suse/test/CodeGen/PowerPC/resolvefi-basereg.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/resolvefi-basereg.ll @@ -0,0 +1,362 @@ +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s + +; Due to a bug in resolveFrameIndex we ended up with invalid addresses +; containing a base register 0. Verify that this no longer happens. +; CHECK-NOT: (0) + +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.Info = type { i32, i32, i8*, i8*, i8*, [32 x i8*], i64, [32 x i64], i64, i64, i64, [32 x i64] } +%struct.S1998 = type { [2 x i32*], i64, i64, double, i16, i32, [29 x %struct.anon], i16, i8, i32, [8 x i8] } +%struct.anon = type { [16 x double], i32, i16, i32, [3 x i8], [6 x i8], [4 x i32], i8 } + +@info = global %struct.Info zeroinitializer, align 8 +@fails = global i32 0, align 4 +@intarray = global [256 x i32] zeroinitializer, align 4 +@s1998 = global %struct.S1998 zeroinitializer, align 16 +@a1998 = external global [5 x %struct.S1998] + +define void @test1998() { +entry: + %i = alloca i32, align 4 + %j = alloca i32, align 4 + %tmp = alloca i32, align 4 + %agg.tmp = alloca %struct.S1998, align 16 + %agg.tmp111 = alloca %struct.S1998, align 16 + %agg.tmp112 = alloca %struct.S1998, align 16 + %agg.tmp113 = alloca %struct.S1998, align 16 + %agg.tmp114 = alloca %struct.S1998, align 16 + %agg.tmp115 = alloca %struct.S1998, align 16 + %agg.tmp116 = alloca %struct.S1998, align 16 + %agg.tmp117 = alloca %struct.S1998, align 16 + %agg.tmp118 = alloca %struct.S1998, align 16 + %agg.tmp119 = alloca %struct.S1998, align 16 + call void @llvm.memset.p0i8.i64(i8* bitcast (%struct.S1998* @s1998 to i8*), i8 0, i64 5168, i32 16, i1 false) + call void @llvm.memset.p0i8.i64(i8* bitcast ([5 x %struct.S1998]* @a1998 to i8*), i8 0, i64 25840, i32 16, i1 false) + call void @llvm.memset.p0i8.i64(i8* bitcast (%struct.Info* @info to i8*), i8 0, i64 832, i32 8, i1 false) + store i8* bitcast (%struct.S1998* @s1998 to i8*), i8** getelementptr inbounds (%struct.Info* @info, i32 0, i32 2), align 8 + store i8* bitcast ([5 x %struct.S1998]* @a1998 to i8*), i8** getelementptr inbounds (%struct.Info* @info, i32 0, i32 3), align 8 + store i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 3) to i8*), i8** getelementptr inbounds (%struct.Info* @info, i32 0, i32 4), align 8 + store i64 5168, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 6), align 8 + store i64 16, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 8), align 8 + store i64 16, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 9), align 8 + store i64 16, i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 10), align 8 + %0 = load i64* getelementptr inbounds (%struct.Info* @info, i32 0, i32 8), align 8 + %sub = sub i64 %0, 1 + %and = and i64 ptrtoint (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 3) to i64), %sub + %tobool = icmp ne i64 %and, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %1 = load i32* @fails, align 4 + %inc = add nsw i32 %1, 1 + store i32 %inc, i32* @fails, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + store i32 0, i32* %i, align 4 + store i32 0, i32* %j, align 4 + %2 = load i32* %i, align 4 + %idxprom = sext i32 %2 to i64 + %arrayidx = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom + store i8* bitcast (i32** getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 0, i64 1) to i8*), i8** %arrayidx, align 8 + %3 = load i32* %i, align 4 + %idxprom1 = sext i32 %3 to i64 + %arrayidx2 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom1 + store i64 8, i64* %arrayidx2, align 8 + %4 = load i32* %i, align 4 + %idxprom3 = sext i32 %4 to i64 + %arrayidx4 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom3 + store i64 8, i64* %arrayidx4, align 8 + store i32* getelementptr inbounds ([256 x i32]* @intarray, i32 0, i64 190), i32** getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 0, i64 1), align 8 + store i32* getelementptr inbounds ([256 x i32]* @intarray, i32 0, i64 241), i32** getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 0, i64 1), align 8 + %5 = load i32* %i, align 4 + %inc5 = add nsw i32 %5, 1 + store i32 %inc5, i32* %i, align 4 + %6 = load i32* %i, align 4 + %idxprom6 = sext i32 %6 to i64 + %arrayidx7 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom6 + store i8* bitcast (i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 1) to i8*), i8** %arrayidx7, align 8 + %7 = load i32* %i, align 4 + %idxprom8 = sext i32 %7 to i64 + %arrayidx9 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom8 + store i64 8, i64* %arrayidx9, align 8 + %8 = load i32* %i, align 4 + %idxprom10 = sext i32 %8 to i64 + %arrayidx11 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom10 + store i64 8, i64* %arrayidx11, align 8 + store i64 -3866974208859106459, i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 1), align 8 + store i64 -185376695371304091, i64* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 1), align 8 + %9 = load i32* %i, align 4 + %inc12 = add nsw i32 %9, 1 + store i32 %inc12, i32* %i, align 4 + %10 = load i32* %i, align 4 + %idxprom13 = sext i32 %10 to i64 + %arrayidx14 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom13 + store i8* bitcast (i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 2) to i8*), i8** %arrayidx14, align 8 + %11 = load i32* %i, align 4 + %idxprom15 = sext i32 %11 to i64 + %arrayidx16 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom15 + store i64 8, i64* %arrayidx16, align 8 + %12 = load i32* %i, align 4 + %idxprom17 = sext i32 %12 to i64 + %arrayidx18 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom17 + store i64 8, i64* %arrayidx18, align 8 + store i64 -963638028680427187, i64* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 2), align 8 + store i64 7510542175772455554, i64* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 2), align 8 + %13 = load i32* %i, align 4 + %inc19 = add nsw i32 %13, 1 + store i32 %inc19, i32* %i, align 4 + %14 = load i32* %i, align 4 + %idxprom20 = sext i32 %14 to i64 + %arrayidx21 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom20 + store i8* bitcast (double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 3) to i8*), i8** %arrayidx21, align 8 + %15 = load i32* %i, align 4 + %idxprom22 = sext i32 %15 to i64 + %arrayidx23 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom22 + store i64 8, i64* %arrayidx23, align 8 + %16 = load i32* %i, align 4 + %idxprom24 = sext i32 %16 to i64 + %arrayidx25 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom24 + store i64 16, i64* %arrayidx25, align 8 + store double 0xC0F8783300000000, double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 3), align 16 + store double 0xC10DF3CCC0000000, double* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 3), align 16 + %17 = load i32* %i, align 4 + %inc26 = add nsw i32 %17, 1 + store i32 %inc26, i32* %i, align 4 + %18 = load i32* %i, align 4 + %idxprom27 = sext i32 %18 to i64 + %arrayidx28 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom27 + store i8* bitcast (i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 4) to i8*), i8** %arrayidx28, align 8 + %19 = load i32* %i, align 4 + %idxprom29 = sext i32 %19 to i64 + %arrayidx30 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom29 + store i64 2, i64* %arrayidx30, align 8 + %20 = load i32* %i, align 4 + %idxprom31 = sext i32 %20 to i64 + %arrayidx32 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom31 + store i64 2, i64* %arrayidx32, align 8 + store i16 -15897, i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 4), align 2 + store i16 30935, i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 4), align 2 + %21 = load i32* %i, align 4 + %inc33 = add nsw i32 %21, 1 + store i32 %inc33, i32* %i, align 4 + store i32 -419541644, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 5), align 4 + store i32 2125926812, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 5), align 4 + %22 = load i32* %j, align 4 + %inc34 = add nsw i32 %22, 1 + store i32 %inc34, i32* %j, align 4 + %23 = load i32* %i, align 4 + %idxprom35 = sext i32 %23 to i64 + %arrayidx36 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom35 + store i8* bitcast (double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 0, i64 0) to i8*), i8** %arrayidx36, align 8 + %24 = load i32* %i, align 4 + %idxprom37 = sext i32 %24 to i64 + %arrayidx38 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom37 + store i64 8, i64* %arrayidx38, align 8 + %25 = load i32* %i, align 4 + %idxprom39 = sext i32 %25 to i64 + %arrayidx40 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom39 + store i64 8, i64* %arrayidx40, align 8 + store double 0xC0FC765780000000, double* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 0, i64 0), align 8 + store double 0xC1025CD7A0000000, double* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 0, i64 0), align 8 + %26 = load i32* %i, align 4 + %inc41 = add nsw i32 %26, 1 + store i32 %inc41, i32* %i, align 4 + %bf.load = load i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 1), align 8 + %bf.clear = and i32 %bf.load, 7 + %bf.set = or i32 %bf.clear, 16 + store i32 %bf.set, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 1), align 8 + %bf.load42 = load i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 1), align 8 + %bf.clear43 = and i32 %bf.load42, 7 + %bf.set44 = or i32 %bf.clear43, 24 + store i32 %bf.set44, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 1), align 8 + %27 = load i32* %j, align 4 + %inc45 = add nsw i32 %27, 1 + store i32 %inc45, i32* %j, align 4 + %bf.load46 = load i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 2), align 4 + %bf.clear47 = and i16 %bf.load46, 127 + store i16 %bf.clear47, i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 2), align 4 + %bf.load48 = load i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 2), align 4 + %bf.clear49 = and i16 %bf.load48, 127 + store i16 %bf.clear49, i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 2), align 4 + %28 = load i32* %j, align 4 + %inc50 = add nsw i32 %28, 1 + store i32 %inc50, i32* %j, align 4 + %bf.load51 = load i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 3), align 8 + %bf.clear52 = and i32 %bf.load51, 63 + store i32 %bf.clear52, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 3), align 8 + %bf.load53 = load i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 3), align 8 + %bf.clear54 = and i32 %bf.load53, 63 + %bf.set55 = or i32 %bf.clear54, 64 + store i32 %bf.set55, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 3), align 8 + %29 = load i32* %j, align 4 + %inc56 = add nsw i32 %29, 1 + store i32 %inc56, i32* %j, align 4 + %bf.load57 = load i24* bitcast ([3 x i8]* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 4) to i24*), align 4 + %bf.clear58 = and i24 %bf.load57, 63 + store i24 %bf.clear58, i24* bitcast ([3 x i8]* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 4) to i24*), align 4 + %bf.load59 = load i24* bitcast ([3 x i8]* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 4) to i24*), align 4 + %bf.clear60 = and i24 %bf.load59, 63 + store i24 %bf.clear60, i24* bitcast ([3 x i8]* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 4) to i24*), align 4 + %30 = load i32* %j, align 4 + %inc61 = add nsw i32 %30, 1 + store i32 %inc61, i32* %j, align 4 + %31 = load i32* %i, align 4 + %idxprom62 = sext i32 %31 to i64 + %arrayidx63 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom62 + store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 5), i8** %arrayidx63, align 8 + %32 = load i32* %i, align 4 + %idxprom64 = sext i32 %32 to i64 + %arrayidx65 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom64 + store i64 1, i64* %arrayidx65, align 8 + %33 = load i32* %i, align 4 + %idxprom66 = sext i32 %33 to i64 + %arrayidx67 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom66 + store i64 1, i64* %arrayidx67, align 8 + store i8 -83, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 5), align 1 + store i8 -67, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 5, i64 5), align 1 + %34 = load i32* %i, align 4 + %inc68 = add nsw i32 %34, 1 + store i32 %inc68, i32* %i, align 4 + %35 = load i32* %i, align 4 + %idxprom69 = sext i32 %35 to i64 + %arrayidx70 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom69 + store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 1), i8** %arrayidx70, align 8 + %36 = load i32* %i, align 4 + %idxprom71 = sext i32 %36 to i64 + %arrayidx72 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom71 + store i64 1, i64* %arrayidx72, align 8 + %37 = load i32* %i, align 4 + %idxprom73 = sext i32 %37 to i64 + %arrayidx74 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom73 + store i64 1, i64* %arrayidx74, align 8 + store i8 34, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 5, i64 1), align 1 + store i8 64, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 5, i64 1), align 1 + %38 = load i32* %i, align 4 + %inc75 = add nsw i32 %38, 1 + store i32 %inc75, i32* %i, align 4 + %39 = load i32* %i, align 4 + %idxprom76 = sext i32 %39 to i64 + %arrayidx77 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom76 + store i8* bitcast (i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 6, i64 3) to i8*), i8** %arrayidx77, align 8 + %40 = load i32* %i, align 4 + %idxprom78 = sext i32 %40 to i64 + %arrayidx79 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom78 + store i64 4, i64* %arrayidx79, align 8 + %41 = load i32* %i, align 4 + %idxprom80 = sext i32 %41 to i64 + %arrayidx81 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom80 + store i64 4, i64* %arrayidx81, align 8 + store i32 -3, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 6, i64 3), align 4 + store i32 -3, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 6, i64 3), align 4 + %42 = load i32* %i, align 4 + %inc82 = add nsw i32 %42, 1 + store i32 %inc82, i32* %i, align 4 + %43 = load i32* %i, align 4 + %idxprom83 = sext i32 %43 to i64 + %arrayidx84 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom83 + store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 7), i8** %arrayidx84, align 8 + %44 = load i32* %i, align 4 + %idxprom85 = sext i32 %44 to i64 + %arrayidx86 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom85 + store i64 1, i64* %arrayidx86, align 8 + %45 = load i32* %i, align 4 + %idxprom87 = sext i32 %45 to i64 + %arrayidx88 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom87 + store i64 1, i64* %arrayidx88, align 8 + store i8 106, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 6, i64 4, i32 7), align 1 + store i8 -102, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 6, i64 4, i32 7), align 1 + %46 = load i32* %i, align 4 + %inc89 = add nsw i32 %46, 1 + store i32 %inc89, i32* %i, align 4 + %47 = load i32* %i, align 4 + %idxprom90 = sext i32 %47 to i64 + %arrayidx91 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom90 + store i8* bitcast (i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 7) to i8*), i8** %arrayidx91, align 8 + %48 = load i32* %i, align 4 + %idxprom92 = sext i32 %48 to i64 + %arrayidx93 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom92 + store i64 2, i64* %arrayidx93, align 8 + %49 = load i32* %i, align 4 + %idxprom94 = sext i32 %49 to i64 + %arrayidx95 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom94 + store i64 2, i64* %arrayidx95, align 8 + store i16 29665, i16* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 7), align 2 + store i16 7107, i16* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 7), align 2 + %50 = load i32* %i, align 4 + %inc96 = add nsw i32 %50, 1 + store i32 %inc96, i32* %i, align 4 + %51 = load i32* %i, align 4 + %idxprom97 = sext i32 %51 to i64 + %arrayidx98 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom97 + store i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 8), i8** %arrayidx98, align 8 + %52 = load i32* %i, align 4 + %idxprom99 = sext i32 %52 to i64 + %arrayidx100 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom99 + store i64 1, i64* %arrayidx100, align 8 + %53 = load i32* %i, align 4 + %idxprom101 = sext i32 %53 to i64 + %arrayidx102 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom101 + store i64 1, i64* %arrayidx102, align 8 + store i8 52, i8* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 8), align 1 + store i8 -86, i8* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 8), align 1 + %54 = load i32* %i, align 4 + %inc103 = add nsw i32 %54, 1 + store i32 %inc103, i32* %i, align 4 + %55 = load i32* %i, align 4 + %idxprom104 = sext i32 %55 to i64 + %arrayidx105 = getelementptr inbounds [32 x i8*]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 5), i32 0, i64 %idxprom104 + store i8* bitcast (i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 9) to i8*), i8** %arrayidx105, align 8 + %56 = load i32* %i, align 4 + %idxprom106 = sext i32 %56 to i64 + %arrayidx107 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 7), i32 0, i64 %idxprom106 + store i64 4, i64* %arrayidx107, align 8 + %57 = load i32* %i, align 4 + %idxprom108 = sext i32 %57 to i64 + %arrayidx109 = getelementptr inbounds [32 x i64]* getelementptr inbounds (%struct.Info* @info, i32 0, i32 11), i32 0, i64 %idxprom108 + store i64 4, i64* %arrayidx109, align 8 + store i32 -54118453, i32* getelementptr inbounds (%struct.S1998* @s1998, i32 0, i32 9), align 4 + store i32 1668755823, i32* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2, i32 9), align 4 + %58 = load i32* %i, align 4 + %inc110 = add nsw i32 %58, 1 + store i32 %inc110, i32* %i, align 4 + store i32 %inc110, i32* %tmp + %59 = load i32* %tmp + %60 = load i32* %i, align 4 + store i32 %60, i32* getelementptr inbounds (%struct.Info* @info, i32 0, i32 0), align 4 + %61 = load i32* %j, align 4 + store i32 %61, i32* getelementptr inbounds (%struct.Info* @info, i32 0, i32 1), align 4 + %62 = bitcast %struct.S1998* %agg.tmp111 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %62, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) + %63 = bitcast %struct.S1998* %agg.tmp112 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %63, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) + call void @check1998(%struct.S1998* sret %agg.tmp, %struct.S1998* byval align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval align 16 %agg.tmp112) + call void @checkx1998(%struct.S1998* byval align 16 %agg.tmp) + %64 = bitcast %struct.S1998* %agg.tmp113 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %64, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) + %65 = bitcast %struct.S1998* %agg.tmp114 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %65, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) + %66 = bitcast %struct.S1998* %agg.tmp115 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %66, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) + call void (i32, ...)* @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115) + %67 = bitcast %struct.S1998* %agg.tmp116 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %67, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) + %68 = bitcast %struct.S1998* %agg.tmp117 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %68, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) + %69 = bitcast %struct.S1998* %agg.tmp118 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %69, i8* bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i32 16, i1 false) + %70 = bitcast %struct.S1998* %agg.tmp119 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %70, i8* bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i32 16, i1 false) + call void (i32, ...)* @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119) + ret void +} + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) + +declare void @check1998(%struct.S1998* sret, %struct.S1998* byval align 16, %struct.S1998*, %struct.S1998* byval align 16) +declare void @check1998va(i32 signext, ...) +declare void @checkx1998(%struct.S1998* byval align 16 %arg) + Index: llvm-suse/test/CodeGen/PowerPC/resolvefi-disp.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/resolvefi-disp.ll @@ -0,0 +1,71 @@ +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -print-after=localstackalloc <%s >%t 2>&1 && FileCheck <%t %s + +; Due to a bug in isFrameOffsetLegal we ended up with resolveFrameIndex creating +; addresses with out-of-range displacements. Verify that this no longer happens. +; CHECK-NOT: LD {{3276[8-9]}} +; CHECK-NOT: LD {{327[7-9][0-9]}} +; CHECK-NOT: LD {{32[8-9][0-9][0-9]}} +; CHECK-NOT: LD {{3[3-9][0-9][0-9][0-9]}} +; CHECK-NOT: LD {{[4-9][0-9][0-9][0-9][0-9]}} +; CHECK-NOT: LD {{[1-9][0-9][0-9][0-9][0-9][0-9]+}} + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +%struct.S2760 = type { <2 x float>, %struct.anon, i32, [28 x i8] } +%struct.anon = type { [11 x %struct.anon.0], i64, [6 x { i64, i64 }], [24 x i8] } +%struct.anon.0 = type { [30 x %union.U4DI], i8, [0 x i16], [30 x i8] } +%union.U4DI = type { <4 x i64> } + +@s2760 = external global %struct.S2760 +@fails = external global i32 + +define void @check2760(%struct.S2760* noalias sret %agg.result, %struct.S2760* byval align 16, %struct.S2760* %arg1, %struct.S2760* byval align 16) { +entry: + %arg0 = alloca %struct.S2760, align 32 + %arg2 = alloca %struct.S2760, align 32 + %arg1.addr = alloca %struct.S2760*, align 8 + %ret = alloca %struct.S2760, align 32 + %b1 = alloca %struct.S2760, align 32 + %b2 = alloca %struct.S2760, align 32 + %2 = bitcast %struct.S2760* %arg0 to i8* + %3 = bitcast %struct.S2760* %0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 11104, i32 16, i1 false) + %4 = bitcast %struct.S2760* %arg2 to i8* + %5 = bitcast %struct.S2760* %1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %4, i8* %5, i64 11104, i32 16, i1 false) + store %struct.S2760* %arg1, %struct.S2760** %arg1.addr, align 8 + %6 = bitcast %struct.S2760* %ret to i8* + call void @llvm.memset.p0i8.i64(i8* %6, i8 0, i64 11104, i32 32, i1 false) + %7 = bitcast %struct.S2760* %b1 to i8* + call void @llvm.memset.p0i8.i64(i8* %7, i8 0, i64 11104, i32 32, i1 false) + %8 = bitcast %struct.S2760* %b2 to i8* + call void @llvm.memset.p0i8.i64(i8* %8, i8 0, i64 11104, i32 32, i1 false) + %b = getelementptr inbounds %struct.S2760* %arg0, i32 0, i32 1 + %g = getelementptr inbounds %struct.anon* %b, i32 0, i32 1 + %9 = load i64* %g, align 8 + %10 = load i64* getelementptr inbounds (%struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8 + %cmp = icmp ne i64 %9, %10 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %11 = load i32* @fails, align 4 + %inc = add nsw i32 %11, 1 + store i32 %inc, i32* @fails, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + %12 = load i64* getelementptr inbounds (%struct.S2760* @s2760, i32 0, i32 1, i32 1), align 8 + %b3 = getelementptr inbounds %struct.S2760* %ret, i32 0, i32 1 + %g4 = getelementptr inbounds %struct.anon* %b3, i32 0, i32 1 + store i64 %12, i64* %g4, align 8 + %13 = bitcast %struct.S2760* %agg.result to i8* + %14 = bitcast %struct.S2760* %ret to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %13, i8* %14, i64 11104, i32 32, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) + Index: llvm-suse/test/CodeGen/PowerPC/splat-bug.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/splat-bug.ll @@ -0,0 +1,18 @@ +; RUN: llc -mcpu=ppc64 -O0 -fast-isel=false < %s | FileCheck %s + +; Checks for a previous bug where vspltisb/vaddubm were issued in place +; of vsplitsh/vadduhm. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@a = external global <16 x i8> + +define void @foo() nounwind ssp { +; CHECK: foo: + store <16 x i8> <i8 0, i8 16, i8 0, i8 16, i8 0, i8 16, i8 0, i8 16, i8 0, i8 16, i8 0, i8 16, i8 0, i8 16, i8 0, i8 16>, <16 x i8>* @a +; CHECK: vspltish [[REG:[0-9]+]], 8 +; CHECK: vadduhm {{[0-9]+}}, [[REG]], [[REG]] + ret void +} + Index: llvm-suse/test/CodeGen/PowerPC/svr4-redzone.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/svr4-redzone.ll +++ llvm-suse/test/CodeGen/PowerPC/svr4-redzone.ll @@ -36,4 +36,4 @@ entry: ; PPC32: stwu 1, -240(1) ; PPC64-LABEL: bigstack: -; PPC64: stdu 1, -352(1) +; PPC64: stdu 1, -288(1) Index: llvm-suse/test/CodeGen/PowerPC/varargs-struct-float.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/varargs-struct-float.ll +++ llvm-suse/test/CodeGen/PowerPC/varargs-struct-float.ll @@ -16,8 +16,8 @@ entry: ret void } -; CHECK: stfs {{[0-9]+}}, 60(1) -; CHECK: ld 4, 56(1) +; CHECK: stfs {{[0-9]+}}, 116(1) +; CHECK: lwz 4, 116(1) ; CHECK: bl declare void @testvaSf1(i32, ...) Index: llvm-suse/test/CodeGen/PowerPC/vec_cmp.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/vec_cmp.ll +++ llvm-suse/test/CodeGen/PowerPC/vec_cmp.ll @@ -63,9 +63,8 @@ entry: ret <16 x i8> %sext } ; CHECK-LABEL: v16si8_cmp_le: -; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgtsb [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <16 x i8> @v16ui8_cmp_le(<16 x i8> %x, <16 x i8> %y) nounwind readnone { entry: @@ -74,9 +73,8 @@ entry: ret <16 x i8> %sext } ; CHECK-LABEL: v16ui8_cmp_le: -; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgtub [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <16 x i8> @v16si8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone { entry: @@ -121,9 +119,8 @@ entry: ret <16 x i8> %sext } ; CHECK-LABEL: v16si8_cmp_ge: -; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3 -; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] +; CHECK: vcmpgtsb [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <16 x i8> @v16ui8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone { entry: @@ -132,9 +129,8 @@ entry: ret <16 x i8> %sext } ; CHECK-LABEL: v16ui8_cmp_ge: -; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3 -; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] +; CHECK: vcmpgtub [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone { @@ -193,9 +189,8 @@ entry: ret <8 x i16> %sext } ; CHECK-LABEL: v8si16_cmp_le: -; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgtsh [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <8 x i16> @v8ui16_cmp_le(<8 x i16> %x, <8 x i16> %y) nounwind readnone { entry: @@ -204,9 +199,8 @@ entry: ret <8 x i16> %sext } ; CHECK-LABEL: v8ui16_cmp_le: -; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgtuh [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <8 x i16> @v8si16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone { entry: @@ -251,9 +245,8 @@ entry: ret <8 x i16> %sext } ; CHECK-LABEL: v8si16_cmp_ge: -; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3 -; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] +; CHECK: vcmpgtsh [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <8 x i16> @v8ui16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone { entry: @@ -262,9 +255,8 @@ entry: ret <8 x i16> %sext } ; CHECK-LABEL: v8ui16_cmp_ge: -; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3 -; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] +; CHECK: vcmpgtuh [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone { @@ -326,9 +318,8 @@ entry: ret <4 x i32> %sext } ; CHECK-LABEL: v4si32_cmp_le: -; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgtsw [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <4 x i32> @v4ui32_cmp_le(<4 x i32> %x, <4 x i32> %y) nounwind readnone { entry: @@ -337,9 +328,8 @@ entry: ret <4 x i32> %sext } ; CHECK-LABEL: v4ui32_cmp_le: -; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgtuw [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <4 x i32> @v4si32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone { entry: @@ -384,9 +374,8 @@ entry: ret <4 x i32> %sext } ; CHECK-LABEL: v4si32_cmp_ge: -; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3 -; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] +; CHECK: vcmpgtsw [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <4 x i32> @v4ui32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone { entry: @@ -395,9 +384,8 @@ entry: ret <4 x i32> %sext } ; CHECK-LABEL: v4ui32_cmp_ge: -; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3 -; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]] +; CHECK: vcmpgtuw [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone { @@ -480,9 +468,7 @@ entry: ret <4 x float> %0 } ; CHECK-LABEL: v4f32_cmp_le: -; CHECK: vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3 -; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2 -; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]] +; CHECK: vcmpgefp 2, 3, 2 define <4 x float> @v4f32_cmp_lt(<4 x float> %x, <4 x float> %y) nounwind readnone { entry: @@ -514,6 +500,50 @@ entry: ; CHECK-LABEL: v4f32_cmp_gt: ; CHECK: vcmpgtfp 2, 2, 3 +define <4 x float> @v4f32_cmp_ule(<4 x float> %x, <4 x float> %y) nounwind readnone { +entry: + %cmp = fcmp ule <4 x float> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i32> + %0 = bitcast <4 x i32> %sext to <4 x float> + ret <4 x float> %0 +} +; CHECK-LABEL: v4f32_cmp_ule: +; CHECK: vcmpgtfp [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] + +define <4 x float> @v4f32_cmp_ult(<4 x float> %x, <4 x float> %y) nounwind readnone { +entry: + %cmp = fcmp ult <4 x float> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i32> + %0 = bitcast <4 x i32> %sext to <4 x float> + ret <4 x float> %0 +} +; CHECK-LABEL: v4f32_cmp_ult: +; CHECK: vcmpgefp [[RET:[0-9]+]], 2, 3 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] + +define <4 x float> @v4f32_cmp_uge(<4 x float> %x, <4 x float> %y) nounwind readnone { +entry: + %cmp = fcmp uge <4 x float> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i32> + %0 = bitcast <4 x i32> %sext to <4 x float> + ret <4 x float> %0 +} +; CHECK-LABEL: v4f32_cmp_uge: +; CHECK: vcmpgtfp [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] + +define <4 x float> @v4f32_cmp_ugt(<4 x float> %x, <4 x float> %y) nounwind readnone { +entry: + %cmp = fcmp ugt <4 x float> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i32> + %0 = bitcast <4 x i32> %sext to <4 x float> + ret <4 x float> %0 +} +; CHECK-LABEL: v4f32_cmp_ugt: +; CHECK: vcmpgefp [[RET:[0-9]+]], 3, 2 +; CHECK-NEXT: vnor 2, [[RET]], [[RET]] + define <8 x float> @v8f32_cmp(<8 x float> %x, <8 x float> %y) nounwind readnone { entry: Index: llvm-suse/test/CodeGen/PowerPC/vec_misaligned.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/vec_misaligned.ll +++ llvm-suse/test/CodeGen/PowerPC/vec_misaligned.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=ppc32 -mcpu=g5 +; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" @@ -8,6 +10,8 @@ target triple = "powerpc-apple-darwin8" define void @foo(i32 %x, ...) { entry: +; CHECK: foo: +; CHECK-LE: foo: %x_addr = alloca i32 ; <i32*> [#uses=1] %ap = alloca i8* ; <i8**> [#uses=3] %ap.0 = alloca i8* ; <i8**> [#uses=3] @@ -27,6 +31,10 @@ entry: %tmp8 = getelementptr %struct.u16qi* %tmp6, i32 0, i32 0 ; <<16 x i8>*> [#uses=1] %tmp9 = getelementptr %struct.u16qi* %tmp7, i32 0, i32 0 ; <<16 x i8>*> [#uses=1] %tmp10 = load <16 x i8>* %tmp9, align 4 ; <<16 x i8>> [#uses=1] +; CHECK: lvsl +; CHECK: vperm +; CHECK-LE: lvsr +; CHECK-LE: vperm store <16 x i8> %tmp10, <16 x i8>* %tmp8, align 4 br label %return Index: llvm-suse/test/CodeGen/PowerPC/vec_mul.ll =================================================================== --- llvm-suse.orig/test/CodeGen/PowerPC/vec_mul.ll +++ llvm-suse/test/CodeGen/PowerPC/vec_mul.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { %tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1] @@ -9,6 +11,9 @@ define <4 x i32> @test_v4i32(<4 x i32>* ; CHECK-LABEL: test_v4i32: ; CHECK: vmsumuhm ; CHECK-NOT: mullw +; CHECK-LE-LABEL: test_v4i32: +; CHECK-LE: vmsumuhm +; CHECK-LE-NOT: mullw define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) { %tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1] @@ -19,6 +24,9 @@ define <8 x i16> @test_v8i16(<8 x i16>* ; CHECK-LABEL: test_v8i16: ; CHECK: vmladduhm ; CHECK-NOT: mullw +; CHECK-LE-LABEL: test_v8i16: +; CHECK-LE: vmladduhm +; CHECK-LE-NOT: mullw define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) { %tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1] @@ -30,6 +38,11 @@ define <16 x i8> @test_v16i8(<16 x i8>* ; CHECK: vmuloub ; CHECK: vmuleub ; CHECK-NOT: mullw +; CHECK-LE-LABEL: test_v16i8: +; CHECK-LE: vmuloub [[REG1:[0-9]+]] +; CHECK-LE: vmuleub [[REG2:[0-9]+]] +; CHECK-LE: vperm {{[0-9]+}}, [[REG2]], [[REG1]] +; CHECK-LE-NOT: mullw define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) { %tmp = load <4 x float>* %X @@ -44,3 +57,7 @@ define <4 x float> @test_float(<4 x floa ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1 ; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]] ; CHECK: vmaddfp +; CHECK-LE-LABEL: test_float: +; CHECK-LE: vspltisw [[ZNEG:[0-9]+]], -1 +; CHECK-LE: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]] +; CHECK-LE: vmaddfp Index: llvm-suse/test/CodeGen/PowerPC/vec_shuffle_le.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/vec_shuffle_le.ll @@ -0,0 +1,209 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s + +define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VPKUHUM_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VPKUHUM_xx(<16 x i8>* %A) { +entry: +; CHECK: VPKUHUM_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> +; CHECK: vpkuhum + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VPKUWUM_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VPKUWUM_xx(<16 x i8>* %A) { +entry: +; CHECK: VPKUWUM_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13> +; CHECK: vpkuwum + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VMRGLB_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VMRGLB_xx(<16 x i8>* %A) { +entry: +; CHECK: VMRGLB_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7> +; CHECK: vmrglb + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VMRGHB_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VMRGHB_xx(<16 x i8>* %A) { +entry: +; CHECK: VMRGHB_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15> +; CHECK: vmrghb + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VMRGLH_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VMRGLH_xx(<16 x i8>* %A) { +entry: +; CHECK: VMRGLH_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7> +; CHECK: vmrglh + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VMRGHH_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VMRGHH_xx(<16 x i8>* %A) { +entry: +; CHECK: VMRGHH_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15> +; CHECK: vmrghh + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VMRGLW_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VMRGLW_xx(<16 x i8>* %A) { +entry: +; CHECK: VMRGLW_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7> +; CHECK: vmrglw + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VMRGHW_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]] + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VMRGHW_xx(<16 x i8>* %A) { +entry: +; CHECK: VMRGHW_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15> +; CHECK: vmrghw + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + +define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) { +entry: +; CHECK: VSLDOI_xy: + %tmp = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4 + store <16 x i8> %tmp3, <16 x i8>* %A + ret void +} + +define void @VSLDOI_xx(<16 x i8>* %A) { +entry: +; CHECK: VSLDOI_xx: + %tmp = load <16 x i8>* %A + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> +; CHECK: vsldoi + store <16 x i8> %tmp2, <16 x i8>* %A + ret void +} + Index: llvm-suse/test/CodeGen/PowerPC/vec_urem_const.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/vec_urem_const.ll @@ -0,0 +1,13 @@ +; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; Common code used to replace the urem by a mulhu, and compilation would +; then crash since mulhu isn't supported on vector types. + +define <4 x i32> @test(<4 x i32> %x) { +entry: + %0 = urem <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> + ret <4 x i32> %0 +} Index: llvm-suse/test/CodeGen/PowerPC/vperm-instcombine.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/vperm-instcombine.ll @@ -0,0 +1,17 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +define <16 x i8> @foo() nounwind ssp { +; CHECK: @foo +;; Arguments are {0,1,...,15},{16,17,...,31},{30,28,26,...,0} + %1 = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> <i32 50462976, i32 117835012, i32 185207048, i32 252579084>, <4 x i32> <i32 319951120, i32 387323156, i32 454695192, i32 522067228>, <16 x i8> <i8 30, i8 28, i8 26, i8 24, i8 22, i8 20, i8 18, i8 16, i8 14, i8 12, i8 10, i8 8, i8 6, i8 4, i8 2, i8 0>) + %2 = bitcast <4 x i32> %1 to <16 x i8> + ret <16 x i8> %2 +;; Revised arguments are {16,17,...31},{0,1,...,15},{1,3,5,...,31} +;; optimized into the following: +; CHECK: ret <16 x i8> <i8 17, i8 19, i8 21, i8 23, i8 25, i8 27, i8 29, i8 31, i8 1, i8 3, i8 5, i8 7, i8 9, i8 11, i8 13, i8 15> +} + +declare <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>, <4 x i32>, <16 x i8>) Index: llvm-suse/test/CodeGen/PowerPC/vperm-lowering.ll =================================================================== --- /dev/null +++ llvm-suse/test/CodeGen/PowerPC/vperm-lowering.ll @@ -0,0 +1,66 @@ +; RUN: llc -O0 -fast-isel=false -mcpu=ppc64 < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +define <16 x i8> @foo() nounwind ssp { + %1 = shufflevector <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 3, i32 8, i32 13, i32 18, i32 23, i32 28, i32 1, i32 6, i32 11> + ret <16 x i8> %1 +} + +; CHECK: .LCPI0_0: +; CHECK: .byte 31 +; CHECK: .byte 26 +; CHECK: .byte 21 +; CHECK: .byte 16 +; CHECK: .byte 11 +; CHECK: .byte 6 +; CHECK: .byte 1 +; CHECK: .byte 28 +; CHECK: .byte 23 +; CHECK: .byte 18 +; CHECK: .byte 13 +; CHECK: .byte 8 +; CHECK: .byte 3 +; CHECK: .byte 30 +; CHECK: .byte 25 +; CHECK: .byte 20 +; CHECK: .LCPI0_1: +; CHECK: .byte 0 +; CHECK: .byte 1 +; CHECK: .byte 2 +; CHECK: .byte 3 +; CHECK: .byte 4 +; CHECK: .byte 5 +; CHECK: .byte 6 +; CHECK: .byte 7 +; CHECK: .byte 8 +; CHECK: .byte 9 +; CHECK: .byte 10 +; CHECK: .byte 11 +; CHECK: .byte 12 +; CHECK: .byte 13 +; CHECK: .byte 14 +; CHECK: .byte 15 +; CHECK: .LCPI0_2: +; CHECK: .byte 16 +; CHECK: .byte 17 +; CHECK: .byte 18 +; CHECK: .byte 19 +; CHECK: .byte 20 +; CHECK: .byte 21 +; CHECK: .byte 22 +; CHECK: .byte 23 +; CHECK: .byte 24 +; CHECK: .byte 25 +; CHECK: .byte 26 +; CHECK: .byte 27 +; CHECK: .byte 28 +; CHECK: .byte 29 +; CHECK: .byte 30 +; CHECK: .byte 31 +; CHECK: foo: +; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI0_2@toc@ha +; CHECK: addi [[REG2:[0-9]+]], [[REG1]], .LCPI0_2@toc@l +; CHECK: lvx [[REG3:[0-9]+]], 0, [[REG2]] +; CHECK: vperm {{[0-9]+}}, [[REG3]], {{[0-9]+}}, {{[0-9]+}} Index: llvm-suse/test/CodeGen/X86/float-asmprint.ll =================================================================== --- llvm-suse.orig/test/CodeGen/X86/float-asmprint.ll +++ llvm-suse/test/CodeGen/X86/float-asmprint.ll @@ -16,8 +16,9 @@ ; CHECK-NEXT: .size ; CHECK: varppc128: -; CHECK-NEXT: .quad 0 # ppc_fp128 -0 -; CHECK-NEXT: .quad -9223372036854775808 +; For ppc_fp128, the high double always comes first. +; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0 +; CHECK-NEXT: .quad 0 ; CHECK-NEXT: .size ; CHECK: var80: Index: llvm-suse/test/ExecutionEngine/MCJIT/eh-lg-pic.ll =================================================================== --- llvm-suse.orig/test/ExecutionEngine/MCJIT/eh-lg-pic.ll +++ llvm-suse/test/ExecutionEngine/MCJIT/eh-lg-pic.ll @@ -1,5 +1,5 @@ ; RUN: %lli_mcjit -relocation-model=pic -code-model=large %s -; XFAIL: cygwin, win32, mingw, mips, powerpc64, i686, i386, aarch64, arm +; XFAIL: cygwin, win32, mingw, mips, i686, i386, aarch64, arm declare i8* @__cxa_allocate_exception(i64) declare void @__cxa_throw(i8*, i8*, i8*) declare i32 @__gxx_personality_v0(...) Index: llvm-suse/test/ExecutionEngine/lit.local.cfg =================================================================== --- llvm-suse.orig/test/ExecutionEngine/lit.local.cfg +++ llvm-suse/test/ExecutionEngine/lit.local.cfg @@ -4,6 +4,9 @@ if config.root.host_arch in ['PowerPC', if 'hexagon' in config.root.target_triple: config.unsupported = True +if 'powerpc64' in config.root.target_triple: + config.unsupported = True + # ExecutionEngine tests are not expected to pass in a cross-compilation setup. if 'native' not in config.available_features: config.unsupported = True Index: llvm-suse/test/MC/PowerPC/deprecated-p7.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/deprecated-p7.s +++ llvm-suse/test/MC/PowerPC/deprecated-p7.s @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 -show-encoding < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu -mcpu=pwr7 -show-encoding < %s 2>&1 | FileCheck %s # RUN: llvm-mc -triple powerpc-unknown-linux-gnu -mcpu=601 -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-OLD %s mftb 3 Index: llvm-suse/test/MC/PowerPC/ppc-llong.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc-llong.s +++ llvm-suse/test/MC/PowerPC/ppc-llong.s @@ -3,6 +3,8 @@ # RUN: llvm-readobj -s -sd | FileCheck %s # RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ # RUN: llvm-readobj -s -sd | FileCheck %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -s -sd | FileCheck %s .data .llong 0 Index: llvm-suse/test/MC/PowerPC/ppc-machine.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc-machine.s +++ llvm-suse/test/MC/PowerPC/ppc-machine.s @@ -1,5 +1,6 @@ # RUN: llvm-mc -triple powerpc-unknown-unknown %s # RUN: llvm-mc -triple powerpc64-unknown-unknown %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown %s # For now, the only thing we check is that the .machine directive # is accepted without syntax error. Index: llvm-suse/test/MC/PowerPC/ppc-nop.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc-nop.s +++ llvm-suse/test/MC/PowerPC/ppc-nop.s @@ -1,5 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck %s +# RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck -check-prefix=CHECK-LE %s blr .p2align 3 @@ -8,5 +9,6 @@ blr .byte 0x42 .p2align 2 -# CHECK: 0000: 4E800020 60000000 4E800020 42000000 +# CHECK-BE: 0000: 4E800020 60000000 4E800020 42000000 +# CHECK-LE: 0000: 2000804E 00000060 2000804E 42000000 Index: llvm-suse/test/MC/PowerPC/ppc-word.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc-word.s +++ llvm-suse/test/MC/PowerPC/ppc-word.s @@ -3,6 +3,8 @@ # RUN: llvm-readobj -s -sd | FileCheck %s # RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ # RUN: llvm-readobj -s -sd | FileCheck %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -s -sd | FileCheck %s .data .word 0 Index: llvm-suse/test/MC/PowerPC/ppc64-abiversion.s =================================================================== --- /dev/null +++ llvm-suse/test/MC/PowerPC/ppc64-abiversion.s @@ -0,0 +1,9 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -h | FileCheck %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -h | FileCheck %s + + .abiversion 2 +# CHECK: Flags [ (0x2) + Index: llvm-suse/test/MC/PowerPC/ppc64-encoding-bookII.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-encoding-bookII.s +++ llvm-suse/test/MC/PowerPC/ppc64-encoding-bookII.s @@ -1,82 +1,107 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Cache management instruction -# CHECK: icbi 2, 3 # encoding: [0x7c,0x02,0x1f,0xac] - icbi 2, 3 - -# FIXME: dcbt 2, 3, 10 -# CHECK: dcbt 2, 3 # encoding: [0x7c,0x02,0x1a,0x2c] - dcbt 2, 3 -# FIXME: dcbtst 2, 3, 10 -# CHECK: dcbtst 2, 3 # encoding: [0x7c,0x02,0x19,0xec] - dcbtst 2, 3 -# CHECK: dcbz 2, 3 # encoding: [0x7c,0x02,0x1f,0xec] - dcbz 2, 3 -# CHECK: dcbst 2, 3 # encoding: [0x7c,0x02,0x18,0x6c] - dcbst 2, 3 -# FIXME: dcbf 2, 3, 1 +# CHECK-BE: icbi 2, 3 # encoding: [0x7c,0x02,0x1f,0xac] +# CHECK-LE: icbi 2, 3 # encoding: [0xac,0x1f,0x02,0x7c] + icbi 2, 3 + +# FIXME: dcbt 2, 3, 10 +# CHECK-BE: dcbt 2, 3 # encoding: [0x7c,0x02,0x1a,0x2c] +# CHECK-LE: dcbt 2, 3 # encoding: [0x2c,0x1a,0x02,0x7c] + dcbt 2, 3 +# FIXME: dcbtst 2, 3, 10 +# CHECK-BE: dcbtst 2, 3 # encoding: [0x7c,0x02,0x19,0xec] +# CHECK-LE: dcbtst 2, 3 # encoding: [0xec,0x19,0x02,0x7c] + dcbtst 2, 3 +# CHECK-BE: dcbz 2, 3 # encoding: [0x7c,0x02,0x1f,0xec] +# CHECK-LE: dcbz 2, 3 # encoding: [0xec,0x1f,0x02,0x7c] + dcbz 2, 3 +# CHECK-BE: dcbst 2, 3 # encoding: [0x7c,0x02,0x18,0x6c] +# CHECK-LE: dcbst 2, 3 # encoding: [0x6c,0x18,0x02,0x7c] + dcbst 2, 3 +# FIXME: dcbf 2, 3, 1 # Synchronization instructions -# CHECK: isync # encoding: [0x4c,0x00,0x01,0x2c] - isync - -# FIXME: lbarx 2, 3, 4, 1 -# FIXME: lharx 2, 3, 4, 1 -# FIXME: lwarx 2, 3, 4, 1 -# FIXME: ldarx 2, 3, 4, 1 - -# FIXME: stbcx. 2, 3, 4 -# FIXME: sthcx. 2, 3, 4 -# CHECK: stwcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2d] - stwcx. 2, 3, 4 -# CHECK: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad] - stdcx. 2, 3, 4 - -# CHECK: sync 2 # encoding: [0x7c,0x40,0x04,0xac] - sync 2 -# CHECK: eieio # encoding: [0x7c,0x00,0x06,0xac] - eieio -# CHECK: wait 2 # encoding: [0x7c,0x40,0x00,0x7c] - wait 2 +# CHECK-BE: isync # encoding: [0x4c,0x00,0x01,0x2c] +# CHECK-LE: isync # encoding: [0x2c,0x01,0x00,0x4c] + isync + +# FIXME: lbarx 2, 3, 4, 1 +# FIXME: lharx 2, 3, 4, 1 +# FIXME: lwarx 2, 3, 4, 1 +# FIXME: ldarx 2, 3, 4, 1 + +# FIXME: stbcx. 2, 3, 4 +# FIXME: sthcx. 2, 3, 4 +# CHECK-BE: stwcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2d] +# CHECK-LE: stwcx. 2, 3, 4 # encoding: [0x2d,0x21,0x43,0x7c] + stwcx. 2, 3, 4 +# CHECK-BE: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad] +# CHECK-LE: stdcx. 2, 3, 4 # encoding: [0xad,0x21,0x43,0x7c] + stdcx. 2, 3, 4 + +# CHECK-BE: sync 2 # encoding: [0x7c,0x40,0x04,0xac] +# CHECK-LE: sync 2 # encoding: [0xac,0x04,0x40,0x7c] + sync 2 +# CHECK-BE: eieio # encoding: [0x7c,0x00,0x06,0xac] +# CHECK-LE: eieio # encoding: [0xac,0x06,0x00,0x7c] + eieio +# CHECK-BE: wait 2 # encoding: [0x7c,0x40,0x00,0x7c] +# CHECK-LE: wait 2 # encoding: [0x7c,0x00,0x40,0x7c] + wait 2 # Extended mnemonics -# CHECK: dcbf 2, 3 # encoding: [0x7c,0x02,0x18,0xac] - dcbf 2, 3 -# FIXME: dcbfl 2, 3 - -# FIXME: lbarx 2, 3, 4 -# FIXME: lharx 2, 3, 4 -# CHECK: lwarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x28] - lwarx 2, 3, 4 -# CHECK: ldarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xa8] - ldarx 2, 3, 4 - -# CHECK: sync 0 # encoding: [0x7c,0x00,0x04,0xac] - sync -# CHECK: sync 0 # encoding: [0x7c,0x00,0x04,0xac] - msync -# CHECK: sync 1 # encoding: [0x7c,0x20,0x04,0xac] - lwsync -# CHECK: sync 2 # encoding: [0x7c,0x40,0x04,0xac] - ptesync - -# CHECK: wait 0 # encoding: [0x7c,0x00,0x00,0x7c] - wait -# CHECK: wait 1 # encoding: [0x7c,0x20,0x00,0x7c] - waitrsv -# CHECK: wait 2 # encoding: [0x7c,0x40,0x00,0x7c] - waitimpl +# CHECK-BE: dcbf 2, 3 # encoding: [0x7c,0x02,0x18,0xac] +# CHECK-LE: dcbf 2, 3 # encoding: [0xac,0x18,0x02,0x7c] + dcbf 2, 3 +# FIXME: dcbfl 2, 3 + +# FIXME: lbarx 2, 3, 4 +# FIXME: lharx 2, 3, 4 +# CHECK-BE: lwarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x28] +# CHECK-LE: lwarx 2, 3, 4 # encoding: [0x28,0x20,0x43,0x7c] + lwarx 2, 3, 4 +# CHECK-BE: ldarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xa8] +# CHECK-LE: ldarx 2, 3, 4 # encoding: [0xa8,0x20,0x43,0x7c] + ldarx 2, 3, 4 + +# CHECK-BE: sync 0 # encoding: [0x7c,0x00,0x04,0xac] +# CHECK-LE: sync 0 # encoding: [0xac,0x04,0x00,0x7c] + sync +# CHECK-BE: sync 0 # encoding: [0x7c,0x00,0x04,0xac] +# CHECK-LE: sync 0 # encoding: [0xac,0x04,0x00,0x7c] + msync +# CHECK-BE: sync 1 # encoding: [0x7c,0x20,0x04,0xac] +# CHECK-LE: sync 1 # encoding: [0xac,0x04,0x20,0x7c] + lwsync +# CHECK-BE: sync 2 # encoding: [0x7c,0x40,0x04,0xac] +# CHECK-LE: sync 2 # encoding: [0xac,0x04,0x40,0x7c] + ptesync + +# CHECK-BE: wait 0 # encoding: [0x7c,0x00,0x00,0x7c] +# CHECK-LE: wait 0 # encoding: [0x7c,0x00,0x00,0x7c] + wait +# CHECK-BE: wait 1 # encoding: [0x7c,0x20,0x00,0x7c] +# CHECK-LE: wait 1 # encoding: [0x7c,0x00,0x20,0x7c] + waitrsv +# CHECK-BE: wait 2 # encoding: [0x7c,0x40,0x00,0x7c] +# CHECK-LE: wait 2 # encoding: [0x7c,0x00,0x40,0x7c] + waitimpl # Time base instructions -# CHECK: mftb 2, 123 # encoding: [0x7c,0x5b,0x1a,0xe6] - mftb 2, 123 -# CHECK: mftb 2, 268 # encoding: [0x7c,0x4c,0x42,0xe6] - mftb 2 -# CHECK: mftb 2, 269 # encoding: [0x7c,0x4d,0x42,0xe6] - mftbu 2 +# CHECK-BE: mftb 2, 123 # encoding: [0x7c,0x5b,0x1a,0xe6] +# CHECK-LE: mftb 2, 123 # encoding: [0xe6,0x1a,0x5b,0x7c] + mftb 2, 123 +# CHECK-BE: mftb 2, 268 # encoding: [0x7c,0x4c,0x42,0xe6] +# CHECK-LE: mftb 2, 268 # encoding: [0xe6,0x42,0x4c,0x7c] + mftb 2 +# CHECK-BE: mftb 2, 269 # encoding: [0x7c,0x4d,0x42,0xe6] +# CHECK-LE: mftb 2, 269 # encoding: [0xe6,0x42,0x4d,0x7c] + mftbu 2 Index: llvm-suse/test/MC/PowerPC/ppc64-encoding-bookIII.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-encoding-bookIII.s +++ llvm-suse/test/MC/PowerPC/ppc64-encoding-bookIII.s @@ -1,107 +1,143 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s -# CHECK: mtmsr 4, 0 # encoding: [0x7c,0x80,0x01,0x24] - mtmsr %r4 - -# CHECK: mtmsr 4, 1 # encoding: [0x7c,0x81,0x01,0x24] - mtmsr %r4, 1 - -# CHECK: mfmsr 4 # encoding: [0x7c,0x80,0x00,0xa6] - mfmsr %r4 - -# CHECK: mtmsrd 4, 0 # encoding: [0x7c,0x80,0x01,0x64] - mtmsrd %r4 - -# CHECK: mtmsrd 4, 1 # encoding: [0x7c,0x81,0x01,0x64] - mtmsrd %r4, 1 - -# CHECK: mfspr 4, 272 # encoding: [0x7c,0x90,0x42,0xa6] - mfsprg %r4, 0 - -# CHECK: mfspr 4, 273 # encoding: [0x7c,0x91,0x42,0xa6] - mfsprg %r4, 1 - -# CHECK: mfspr 4, 274 # encoding: [0x7c,0x92,0x42,0xa6] - mfsprg %r4, 2 - -# CHECK: mfspr 4, 275 # encoding: [0x7c,0x93,0x42,0xa6] - mfsprg %r4, 3 - -# CHECK: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6] - mtsprg 0, %r4 - -# CHECK: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6] - mtsprg 1, %r4 - -# CHECK: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6] - mtsprg 2, %r4 - -# CHECK: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6] - mtsprg 3, %r4 - -# CHECK: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6] - mtsprg0 %r4 - -# CHECK: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6] - mtsprg1 %r4 - -# CHECK: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6] - mtsprg2 %r4 - -# CHECK: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6] - mtsprg3 %r4 - -# CHECK: mtspr 280, 4 # encoding: [0x7c,0x98,0x43,0xa6] - mtasr %r4 - -# CHECK: mfspr 4, 22 # encoding: [0x7c,0x96,0x02,0xa6] - mfdec %r4 - -# CHECK: mtspr 22, 4 # encoding: [0x7c,0x96,0x03,0xa6] - mtdec %r4 - -# CHECK: mfspr 4, 287 # encoding: [0x7c,0x9f,0x42,0xa6] - mfpvr %r4 - -# CHECK: mfspr 4, 25 # encoding: [0x7c,0x99,0x02,0xa6] - mfsdr1 %r4 - -# CHECK: mtspr 25, 4 # encoding: [0x7c,0x99,0x03,0xa6] - mtsdr1 %r4 - -# CHECK: mfspr 4, 26 # encoding: [0x7c,0x9a,0x02,0xa6] - mfsrr0 %r4 - -# CHECK: mtspr 26, 4 # encoding: [0x7c,0x9a,0x03,0xa6] - mtsrr0 %r4 - -# CHECK: mfspr 4, 27 # encoding: [0x7c,0x9b,0x02,0xa6] - mfsrr1 %r4 - -# CHECK: mtspr 27, 4 # encoding: [0x7c,0x9b,0x03,0xa6] - mtsrr1 %r4 - -# CHECK: slbie 4 # encoding: [0x7c,0x00,0x23,0x64] - slbie %r4 - -# CHECK: slbmte 4, 5 # encoding: [0x7c,0x80,0x2b,0x24] - slbmte %r4, %r5 - -# CHECK: slbmfee 4, 5 # encoding: [0x7c,0x80,0x2f,0x26] - slbmfee %r4, %r5 - -# CHECK: slbia # encoding: [0x7c,0x00,0x03,0xe4] - slbia - -# CHECK: tlbsync # encoding: [0x7c,0x00,0x04,0x6c] - tlbsync - -# CHECK: tlbiel 4 # encoding: [0x7c,0x00,0x22,0x24] - tlbiel %r4 - -# CHECK: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64] - tlbie %r4, 0 - -# CHECK: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64] - tlbie %r4 +# CHECK-BE: mtmsr 4, 0 # encoding: [0x7c,0x80,0x01,0x24] +# CHECK-LE: mtmsr 4, 0 # encoding: [0x24,0x01,0x80,0x7c] + mtmsr %r4 + +# CHECK-BE: mtmsr 4, 1 # encoding: [0x7c,0x81,0x01,0x24] +# CHECK-LE: mtmsr 4, 1 # encoding: [0x24,0x01,0x81,0x7c] + mtmsr %r4, 1 + +# CHECK-BE: mfmsr 4 # encoding: [0x7c,0x80,0x00,0xa6] +# CHECK-LE: mfmsr 4 # encoding: [0xa6,0x00,0x80,0x7c] + mfmsr %r4 + +# CHECK-BE: mtmsrd 4, 0 # encoding: [0x7c,0x80,0x01,0x64] +# CHECK-LE: mtmsrd 4, 0 # encoding: [0x64,0x01,0x80,0x7c] + mtmsrd %r4 + +# CHECK-BE: mtmsrd 4, 1 # encoding: [0x7c,0x81,0x01,0x64] +# CHECK-LE: mtmsrd 4, 1 # encoding: [0x64,0x01,0x81,0x7c] + mtmsrd %r4, 1 + +# CHECK-BE: mfspr 4, 272 # encoding: [0x7c,0x90,0x42,0xa6] +# CHECK-LE: mfspr 4, 272 # encoding: [0xa6,0x42,0x90,0x7c] + mfsprg %r4, 0 + +# CHECK-BE: mfspr 4, 273 # encoding: [0x7c,0x91,0x42,0xa6] +# CHECK-LE: mfspr 4, 273 # encoding: [0xa6,0x42,0x91,0x7c] + mfsprg %r4, 1 + +# CHECK-BE: mfspr 4, 274 # encoding: [0x7c,0x92,0x42,0xa6] +# CHECK-LE: mfspr 4, 274 # encoding: [0xa6,0x42,0x92,0x7c] + mfsprg %r4, 2 + +# CHECK-BE: mfspr 4, 275 # encoding: [0x7c,0x93,0x42,0xa6] +# CHECK-LE: mfspr 4, 275 # encoding: [0xa6,0x42,0x93,0x7c] + mfsprg %r4, 3 + +# CHECK-BE: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6] +# CHECK-LE: mtspr 272, 4 # encoding: [0xa6,0x43,0x90,0x7c] + mtsprg 0, %r4 + +# CHECK-BE: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6] +# CHECK-LE: mtspr 273, 4 # encoding: [0xa6,0x43,0x91,0x7c] + mtsprg 1, %r4 + +# CHECK-BE: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6] +# CHECK-LE: mtspr 274, 4 # encoding: [0xa6,0x43,0x92,0x7c] + mtsprg 2, %r4 + +# CHECK-BE: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6] +# CHECK-LE: mtspr 275, 4 # encoding: [0xa6,0x43,0x93,0x7c] + mtsprg 3, %r4 + +# CHECK-BE: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6] +# CHECK-LE: mtspr 272, 4 # encoding: [0xa6,0x43,0x90,0x7c] + mtsprg0 %r4 + +# CHECK-BE: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6] +# CHECK-LE: mtspr 273, 4 # encoding: [0xa6,0x43,0x91,0x7c] + mtsprg1 %r4 + +# CHECK-BE: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6] +# CHECK-LE: mtspr 274, 4 # encoding: [0xa6,0x43,0x92,0x7c] + mtsprg2 %r4 + +# CHECK-BE: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6] +# CHECK-LE: mtspr 275, 4 # encoding: [0xa6,0x43,0x93,0x7c] + mtsprg3 %r4 + +# CHECK-BE: mtspr 280, 4 # encoding: [0x7c,0x98,0x43,0xa6] +# CHECK-LE: mtspr 280, 4 # encoding: [0xa6,0x43,0x98,0x7c] + mtasr %r4 + +# CHECK-BE: mfspr 4, 22 # encoding: [0x7c,0x96,0x02,0xa6] +# CHECK-LE: mfspr 4, 22 # encoding: [0xa6,0x02,0x96,0x7c] + mfdec %r4 + +# CHECK-BE: mtspr 22, 4 # encoding: [0x7c,0x96,0x03,0xa6] +# CHECK-LE: mtspr 22, 4 # encoding: [0xa6,0x03,0x96,0x7c] + mtdec %r4 + +# CHECK-BE: mfspr 4, 287 # encoding: [0x7c,0x9f,0x42,0xa6] +# CHECK-LE: mfspr 4, 287 # encoding: [0xa6,0x42,0x9f,0x7c] + mfpvr %r4 + +# CHECK-BE: mfspr 4, 25 # encoding: [0x7c,0x99,0x02,0xa6] +# CHECK-LE: mfspr 4, 25 # encoding: [0xa6,0x02,0x99,0x7c] + mfsdr1 %r4 + +# CHECK-BE: mtspr 25, 4 # encoding: [0x7c,0x99,0x03,0xa6] +# CHECK-LE: mtspr 25, 4 # encoding: [0xa6,0x03,0x99,0x7c] + mtsdr1 %r4 + +# CHECK-BE: mfspr 4, 26 # encoding: [0x7c,0x9a,0x02,0xa6] +# CHECK-LE: mfspr 4, 26 # encoding: [0xa6,0x02,0x9a,0x7c] + mfsrr0 %r4 + +# CHECK-BE: mtspr 26, 4 # encoding: [0x7c,0x9a,0x03,0xa6] +# CHECK-LE: mtspr 26, 4 # encoding: [0xa6,0x03,0x9a,0x7c] + mtsrr0 %r4 + +# CHECK-BE: mfspr 4, 27 # encoding: [0x7c,0x9b,0x02,0xa6] +# CHECK-LE: mfspr 4, 27 # encoding: [0xa6,0x02,0x9b,0x7c] + mfsrr1 %r4 + +# CHECK-BE: mtspr 27, 4 # encoding: [0x7c,0x9b,0x03,0xa6] +# CHECK-LE: mtspr 27, 4 # encoding: [0xa6,0x03,0x9b,0x7c] + mtsrr1 %r4 + +# CHECK-BE: slbie 4 # encoding: [0x7c,0x00,0x23,0x64] +# CHECK-LE: slbie 4 # encoding: [0x64,0x23,0x00,0x7c] + slbie %r4 + +# CHECK-BE: slbmte 4, 5 # encoding: [0x7c,0x80,0x2b,0x24] +# CHECK-LE: slbmte 4, 5 # encoding: [0x24,0x2b,0x80,0x7c] + slbmte %r4, %r5 + +# CHECK-BE: slbmfee 4, 5 # encoding: [0x7c,0x80,0x2f,0x26] +# CHECK-LE: slbmfee 4, 5 # encoding: [0x26,0x2f,0x80,0x7c] + slbmfee %r4, %r5 + +# CHECK-BE: slbia # encoding: [0x7c,0x00,0x03,0xe4] +# CHECK-LE: slbia # encoding: [0xe4,0x03,0x00,0x7c] + slbia + +# CHECK-BE: tlbsync # encoding: [0x7c,0x00,0x04,0x6c] +# CHECK-LE: tlbsync # encoding: [0x6c,0x04,0x00,0x7c] + tlbsync + +# CHECK-BE: tlbiel 4 # encoding: [0x7c,0x00,0x22,0x24] +# CHECK-LE: tlbiel 4 # encoding: [0x24,0x22,0x00,0x7c] + tlbiel %r4 + +# CHECK-BE: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64] +# CHECK-LE: tlbie 4,0 # encoding: [0x64,0x22,0x00,0x7c] + tlbie %r4, 0 + +# CHECK-BE: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64] +# CHECK-LE: tlbie 4,0 # encoding: [0x64,0x22,0x00,0x7c] + tlbie %r4 Index: llvm-suse/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-suse/test/MC/PowerPC/ppc64-encoding-ext.s @@ -1,2227 +1,3467 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Condition register bit symbols -# CHECK: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20] - beqlr cr0 -# CHECK: beqlr 1 # encoding: [0x4d,0x86,0x00,0x20] - beqlr cr1 -# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20] - beqlr cr2 -# CHECK: beqlr 3 # encoding: [0x4d,0x8e,0x00,0x20] - beqlr cr3 -# CHECK: beqlr 4 # encoding: [0x4d,0x92,0x00,0x20] - beqlr cr4 -# CHECK: beqlr 5 # encoding: [0x4d,0x96,0x00,0x20] - beqlr cr5 -# CHECK: beqlr 6 # encoding: [0x4d,0x9a,0x00,0x20] - beqlr cr6 -# CHECK: beqlr 7 # encoding: [0x4d,0x9e,0x00,0x20] - beqlr cr7 - -# CHECK: bclr 12, 0, 0 # encoding: [0x4d,0x80,0x00,0x20] - btlr 4*cr0+lt -# CHECK: bclr 12, 1, 0 # encoding: [0x4d,0x81,0x00,0x20] - btlr 4*cr0+gt -# CHECK: bclr 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x20] - btlr 4*cr0+eq -# CHECK: bclr 12, 3, 0 # encoding: [0x4d,0x83,0x00,0x20] - btlr 4*cr0+so -# CHECK: bclr 12, 3, 0 # encoding: [0x4d,0x83,0x00,0x20] - btlr 4*cr0+un -# CHECK: bclr 12, 4, 0 # encoding: [0x4d,0x84,0x00,0x20] - btlr 4*cr1+lt -# CHECK: bclr 12, 5, 0 # encoding: [0x4d,0x85,0x00,0x20] - btlr 4*cr1+gt -# CHECK: bclr 12, 6, 0 # encoding: [0x4d,0x86,0x00,0x20] - btlr 4*cr1+eq -# CHECK: bclr 12, 7, 0 # encoding: [0x4d,0x87,0x00,0x20] - btlr 4*cr1+so -# CHECK: bclr 12, 7, 0 # encoding: [0x4d,0x87,0x00,0x20] - btlr 4*cr1+un -# CHECK: bclr 12, 8, 0 # encoding: [0x4d,0x88,0x00,0x20] - btlr 4*cr2+lt -# CHECK: bclr 12, 9, 0 # encoding: [0x4d,0x89,0x00,0x20] - btlr 4*cr2+gt -# CHECK: bclr 12, 10, 0 # encoding: [0x4d,0x8a,0x00,0x20] - btlr 4*cr2+eq -# CHECK: bclr 12, 11, 0 # encoding: [0x4d,0x8b,0x00,0x20] - btlr 4*cr2+so -# CHECK: bclr 12, 11, 0 # encoding: [0x4d,0x8b,0x00,0x20] - btlr 4*cr2+un -# CHECK: bclr 12, 12, 0 # encoding: [0x4d,0x8c,0x00,0x20] - btlr 4*cr3+lt -# CHECK: bclr 12, 13, 0 # encoding: [0x4d,0x8d,0x00,0x20] - btlr 4*cr3+gt -# CHECK: bclr 12, 14, 0 # encoding: [0x4d,0x8e,0x00,0x20] - btlr 4*cr3+eq -# CHECK: bclr 12, 15, 0 # encoding: [0x4d,0x8f,0x00,0x20] - btlr 4*cr3+so -# CHECK: bclr 12, 15, 0 # encoding: [0x4d,0x8f,0x00,0x20] - btlr 4*cr3+un -# CHECK: bclr 12, 16, 0 # encoding: [0x4d,0x90,0x00,0x20] - btlr 4*cr4+lt -# CHECK: bclr 12, 17, 0 # encoding: [0x4d,0x91,0x00,0x20] - btlr 4*cr4+gt -# CHECK: bclr 12, 18, 0 # encoding: [0x4d,0x92,0x00,0x20] - btlr 4*cr4+eq -# CHECK: bclr 12, 19, 0 # encoding: [0x4d,0x93,0x00,0x20] - btlr 4*cr4+so -# CHECK: bclr 12, 19, 0 # encoding: [0x4d,0x93,0x00,0x20] - btlr 4*cr4+un -# CHECK: bclr 12, 20, 0 # encoding: [0x4d,0x94,0x00,0x20] - btlr 4*cr5+lt -# CHECK: bclr 12, 21, 0 # encoding: [0x4d,0x95,0x00,0x20] - btlr 4*cr5+gt -# CHECK: bclr 12, 22, 0 # encoding: [0x4d,0x96,0x00,0x20] - btlr 4*cr5+eq -# CHECK: bclr 12, 23, 0 # encoding: [0x4d,0x97,0x00,0x20] - btlr 4*cr5+so -# CHECK: bclr 12, 23, 0 # encoding: [0x4d,0x97,0x00,0x20] - btlr 4*cr5+un -# CHECK: bclr 12, 24, 0 # encoding: [0x4d,0x98,0x00,0x20] - btlr 4*cr6+lt -# CHECK: bclr 12, 25, 0 # encoding: [0x4d,0x99,0x00,0x20] - btlr 4*cr6+gt -# CHECK: bclr 12, 26, 0 # encoding: [0x4d,0x9a,0x00,0x20] - btlr 4*cr6+eq -# CHECK: bclr 12, 27, 0 # encoding: [0x4d,0x9b,0x00,0x20] - btlr 4*cr6+so -# CHECK: bclr 12, 27, 0 # encoding: [0x4d,0x9b,0x00,0x20] - btlr 4*cr6+un -# CHECK: bclr 12, 28, 0 # encoding: [0x4d,0x9c,0x00,0x20] - btlr 4*cr7+lt -# CHECK: bclr 12, 29, 0 # encoding: [0x4d,0x9d,0x00,0x20] - btlr 4*cr7+gt -# CHECK: bclr 12, 30, 0 # encoding: [0x4d,0x9e,0x00,0x20] - btlr 4*cr7+eq -# CHECK: bclr 12, 31, 0 # encoding: [0x4d,0x9f,0x00,0x20] - btlr 4*cr7+so -# CHECK: bclr 12, 31, 0 # encoding: [0x4d,0x9f,0x00,0x20] - btlr 4*cr7+un +# CHECK-BE: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20] +# CHECK-LE: beqlr 0 # encoding: [0x20,0x00,0x82,0x4d] + beqlr cr0 +# CHECK-BE: beqlr 1 # encoding: [0x4d,0x86,0x00,0x20] +# CHECK-LE: beqlr 1 # encoding: [0x20,0x00,0x86,0x4d] + beqlr cr1 +# CHECK-BE: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20] +# CHECK-LE: beqlr 2 # encoding: [0x20,0x00,0x8a,0x4d] + beqlr cr2 +# CHECK-BE: beqlr 3 # encoding: [0x4d,0x8e,0x00,0x20] +# CHECK-LE: beqlr 3 # encoding: [0x20,0x00,0x8e,0x4d] + beqlr cr3 +# CHECK-BE: beqlr 4 # encoding: [0x4d,0x92,0x00,0x20] +# CHECK-LE: beqlr 4 # encoding: [0x20,0x00,0x92,0x4d] + beqlr cr4 +# CHECK-BE: beqlr 5 # encoding: [0x4d,0x96,0x00,0x20] +# CHECK-LE: beqlr 5 # encoding: [0x20,0x00,0x96,0x4d] + beqlr cr5 +# CHECK-BE: beqlr 6 # encoding: [0x4d,0x9a,0x00,0x20] +# CHECK-LE: beqlr 6 # encoding: [0x20,0x00,0x9a,0x4d] + beqlr cr6 +# CHECK-BE: beqlr 7 # encoding: [0x4d,0x9e,0x00,0x20] +# CHECK-LE: beqlr 7 # encoding: [0x20,0x00,0x9e,0x4d] + beqlr cr7 + +# CHECK-BE: bclr 12, 0, 0 # encoding: [0x4d,0x80,0x00,0x20] +# CHECK-LE: bclr 12, 0, 0 # encoding: [0x20,0x00,0x80,0x4d] + btlr 4*cr0+lt +# CHECK-BE: bclr 12, 1, 0 # encoding: [0x4d,0x81,0x00,0x20] +# CHECK-LE: bclr 12, 1, 0 # encoding: [0x20,0x00,0x81,0x4d] + btlr 4*cr0+gt +# CHECK-BE: bclr 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x20] +# CHECK-LE: bclr 12, 2, 0 # encoding: [0x20,0x00,0x82,0x4d] + btlr 4*cr0+eq +# CHECK-BE: bclr 12, 3, 0 # encoding: [0x4d,0x83,0x00,0x20] +# CHECK-LE: bclr 12, 3, 0 # encoding: [0x20,0x00,0x83,0x4d] + btlr 4*cr0+so +# CHECK-BE: bclr 12, 3, 0 # encoding: [0x4d,0x83,0x00,0x20] +# CHECK-LE: bclr 12, 3, 0 # encoding: [0x20,0x00,0x83,0x4d] + btlr 4*cr0+un +# CHECK-BE: bclr 12, 4, 0 # encoding: [0x4d,0x84,0x00,0x20] +# CHECK-LE: bclr 12, 4, 0 # encoding: [0x20,0x00,0x84,0x4d] + btlr 4*cr1+lt +# CHECK-BE: bclr 12, 5, 0 # encoding: [0x4d,0x85,0x00,0x20] +# CHECK-LE: bclr 12, 5, 0 # encoding: [0x20,0x00,0x85,0x4d] + btlr 4*cr1+gt +# CHECK-BE: bclr 12, 6, 0 # encoding: [0x4d,0x86,0x00,0x20] +# CHECK-LE: bclr 12, 6, 0 # encoding: [0x20,0x00,0x86,0x4d] + btlr 4*cr1+eq +# CHECK-BE: bclr 12, 7, 0 # encoding: [0x4d,0x87,0x00,0x20] +# CHECK-LE: bclr 12, 7, 0 # encoding: [0x20,0x00,0x87,0x4d] + btlr 4*cr1+so +# CHECK-BE: bclr 12, 7, 0 # encoding: [0x4d,0x87,0x00,0x20] +# CHECK-LE: bclr 12, 7, 0 # encoding: [0x20,0x00,0x87,0x4d] + btlr 4*cr1+un +# CHECK-BE: bclr 12, 8, 0 # encoding: [0x4d,0x88,0x00,0x20] +# CHECK-LE: bclr 12, 8, 0 # encoding: [0x20,0x00,0x88,0x4d] + btlr 4*cr2+lt +# CHECK-BE: bclr 12, 9, 0 # encoding: [0x4d,0x89,0x00,0x20] +# CHECK-LE: bclr 12, 9, 0 # encoding: [0x20,0x00,0x89,0x4d] + btlr 4*cr2+gt +# CHECK-BE: bclr 12, 10, 0 # encoding: [0x4d,0x8a,0x00,0x20] +# CHECK-LE: bclr 12, 10, 0 # encoding: [0x20,0x00,0x8a,0x4d] + btlr 4*cr2+eq +# CHECK-BE: bclr 12, 11, 0 # encoding: [0x4d,0x8b,0x00,0x20] +# CHECK-LE: bclr 12, 11, 0 # encoding: [0x20,0x00,0x8b,0x4d] + btlr 4*cr2+so +# CHECK-BE: bclr 12, 11, 0 # encoding: [0x4d,0x8b,0x00,0x20] +# CHECK-LE: bclr 12, 11, 0 # encoding: [0x20,0x00,0x8b,0x4d] + btlr 4*cr2+un +# CHECK-BE: bclr 12, 12, 0 # encoding: [0x4d,0x8c,0x00,0x20] +# CHECK-LE: bclr 12, 12, 0 # encoding: [0x20,0x00,0x8c,0x4d] + btlr 4*cr3+lt +# CHECK-BE: bclr 12, 13, 0 # encoding: [0x4d,0x8d,0x00,0x20] +# CHECK-LE: bclr 12, 13, 0 # encoding: [0x20,0x00,0x8d,0x4d] + btlr 4*cr3+gt +# CHECK-BE: bclr 12, 14, 0 # encoding: [0x4d,0x8e,0x00,0x20] +# CHECK-LE: bclr 12, 14, 0 # encoding: [0x20,0x00,0x8e,0x4d] + btlr 4*cr3+eq +# CHECK-BE: bclr 12, 15, 0 # encoding: [0x4d,0x8f,0x00,0x20] +# CHECK-LE: bclr 12, 15, 0 # encoding: [0x20,0x00,0x8f,0x4d] + btlr 4*cr3+so +# CHECK-BE: bclr 12, 15, 0 # encoding: [0x4d,0x8f,0x00,0x20] +# CHECK-LE: bclr 12, 15, 0 # encoding: [0x20,0x00,0x8f,0x4d] + btlr 4*cr3+un +# CHECK-BE: bclr 12, 16, 0 # encoding: [0x4d,0x90,0x00,0x20] +# CHECK-LE: bclr 12, 16, 0 # encoding: [0x20,0x00,0x90,0x4d] + btlr 4*cr4+lt +# CHECK-BE: bclr 12, 17, 0 # encoding: [0x4d,0x91,0x00,0x20] +# CHECK-LE: bclr 12, 17, 0 # encoding: [0x20,0x00,0x91,0x4d] + btlr 4*cr4+gt +# CHECK-BE: bclr 12, 18, 0 # encoding: [0x4d,0x92,0x00,0x20] +# CHECK-LE: bclr 12, 18, 0 # encoding: [0x20,0x00,0x92,0x4d] + btlr 4*cr4+eq +# CHECK-BE: bclr 12, 19, 0 # encoding: [0x4d,0x93,0x00,0x20] +# CHECK-LE: bclr 12, 19, 0 # encoding: [0x20,0x00,0x93,0x4d] + btlr 4*cr4+so +# CHECK-BE: bclr 12, 19, 0 # encoding: [0x4d,0x93,0x00,0x20] +# CHECK-LE: bclr 12, 19, 0 # encoding: [0x20,0x00,0x93,0x4d] + btlr 4*cr4+un +# CHECK-BE: bclr 12, 20, 0 # encoding: [0x4d,0x94,0x00,0x20] +# CHECK-LE: bclr 12, 20, 0 # encoding: [0x20,0x00,0x94,0x4d] + btlr 4*cr5+lt +# CHECK-BE: bclr 12, 21, 0 # encoding: [0x4d,0x95,0x00,0x20] +# CHECK-LE: bclr 12, 21, 0 # encoding: [0x20,0x00,0x95,0x4d] + btlr 4*cr5+gt +# CHECK-BE: bclr 12, 22, 0 # encoding: [0x4d,0x96,0x00,0x20] +# CHECK-LE: bclr 12, 22, 0 # encoding: [0x20,0x00,0x96,0x4d] + btlr 4*cr5+eq +# CHECK-BE: bclr 12, 23, 0 # encoding: [0x4d,0x97,0x00,0x20] +# CHECK-LE: bclr 12, 23, 0 # encoding: [0x20,0x00,0x97,0x4d] + btlr 4*cr5+so +# CHECK-BE: bclr 12, 23, 0 # encoding: [0x4d,0x97,0x00,0x20] +# CHECK-LE: bclr 12, 23, 0 # encoding: [0x20,0x00,0x97,0x4d] + btlr 4*cr5+un +# CHECK-BE: bclr 12, 24, 0 # encoding: [0x4d,0x98,0x00,0x20] +# CHECK-LE: bclr 12, 24, 0 # encoding: [0x20,0x00,0x98,0x4d] + btlr 4*cr6+lt +# CHECK-BE: bclr 12, 25, 0 # encoding: [0x4d,0x99,0x00,0x20] +# CHECK-LE: bclr 12, 25, 0 # encoding: [0x20,0x00,0x99,0x4d] + btlr 4*cr6+gt +# CHECK-BE: bclr 12, 26, 0 # encoding: [0x4d,0x9a,0x00,0x20] +# CHECK-LE: bclr 12, 26, 0 # encoding: [0x20,0x00,0x9a,0x4d] + btlr 4*cr6+eq +# CHECK-BE: bclr 12, 27, 0 # encoding: [0x4d,0x9b,0x00,0x20] +# CHECK-LE: bclr 12, 27, 0 # encoding: [0x20,0x00,0x9b,0x4d] + btlr 4*cr6+so +# CHECK-BE: bclr 12, 27, 0 # encoding: [0x4d,0x9b,0x00,0x20] +# CHECK-LE: bclr 12, 27, 0 # encoding: [0x20,0x00,0x9b,0x4d] + btlr 4*cr6+un +# CHECK-BE: bclr 12, 28, 0 # encoding: [0x4d,0x9c,0x00,0x20] +# CHECK-LE: bclr 12, 28, 0 # encoding: [0x20,0x00,0x9c,0x4d] + btlr 4*cr7+lt +# CHECK-BE: bclr 12, 29, 0 # encoding: [0x4d,0x9d,0x00,0x20] +# CHECK-LE: bclr 12, 29, 0 # encoding: [0x20,0x00,0x9d,0x4d] + btlr 4*cr7+gt +# CHECK-BE: bclr 12, 30, 0 # encoding: [0x4d,0x9e,0x00,0x20] +# CHECK-LE: bclr 12, 30, 0 # encoding: [0x20,0x00,0x9e,0x4d] + btlr 4*cr7+eq +# CHECK-BE: bclr 12, 31, 0 # encoding: [0x4d,0x9f,0x00,0x20] +# CHECK-LE: bclr 12, 31, 0 # encoding: [0x20,0x00,0x9f,0x4d] + btlr 4*cr7+so +# CHECK-BE: bclr 12, 31, 0 # encoding: [0x4d,0x9f,0x00,0x20] +# CHECK-LE: bclr 12, 31, 0 # encoding: [0x20,0x00,0x9f,0x4d] + btlr 4*cr7+un # Branch mnemonics -# CHECK: blr # encoding: [0x4e,0x80,0x00,0x20] - blr -# CHECK: bctr # encoding: [0x4e,0x80,0x04,0x20] - bctr -# CHECK: blrl # encoding: [0x4e,0x80,0x00,0x21] - blrl -# CHECK: bctrl # encoding: [0x4e,0x80,0x04,0x21] - bctrl - -# CHECK: bc 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bt 2, target -# CHECK: bca 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bta 2, target -# CHECK: bclr 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x20] - btlr 2 -# CHECK: bcctr 12, 2, 0 # encoding: [0x4d,0x82,0x04,0x20] - btctr 2 -# CHECK: bcl 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - btl 2, target -# CHECK: bcla 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - btla 2, target -# CHECK: bclrl 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x21] - btlrl 2 -# CHECK: bcctrl 12, 2, 0 # encoding: [0x4d,0x82,0x04,0x21] - btctrl 2 - -# CHECK: bc 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bt+ 2, target -# CHECK: bca 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bta+ 2, target -# CHECK: bclr 15, 2, 0 # encoding: [0x4d,0xe2,0x00,0x20] - btlr+ 2 -# CHECK: bcctr 15, 2, 0 # encoding: [0x4d,0xe2,0x04,0x20] - btctr+ 2 -# CHECK: bcl 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - btl+ 2, target -# CHECK: bcla 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - btla+ 2, target -# CHECK: bclrl 15, 2, 0 # encoding: [0x4d,0xe2,0x00,0x21] - btlrl+ 2 -# CHECK: bcctrl 15, 2, 0 # encoding: [0x4d,0xe2,0x04,0x21] - btctrl+ 2 - -# CHECK: bc 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bt- 2, target -# CHECK: bca 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bta- 2, target -# CHECK: bclr 14, 2, 0 # encoding: [0x4d,0xc2,0x00,0x20] - btlr- 2 -# CHECK: bcctr 14, 2, 0 # encoding: [0x4d,0xc2,0x04,0x20] - btctr- 2 -# CHECK: bcl 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - btl- 2, target -# CHECK: bcla 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - btla- 2, target -# CHECK: bclrl 14, 2, 0 # encoding: [0x4d,0xc2,0x00,0x21] - btlrl- 2 -# CHECK: bcctrl 14, 2, 0 # encoding: [0x4d,0xc2,0x04,0x21] - btctrl- 2 - -# CHECK: bc 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bf 2, target -# CHECK: bca 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bfa 2, target -# CHECK: bclr 4, 2, 0 # encoding: [0x4c,0x82,0x00,0x20] - bflr 2 -# CHECK: bcctr 4, 2, 0 # encoding: [0x4c,0x82,0x04,0x20] - bfctr 2 -# CHECK: bcl 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bfl 2, target -# CHECK: bcla 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bfla 2, target -# CHECK: bclrl 4, 2, 0 # encoding: [0x4c,0x82,0x00,0x21] - bflrl 2 -# CHECK: bcctrl 4, 2, 0 # encoding: [0x4c,0x82,0x04,0x21] - bfctrl 2 - -# CHECK: bc 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bf+ 2, target -# CHECK: bca 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bfa+ 2, target -# CHECK: bclr 7, 2, 0 # encoding: [0x4c,0xe2,0x00,0x20] - bflr+ 2 -# CHECK: bcctr 7, 2, 0 # encoding: [0x4c,0xe2,0x04,0x20] - bfctr+ 2 -# CHECK: bcl 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bfl+ 2, target -# CHECK: bcla 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bfla+ 2, target -# CHECK: bclrl 7, 2, 0 # encoding: [0x4c,0xe2,0x00,0x21] - bflrl+ 2 -# CHECK: bcctrl 7, 2, 0 # encoding: [0x4c,0xe2,0x04,0x21] - bfctrl+ 2 - -# CHECK: bc 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bf- 2, target -# CHECK: bca 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bfa- 2, target -# CHECK: bclr 6, 2, 0 # encoding: [0x4c,0xc2,0x00,0x20] - bflr- 2 -# CHECK: bcctr 6, 2, 0 # encoding: [0x4c,0xc2,0x04,0x20] - bfctr- 2 -# CHECK: bcl 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bfl- 2, target -# CHECK: bcla 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bfla- 2, target -# CHECK: bclrl 6, 2, 0 # encoding: [0x4c,0xc2,0x00,0x21] - bflrl- 2 -# CHECK: bcctrl 6, 2, 0 # encoding: [0x4c,0xc2,0x04,0x21] - bfctrl- 2 - -# CHECK: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnz target -# CHECK: bdnza target # encoding: [0x42,0x00,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnza target -# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20] - bdnzlr -# CHECK: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnzl target -# CHECK: bdnzla target # encoding: [0x42,0x00,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnzla target -# CHECK: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21] - bdnzlrl - -# CHECK: bdnz+ target # encoding: [0x43,0x20,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnz+ target -# CHECK: bdnza+ target # encoding: [0x43,0x20,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnza+ target -# CHECK: bdnzlr+ # encoding: [0x4f,0x20,0x00,0x20] - bdnzlr+ -# CHECK: bdnzl+ target # encoding: [0x43,0x20,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnzl+ target -# CHECK: bdnzla+ target # encoding: [0x43,0x20,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnzla+ target -# CHECK: bdnzlrl+ # encoding: [0x4f,0x20,0x00,0x21] - bdnzlrl+ - -# CHECK: bdnz- target # encoding: [0x43,0x00,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnz- target -# CHECK: bdnza- target # encoding: [0x43,0x00,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnza- target -# CHECK: bdnzlr- # encoding: [0x4f,0x00,0x00,0x20] - bdnzlr- -# CHECK: bdnzl- target # encoding: [0x43,0x00,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnzl- target -# CHECK: bdnzla- target # encoding: [0x43,0x00,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnzla- target -# CHECK: bdnzlrl- # encoding: [0x4f,0x00,0x00,0x21] - bdnzlrl- - -# CHECK: bc 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnzt 2, target -# CHECK: bca 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnzta 2, target -# CHECK: bclr 8, 2, 0 # encoding: [0x4d,0x02,0x00,0x20] - bdnztlr 2 -# CHECK: bcl 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnztl 2, target -# CHECK: bcla 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnztla 2, target -# CHECK: bclrl 8, 2, 0 # encoding: [0x4d,0x02,0x00,0x21] - bdnztlrl 2 - -# CHECK: bc 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnzf 2, target -# CHECK: bca 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnzfa 2, target -# CHECK: bclr 0, 2, 0 # encoding: [0x4c,0x02,0x00,0x20] - bdnzflr 2 -# CHECK: bcl 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdnzfl 2, target -# CHECK: bcla 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdnzfla 2, target -# CHECK: bclrl 0, 2, 0 # encoding: [0x4c,0x02,0x00,0x21] - bdnzflrl 2 - -# CHECK: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdz target -# CHECK: bdza target # encoding: [0x42,0x40,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdza target -# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20] - bdzlr -# CHECK: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdzl target -# CHECK: bdzla target # encoding: [0x42,0x40,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdzla target -# CHECK: bdzlrl # encoding: [0x4e,0x40,0x00,0x21] - bdzlrl - -# CHECK: bdz+ target # encoding: [0x43,0x60,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdz+ target -# CHECK: bdza+ target # encoding: [0x43,0x60,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdza+ target -# CHECK: bdzlr+ # encoding: [0x4f,0x60,0x00,0x20] - bdzlr+ -# CHECK: bdzl+ target # encoding: [0x43,0x60,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdzl+ target -# CHECK: bdzla+ target # encoding: [0x43,0x60,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdzla+ target -# CHECK: bdzlrl+ # encoding: [0x4f,0x60,0x00,0x21] - bdzlrl+ - -# CHECK: bdz- target # encoding: [0x43,0x40,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdz- target -# CHECK: bdza- target # encoding: [0x43,0x40,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdza- target -# CHECK: bdzlr- # encoding: [0x4f,0x40,0x00,0x20] - bdzlr- -# CHECK: bdzl- target # encoding: [0x43,0x40,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdzl- target -# CHECK: bdzla- target # encoding: [0x43,0x40,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdzla- target -# CHECK: bdzlrl- # encoding: [0x4f,0x40,0x00,0x21] - bdzlrl- - -# CHECK: bc 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdzt 2, target -# CHECK: bca 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdzta 2, target -# CHECK: bclr 10, 2, 0 # encoding: [0x4d,0x42,0x00,0x20] - bdztlr 2 -# CHECK: bcl 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdztl 2, target -# CHECK: bcla 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdztla 2, target -# CHECK: bclrl 10, 2, 0 # encoding: [0x4d,0x42,0x00,0x21] - bdztlrl 2 - -# CHECK: bc 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdzf 2, target -# CHECK: bca 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdzfa 2, target -# CHECK: bclr 2, 2, 0 # encoding: [0x4c,0x42,0x00,0x20] - bdzflr 2 -# CHECK: bcl 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bdzfl 2, target -# CHECK: bcla 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bdzfla 2, target -# CHECK: bclrl 2, 2, 0 # encoding: [0x4c,0x42,0x00,0x21] - bdzflrl 2 - -# CHECK: blt 2, target # encoding: [0x41,0x88,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blt 2, target -# CHECK: blt 0, target # encoding: [0x41,0x80,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blt target -# CHECK: blta 2, target # encoding: [0x41,0x88,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blta 2, target -# CHECK: blta 0, target # encoding: [0x41,0x80,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blta target -# CHECK: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20] - bltlr 2 -# CHECK: bltlr 0 # encoding: [0x4d,0x80,0x00,0x20] - bltlr -# CHECK: bltctr 2 # encoding: [0x4d,0x88,0x04,0x20] - bltctr 2 -# CHECK: bltctr 0 # encoding: [0x4d,0x80,0x04,0x20] - bltctr -# CHECK: bltl 2, target # encoding: [0x41,0x88,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bltl 2, target -# CHECK: bltl 0, target # encoding: [0x41,0x80,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bltl target -# CHECK: bltla 2, target # encoding: [0x41,0x88,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bltla 2, target -# CHECK: bltla 0, target # encoding: [0x41,0x80,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bltla target -# CHECK: bltlrl 2 # encoding: [0x4d,0x88,0x00,0x21] - bltlrl 2 -# CHECK: bltlrl 0 # encoding: [0x4d,0x80,0x00,0x21] - bltlrl -# CHECK: bltctrl 2 # encoding: [0x4d,0x88,0x04,0x21] - bltctrl 2 -# CHECK: bltctrl 0 # encoding: [0x4d,0x80,0x04,0x21] - bltctrl - -# CHECK: blt+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blt+ 2, target -# CHECK: blt+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blt+ target -# CHECK: blta+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blta+ 2, target -# CHECK: blta+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blta+ target -# CHECK: bltlr+ 2 # encoding: [0x4d,0xe8,0x00,0x20] - bltlr+ 2 -# CHECK: bltlr+ 0 # encoding: [0x4d,0xe0,0x00,0x20] - bltlr+ -# CHECK: bltctr+ 2 # encoding: [0x4d,0xe8,0x04,0x20] - bltctr+ 2 -# CHECK: bltctr+ 0 # encoding: [0x4d,0xe0,0x04,0x20] - bltctr+ -# CHECK: bltl+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bltl+ 2, target -# CHECK: bltl+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bltl+ target -# CHECK: bltla+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bltla+ 2, target -# CHECK: bltla+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bltla+ target -# CHECK: bltlrl+ 2 # encoding: [0x4d,0xe8,0x00,0x21] - bltlrl+ 2 -# CHECK: bltlrl+ 0 # encoding: [0x4d,0xe0,0x00,0x21] - bltlrl+ -# CHECK: bltctrl+ 2 # encoding: [0x4d,0xe8,0x04,0x21] - bltctrl+ 2 -# CHECK: bltctrl+ 0 # encoding: [0x4d,0xe0,0x04,0x21] - bltctrl+ - -# CHECK: blt- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blt- 2, target -# CHECK: blt- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blt- target -# CHECK: blta- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blta- 2, target -# CHECK: blta- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blta- target -# CHECK: bltlr- 2 # encoding: [0x4d,0xc8,0x00,0x20] - bltlr- 2 -# CHECK: bltlr- 0 # encoding: [0x4d,0xc0,0x00,0x20] - bltlr- -# CHECK: bltctr- 2 # encoding: [0x4d,0xc8,0x04,0x20] - bltctr- 2 -# CHECK: bltctr- 0 # encoding: [0x4d,0xc0,0x04,0x20] - bltctr- -# CHECK: bltl- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bltl- 2, target -# CHECK: bltl- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bltl- target -# CHECK: bltla- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bltla- 2, target -# CHECK: bltla- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bltla- target -# CHECK: bltlrl- 2 # encoding: [0x4d,0xc8,0x00,0x21] - bltlrl- 2 -# CHECK: bltlrl- 0 # encoding: [0x4d,0xc0,0x00,0x21] - bltlrl- -# CHECK: bltctrl- 2 # encoding: [0x4d,0xc8,0x04,0x21] - bltctrl- 2 -# CHECK: bltctrl- 0 # encoding: [0x4d,0xc0,0x04,0x21] - bltctrl- - -# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - ble 2, target -# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - ble target -# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blea 2, target -# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blea target -# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20] - blelr 2 -# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20] - blelr -# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20] - blectr 2 -# CHECK: blectr 0 # encoding: [0x4c,0x81,0x04,0x20] - blectr -# CHECK: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blel 2, target -# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blel target -# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blela 2, target -# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blela target -# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21] - blelrl 2 -# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21] - blelrl -# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21] - blectrl 2 -# CHECK: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21] - blectrl - -# CHECK: ble+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - ble+ 2, target -# CHECK: ble+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - ble+ target -# CHECK: blea+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blea+ 2, target -# CHECK: blea+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blea+ target -# CHECK: blelr+ 2 # encoding: [0x4c,0xe9,0x00,0x20] - blelr+ 2 -# CHECK: blelr+ 0 # encoding: [0x4c,0xe1,0x00,0x20] - blelr+ -# CHECK: blectr+ 2 # encoding: [0x4c,0xe9,0x04,0x20] - blectr+ 2 -# CHECK: blectr+ 0 # encoding: [0x4c,0xe1,0x04,0x20] - blectr+ -# CHECK: blel+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blel+ 2, target -# CHECK: blel+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blel+ target -# CHECK: blela+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blela+ 2, target -# CHECK: blela+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blela+ target -# CHECK: blelrl+ 2 # encoding: [0x4c,0xe9,0x00,0x21] - blelrl+ 2 -# CHECK: blelrl+ 0 # encoding: [0x4c,0xe1,0x00,0x21] - blelrl+ -# CHECK: blectrl+ 2 # encoding: [0x4c,0xe9,0x04,0x21] - blectrl+ 2 -# CHECK: blectrl+ 0 # encoding: [0x4c,0xe1,0x04,0x21] - blectrl+ - -# CHECK: ble- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - ble- 2, target -# CHECK: ble- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - ble- target -# CHECK: blea- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blea- 2, target -# CHECK: blea- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blea- target -# CHECK: blelr- 2 # encoding: [0x4c,0xc9,0x00,0x20] - blelr- 2 -# CHECK: blelr- 0 # encoding: [0x4c,0xc1,0x00,0x20] - blelr- -# CHECK: blectr- 2 # encoding: [0x4c,0xc9,0x04,0x20] - blectr- 2 -# CHECK: blectr- 0 # encoding: [0x4c,0xc1,0x04,0x20] - blectr- -# CHECK: blel- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blel- 2, target -# CHECK: blel- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - blel- target -# CHECK: blela- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blela- 2, target -# CHECK: blela- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - blela- target -# CHECK: blelrl- 2 # encoding: [0x4c,0xc9,0x00,0x21] - blelrl- 2 -# CHECK: blelrl- 0 # encoding: [0x4c,0xc1,0x00,0x21] - blelrl- -# CHECK: blectrl- 2 # encoding: [0x4c,0xc9,0x04,0x21] - blectrl- 2 -# CHECK: blectrl- 0 # encoding: [0x4c,0xc1,0x04,0x21] - blectrl- - -# CHECK: beq 2, target # encoding: [0x41,0x8a,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beq 2, target -# CHECK: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beq target -# CHECK: beqa 2, target # encoding: [0x41,0x8a,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqa 2, target -# CHECK: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqa target -# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20] - beqlr 2 -# CHECK: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20] - beqlr -# CHECK: beqctr 2 # encoding: [0x4d,0x8a,0x04,0x20] - beqctr 2 -# CHECK: beqctr 0 # encoding: [0x4d,0x82,0x04,0x20] - beqctr -# CHECK: beql 2, target # encoding: [0x41,0x8a,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beql 2, target -# CHECK: beql 0, target # encoding: [0x41,0x82,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beql target -# CHECK: beqla 2, target # encoding: [0x41,0x8a,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqla 2, target -# CHECK: beqla 0, target # encoding: [0x41,0x82,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqla target -# CHECK: beqlrl 2 # encoding: [0x4d,0x8a,0x00,0x21] - beqlrl 2 -# CHECK: beqlrl 0 # encoding: [0x4d,0x82,0x00,0x21] - beqlrl -# CHECK: beqctrl 2 # encoding: [0x4d,0x8a,0x04,0x21] - beqctrl 2 -# CHECK: beqctrl 0 # encoding: [0x4d,0x82,0x04,0x21] - beqctrl - -# CHECK: beq+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beq+ 2, target -# CHECK: beq+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beq+ target -# CHECK: beqa+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqa+ 2, target -# CHECK: beqa+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqa+ target -# CHECK: beqlr+ 2 # encoding: [0x4d,0xea,0x00,0x20] - beqlr+ 2 -# CHECK: beqlr+ 0 # encoding: [0x4d,0xe2,0x00,0x20] - beqlr+ -# CHECK: beqctr+ 2 # encoding: [0x4d,0xea,0x04,0x20] - beqctr+ 2 -# CHECK: beqctr+ 0 # encoding: [0x4d,0xe2,0x04,0x20] - beqctr+ -# CHECK: beql+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beql+ 2, target -# CHECK: beql+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beql+ target -# CHECK: beqla+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqla+ 2, target -# CHECK: beqla+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqla+ target -# CHECK: beqlrl+ 2 # encoding: [0x4d,0xea,0x00,0x21] - beqlrl+ 2 -# CHECK: beqlrl+ 0 # encoding: [0x4d,0xe2,0x00,0x21] - beqlrl+ -# CHECK: beqctrl+ 2 # encoding: [0x4d,0xea,0x04,0x21] - beqctrl+ 2 -# CHECK: beqctrl+ 0 # encoding: [0x4d,0xe2,0x04,0x21] - beqctrl+ - -# CHECK: beq- 2, target # encoding: [0x41,0xca,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beq- 2, target -# CHECK: beq- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beq- target -# CHECK: beqa- 2, target # encoding: [0x41,0xca,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqa- 2, target -# CHECK: beqa- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqa- target -# CHECK: beqlr- 2 # encoding: [0x4d,0xca,0x00,0x20] - beqlr- 2 -# CHECK: beqlr- 0 # encoding: [0x4d,0xc2,0x00,0x20] - beqlr- -# CHECK: beqctr- 2 # encoding: [0x4d,0xca,0x04,0x20] - beqctr- 2 -# CHECK: beqctr- 0 # encoding: [0x4d,0xc2,0x04,0x20] - beqctr- -# CHECK: beql- 2, target # encoding: [0x41,0xca,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beql- 2, target -# CHECK: beql- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - beql- target -# CHECK: beqla- 2, target # encoding: [0x41,0xca,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqla- 2, target -# CHECK: beqla- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - beqla- target -# CHECK: beqlrl- 2 # encoding: [0x4d,0xca,0x00,0x21] - beqlrl- 2 -# CHECK: beqlrl- 0 # encoding: [0x4d,0xc2,0x00,0x21] - beqlrl- -# CHECK: beqctrl- 2 # encoding: [0x4d,0xca,0x04,0x21] - beqctrl- 2 -# CHECK: beqctrl- 0 # encoding: [0x4d,0xc2,0x04,0x21] - beqctrl- - -# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bge 2, target -# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bge target -# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgea 2, target -# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgea target -# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20] - bgelr 2 -# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20] - bgelr -# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20] - bgectr 2 -# CHECK: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20] - bgectr -# CHECK: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgel 2, target -# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgel target -# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgela 2, target -# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgela target -# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21] - bgelrl 2 -# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21] - bgelrl -# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21] - bgectrl 2 -# CHECK: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21] - bgectrl - -# CHECK: bge+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bge+ 2, target -# CHECK: bge+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bge+ target -# CHECK: bgea+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgea+ 2, target -# CHECK: bgea+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgea+ target -# CHECK: bgelr+ 2 # encoding: [0x4c,0xe8,0x00,0x20] - bgelr+ 2 -# CHECK: bgelr+ 0 # encoding: [0x4c,0xe0,0x00,0x20] - bgelr+ -# CHECK: bgectr+ 2 # encoding: [0x4c,0xe8,0x04,0x20] - bgectr+ 2 -# CHECK: bgectr+ 0 # encoding: [0x4c,0xe0,0x04,0x20] - bgectr+ -# CHECK: bgel+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgel+ 2, target -# CHECK: bgel+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgel+ target -# CHECK: bgela+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgela+ 2, target -# CHECK: bgela+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgela+ target -# CHECK: bgelrl+ 2 # encoding: [0x4c,0xe8,0x00,0x21] - bgelrl+ 2 -# CHECK: bgelrl+ 0 # encoding: [0x4c,0xe0,0x00,0x21] - bgelrl+ -# CHECK: bgectrl+ 2 # encoding: [0x4c,0xe8,0x04,0x21] - bgectrl+ 2 -# CHECK: bgectrl+ 0 # encoding: [0x4c,0xe0,0x04,0x21] - bgectrl+ - -# CHECK: bge- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bge- 2, target -# CHECK: bge- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bge- target -# CHECK: bgea- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgea- 2, target -# CHECK: bgea- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgea- target -# CHECK: bgelr- 2 # encoding: [0x4c,0xc8,0x00,0x20] - bgelr- 2 -# CHECK: bgelr- 0 # encoding: [0x4c,0xc0,0x00,0x20] - bgelr- -# CHECK: bgectr- 2 # encoding: [0x4c,0xc8,0x04,0x20] - bgectr- 2 -# CHECK: bgectr- 0 # encoding: [0x4c,0xc0,0x04,0x20] - bgectr- -# CHECK: bgel- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgel- 2, target -# CHECK: bgel- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgel- target -# CHECK: bgela- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgela- 2, target -# CHECK: bgela- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgela- target -# CHECK: bgelrl- 2 # encoding: [0x4c,0xc8,0x00,0x21] - bgelrl- 2 -# CHECK: bgelrl- 0 # encoding: [0x4c,0xc0,0x00,0x21] - bgelrl- -# CHECK: bgectrl- 2 # encoding: [0x4c,0xc8,0x04,0x21] - bgectrl- 2 -# CHECK: bgectrl- 0 # encoding: [0x4c,0xc0,0x04,0x21] - bgectrl- - -# CHECK: bgt 2, target # encoding: [0x41,0x89,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgt 2, target -# CHECK: bgt 0, target # encoding: [0x41,0x81,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgt target -# CHECK: bgta 2, target # encoding: [0x41,0x89,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgta 2, target -# CHECK: bgta 0, target # encoding: [0x41,0x81,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgta target -# CHECK: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20] - bgtlr 2 -# CHECK: bgtlr 0 # encoding: [0x4d,0x81,0x00,0x20] - bgtlr -# CHECK: bgtctr 2 # encoding: [0x4d,0x89,0x04,0x20] - bgtctr 2 -# CHECK: bgtctr 0 # encoding: [0x4d,0x81,0x04,0x20] - bgtctr -# CHECK: bgtl 2, target # encoding: [0x41,0x89,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgtl 2, target -# CHECK: bgtl 0, target # encoding: [0x41,0x81,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgtl target -# CHECK: bgtla 2, target # encoding: [0x41,0x89,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgtla 2, target -# CHECK: bgtla 0, target # encoding: [0x41,0x81,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgtla target -# CHECK: bgtlrl 2 # encoding: [0x4d,0x89,0x00,0x21] - bgtlrl 2 -# CHECK: bgtlrl 0 # encoding: [0x4d,0x81,0x00,0x21] - bgtlrl -# CHECK: bgtctrl 2 # encoding: [0x4d,0x89,0x04,0x21] - bgtctrl 2 -# CHECK: bgtctrl 0 # encoding: [0x4d,0x81,0x04,0x21] - bgtctrl - -# CHECK: bgt+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgt+ 2, target -# CHECK: bgt+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgt+ target -# CHECK: bgta+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgta+ 2, target -# CHECK: bgta+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgta+ target -# CHECK: bgtlr+ 2 # encoding: [0x4d,0xe9,0x00,0x20] - bgtlr+ 2 -# CHECK: bgtlr+ 0 # encoding: [0x4d,0xe1,0x00,0x20] - bgtlr+ -# CHECK: bgtctr+ 2 # encoding: [0x4d,0xe9,0x04,0x20] - bgtctr+ 2 -# CHECK: bgtctr+ 0 # encoding: [0x4d,0xe1,0x04,0x20] - bgtctr+ -# CHECK: bgtl+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgtl+ 2, target -# CHECK: bgtl+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgtl+ target -# CHECK: bgtla+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgtla+ 2, target -# CHECK: bgtla+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgtla+ target -# CHECK: bgtlrl+ 2 # encoding: [0x4d,0xe9,0x00,0x21] - bgtlrl+ 2 -# CHECK: bgtlrl+ 0 # encoding: [0x4d,0xe1,0x00,0x21] - bgtlrl+ -# CHECK: bgtctrl+ 2 # encoding: [0x4d,0xe9,0x04,0x21] - bgtctrl+ 2 -# CHECK: bgtctrl+ 0 # encoding: [0x4d,0xe1,0x04,0x21] - bgtctrl+ - -# CHECK: bgt- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgt- 2, target -# CHECK: bgt- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgt- target -# CHECK: bgta- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgta- 2, target -# CHECK: bgta- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgta- target -# CHECK: bgtlr- 2 # encoding: [0x4d,0xc9,0x00,0x20] - bgtlr- 2 -# CHECK: bgtlr- 0 # encoding: [0x4d,0xc1,0x00,0x20] - bgtlr- -# CHECK: bgtctr- 2 # encoding: [0x4d,0xc9,0x04,0x20] - bgtctr- 2 -# CHECK: bgtctr- 0 # encoding: [0x4d,0xc1,0x04,0x20] - bgtctr- -# CHECK: bgtl- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgtl- 2, target -# CHECK: bgtl- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bgtl- target -# CHECK: bgtla- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgtla- 2, target -# CHECK: bgtla- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bgtla- target -# CHECK: bgtlrl- 2 # encoding: [0x4d,0xc9,0x00,0x21] - bgtlrl- 2 -# CHECK: bgtlrl- 0 # encoding: [0x4d,0xc1,0x00,0x21] - bgtlrl- -# CHECK: bgtctrl- 2 # encoding: [0x4d,0xc9,0x04,0x21] - bgtctrl- 2 -# CHECK: bgtctrl- 0 # encoding: [0x4d,0xc1,0x04,0x21] - bgtctrl- - -# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnl 2, target -# CHECK: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnl target -# CHECK: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnla 2, target -# CHECK: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnla target -# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20] - bnllr 2 -# CHECK: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20] - bnllr -# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20] - bnlctr 2 -# CHECK: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20] - bnlctr -# CHECK: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnll 2, target -# CHECK: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnll target -# CHECK: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnlla 2, target -# CHECK: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnlla target -# CHECK: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21] - bnllrl 2 -# CHECK: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21] - bnllrl -# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21] - bnlctrl 2 -# CHECK: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21] - bnlctrl - -# CHECK: bge+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnl+ 2, target -# CHECK: bge+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnl+ target -# CHECK: bgea+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnla+ 2, target -# CHECK: bgea+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnla+ target -# CHECK: bgelr+ 2 # encoding: [0x4c,0xe8,0x00,0x20] - bnllr+ 2 -# CHECK: bgelr+ 0 # encoding: [0x4c,0xe0,0x00,0x20] - bnllr+ -# CHECK: bgectr+ 2 # encoding: [0x4c,0xe8,0x04,0x20] - bnlctr+ 2 -# CHECK: bgectr+ 0 # encoding: [0x4c,0xe0,0x04,0x20] - bnlctr+ -# CHECK: bgel+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnll+ 2, target -# CHECK: bgel+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnll+ target -# CHECK: bgela+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnlla+ 2, target -# CHECK: bgela+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnlla+ target -# CHECK: bgelrl+ 2 # encoding: [0x4c,0xe8,0x00,0x21] - bnllrl+ 2 -# CHECK: bgelrl+ 0 # encoding: [0x4c,0xe0,0x00,0x21] - bnllrl+ -# CHECK: bgectrl+ 2 # encoding: [0x4c,0xe8,0x04,0x21] - bnlctrl+ 2 -# CHECK: bgectrl+ 0 # encoding: [0x4c,0xe0,0x04,0x21] - bnlctrl+ - -# CHECK: bge- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnl- 2, target -# CHECK: bge- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnl- target -# CHECK: bgea- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnla- 2, target -# CHECK: bgea- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnla- target -# CHECK: bgelr- 2 # encoding: [0x4c,0xc8,0x00,0x20] - bnllr- 2 -# CHECK: bgelr- 0 # encoding: [0x4c,0xc0,0x00,0x20] - bnllr- -# CHECK: bgectr- 2 # encoding: [0x4c,0xc8,0x04,0x20] - bnlctr- 2 -# CHECK: bgectr- 0 # encoding: [0x4c,0xc0,0x04,0x20] - bnlctr- -# CHECK: bgel- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnll- 2, target -# CHECK: bgel- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnll- target -# CHECK: bgela- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnlla- 2, target -# CHECK: bgela- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnlla- target -# CHECK: bgelrl- 2 # encoding: [0x4c,0xc8,0x00,0x21] - bnllrl- 2 -# CHECK: bgelrl- 0 # encoding: [0x4c,0xc0,0x00,0x21] - bnllrl- -# CHECK: bgectrl- 2 # encoding: [0x4c,0xc8,0x04,0x21] - bnlctrl- 2 -# CHECK: bgectrl- 0 # encoding: [0x4c,0xc0,0x04,0x21] - bnlctrl- - -# CHECK: bne 2, target # encoding: [0x40,0x8a,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bne 2, target -# CHECK: bne 0, target # encoding: [0x40,0x82,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bne target -# CHECK: bnea 2, target # encoding: [0x40,0x8a,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnea 2, target -# CHECK: bnea 0, target # encoding: [0x40,0x82,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnea target -# CHECK: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20] - bnelr 2 -# CHECK: bnelr 0 # encoding: [0x4c,0x82,0x00,0x20] - bnelr -# CHECK: bnectr 2 # encoding: [0x4c,0x8a,0x04,0x20] - bnectr 2 -# CHECK: bnectr 0 # encoding: [0x4c,0x82,0x04,0x20] - bnectr -# CHECK: bnel 2, target # encoding: [0x40,0x8a,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnel 2, target -# CHECK: bnel 0, target # encoding: [0x40,0x82,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnel target -# CHECK: bnela 2, target # encoding: [0x40,0x8a,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnela 2, target -# CHECK: bnela 0, target # encoding: [0x40,0x82,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnela target -# CHECK: bnelrl 2 # encoding: [0x4c,0x8a,0x00,0x21] - bnelrl 2 -# CHECK: bnelrl 0 # encoding: [0x4c,0x82,0x00,0x21] - bnelrl -# CHECK: bnectrl 2 # encoding: [0x4c,0x8a,0x04,0x21] - bnectrl 2 -# CHECK: bnectrl 0 # encoding: [0x4c,0x82,0x04,0x21] - bnectrl - -# CHECK: bne+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bne+ 2, target -# CHECK: bne+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bne+ target -# CHECK: bnea+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnea+ 2, target -# CHECK: bnea+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnea+ target -# CHECK: bnelr+ 2 # encoding: [0x4c,0xea,0x00,0x20] - bnelr+ 2 -# CHECK: bnelr+ 0 # encoding: [0x4c,0xe2,0x00,0x20] - bnelr+ -# CHECK: bnectr+ 2 # encoding: [0x4c,0xea,0x04,0x20] - bnectr+ 2 -# CHECK: bnectr+ 0 # encoding: [0x4c,0xe2,0x04,0x20] - bnectr+ -# CHECK: bnel+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnel+ 2, target -# CHECK: bnel+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnel+ target -# CHECK: bnela+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnela+ 2, target -# CHECK: bnela+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnela+ target -# CHECK: bnelrl+ 2 # encoding: [0x4c,0xea,0x00,0x21] - bnelrl+ 2 -# CHECK: bnelrl+ 0 # encoding: [0x4c,0xe2,0x00,0x21] - bnelrl+ -# CHECK: bnectrl+ 2 # encoding: [0x4c,0xea,0x04,0x21] - bnectrl+ 2 -# CHECK: bnectrl+ 0 # encoding: [0x4c,0xe2,0x04,0x21] - bnectrl+ - -# CHECK: bne- 2, target # encoding: [0x40,0xca,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bne- 2, target -# CHECK: bne- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bne- target -# CHECK: bnea- 2, target # encoding: [0x40,0xca,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnea- 2, target -# CHECK: bnea- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnea- target -# CHECK: bnelr- 2 # encoding: [0x4c,0xca,0x00,0x20] - bnelr- 2 -# CHECK: bnelr- 0 # encoding: [0x4c,0xc2,0x00,0x20] - bnelr- -# CHECK: bnectr- 2 # encoding: [0x4c,0xca,0x04,0x20] - bnectr- 2 -# CHECK: bnectr- 0 # encoding: [0x4c,0xc2,0x04,0x20] - bnectr- -# CHECK: bnel- 2, target # encoding: [0x40,0xca,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnel- 2, target -# CHECK: bnel- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnel- target -# CHECK: bnela- 2, target # encoding: [0x40,0xca,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnela- 2, target -# CHECK: bnela- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnela- target -# CHECK: bnelrl- 2 # encoding: [0x4c,0xca,0x00,0x21] - bnelrl- 2 -# CHECK: bnelrl- 0 # encoding: [0x4c,0xc2,0x00,0x21] - bnelrl- -# CHECK: bnectrl- 2 # encoding: [0x4c,0xca,0x04,0x21] - bnectrl- 2 -# CHECK: bnectrl- 0 # encoding: [0x4c,0xc2,0x04,0x21] - bnectrl- - -# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bng 2, target -# CHECK: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bng target -# CHECK: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnga 2, target -# CHECK: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnga target -# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20] - bnglr 2 -# CHECK: blelr 0 # encoding: [0x4c,0x81,0x00,0x20] - bnglr -# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20] - bngctr 2 -# CHECK: blectr 0 # encoding: [0x4c,0x81,0x04,0x20] - bngctr -# CHECK: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bngl 2, target -# CHECK: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bngl target -# CHECK: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bngla 2, target -# CHECK: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bngla target -# CHECK: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21] - bnglrl 2 -# CHECK: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21] - bnglrl -# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21] - bngctrl 2 -# CHECK: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21] - bngctrl - -# CHECK: ble+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bng+ 2, target -# CHECK: ble+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bng+ target -# CHECK: blea+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnga+ 2, target -# CHECK: blea+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnga+ target -# CHECK: blelr+ 2 # encoding: [0x4c,0xe9,0x00,0x20] - bnglr+ 2 -# CHECK: blelr+ 0 # encoding: [0x4c,0xe1,0x00,0x20] - bnglr+ -# CHECK: blectr+ 2 # encoding: [0x4c,0xe9,0x04,0x20] - bngctr+ 2 -# CHECK: blectr+ 0 # encoding: [0x4c,0xe1,0x04,0x20] - bngctr+ -# CHECK: blel+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bngl+ 2, target -# CHECK: blel+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bngl+ target -# CHECK: blela+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bngla+ 2, target -# CHECK: blela+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bngla+ target -# CHECK: blelrl+ 2 # encoding: [0x4c,0xe9,0x00,0x21] - bnglrl+ 2 -# CHECK: blelrl+ 0 # encoding: [0x4c,0xe1,0x00,0x21] - bnglrl+ -# CHECK: blectrl+ 2 # encoding: [0x4c,0xe9,0x04,0x21] - bngctrl+ 2 -# CHECK: blectrl+ 0 # encoding: [0x4c,0xe1,0x04,0x21] - bngctrl+ - -# CHECK: ble- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bng- 2, target -# CHECK: ble- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bng- target -# CHECK: blea- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnga- 2, target -# CHECK: blea- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnga- target -# CHECK: blelr- 2 # encoding: [0x4c,0xc9,0x00,0x20] - bnglr- 2 -# CHECK: blelr- 0 # encoding: [0x4c,0xc1,0x00,0x20] - bnglr- -# CHECK: blectr- 2 # encoding: [0x4c,0xc9,0x04,0x20] - bngctr- 2 -# CHECK: blectr- 0 # encoding: [0x4c,0xc1,0x04,0x20] - bngctr- -# CHECK: blel- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bngl- 2, target -# CHECK: blel- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bngl- target -# CHECK: blela- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bngla- 2, target -# CHECK: blela- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bngla- target -# CHECK: blelrl- 2 # encoding: [0x4c,0xc9,0x00,0x21] - bnglrl- 2 -# CHECK: blelrl- 0 # encoding: [0x4c,0xc1,0x00,0x21] - bnglrl- -# CHECK: blectrl- 2 # encoding: [0x4c,0xc9,0x04,0x21] - bngctrl- 2 -# CHECK: blectrl- 0 # encoding: [0x4c,0xc1,0x04,0x21] - bngctrl- - -# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bso 2, target -# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bso target -# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsoa 2, target -# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsoa target -# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20] - bsolr 2 -# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20] - bsolr -# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20] - bsoctr 2 -# CHECK: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20] - bsoctr -# CHECK: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bsol 2, target -# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bsol target -# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsola 2, target -# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsola target -# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21] - bsolrl 2 -# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21] - bsolrl -# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21] - bsoctrl 2 -# CHECK: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21] - bsoctrl - -# CHECK: bun+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bso+ 2, target -# CHECK: bun+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bso+ target -# CHECK: buna+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsoa+ 2, target -# CHECK: buna+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsoa+ target -# CHECK: bunlr+ 2 # encoding: [0x4d,0xeb,0x00,0x20] - bsolr+ 2 -# CHECK: bunlr+ 0 # encoding: [0x4d,0xe3,0x00,0x20] - bsolr+ -# CHECK: bunctr+ 2 # encoding: [0x4d,0xeb,0x04,0x20] - bsoctr+ 2 -# CHECK: bunctr+ 0 # encoding: [0x4d,0xe3,0x04,0x20] - bsoctr+ -# CHECK: bunl+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bsol+ 2, target -# CHECK: bunl+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bsol+ target -# CHECK: bunla+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsola+ 2, target -# CHECK: bunla+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsola+ target -# CHECK: bunlrl+ 2 # encoding: [0x4d,0xeb,0x00,0x21] - bsolrl+ 2 -# CHECK: bunlrl+ 0 # encoding: [0x4d,0xe3,0x00,0x21] - bsolrl+ -# CHECK: bunctrl+ 2 # encoding: [0x4d,0xeb,0x04,0x21] - bsoctrl+ 2 -# CHECK: bunctrl+ 0 # encoding: [0x4d,0xe3,0x04,0x21] - bsoctrl+ - -# CHECK: bun- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bso- 2, target -# CHECK: bun- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bso- target -# CHECK: buna- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsoa- 2, target -# CHECK: buna- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsoa- target -# CHECK: bunlr- 2 # encoding: [0x4d,0xcb,0x00,0x20] - bsolr- 2 -# CHECK: bunlr- 0 # encoding: [0x4d,0xc3,0x00,0x20] - bsolr- -# CHECK: bunctr- 2 # encoding: [0x4d,0xcb,0x04,0x20] - bsoctr- 2 -# CHECK: bunctr- 0 # encoding: [0x4d,0xc3,0x04,0x20] - bsoctr- -# CHECK: bunl- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bsol- 2, target -# CHECK: bunl- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bsol- target -# CHECK: bunla- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsola- 2, target -# CHECK: bunla- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bsola- target -# CHECK: bunlrl- 2 # encoding: [0x4d,0xcb,0x00,0x21] - bsolrl- 2 -# CHECK: bunlrl- 0 # encoding: [0x4d,0xc3,0x00,0x21] - bsolrl- -# CHECK: bunctrl- 2 # encoding: [0x4d,0xcb,0x04,0x21] - bsoctrl- 2 -# CHECK: bunctrl- 0 # encoding: [0x4d,0xc3,0x04,0x21] - bsoctrl- - -# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bns 2, target -# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bns target -# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsa 2, target -# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsa target -# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20] - bnslr 2 -# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20] - bnslr -# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20] - bnsctr 2 -# CHECK: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20] - bnsctr -# CHECK: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnsl 2, target -# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnsl target -# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsla 2, target -# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsla target -# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21] - bnslrl 2 -# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21] - bnslrl -# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21] - bnsctrl 2 -# CHECK: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21] - bnsctrl - -# CHECK: bnu+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bns+ 2, target -# CHECK: bnu+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bns+ target -# CHECK: bnua+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsa+ 2, target -# CHECK: bnua+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsa+ target -# CHECK: bnulr+ 2 # encoding: [0x4c,0xeb,0x00,0x20] - bnslr+ 2 -# CHECK: bnulr+ 0 # encoding: [0x4c,0xe3,0x00,0x20] - bnslr+ -# CHECK: bnuctr+ 2 # encoding: [0x4c,0xeb,0x04,0x20] - bnsctr+ 2 -# CHECK: bnuctr+ 0 # encoding: [0x4c,0xe3,0x04,0x20] - bnsctr+ -# CHECK: bnul+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnsl+ 2, target -# CHECK: bnul+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnsl+ target -# CHECK: bnula+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsla+ 2, target -# CHECK: bnula+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsla+ target -# CHECK: bnulrl+ 2 # encoding: [0x4c,0xeb,0x00,0x21] - bnslrl+ 2 -# CHECK: bnulrl+ 0 # encoding: [0x4c,0xe3,0x00,0x21] - bnslrl+ -# CHECK: bnuctrl+ 2 # encoding: [0x4c,0xeb,0x04,0x21] - bnsctrl+ 2 -# CHECK: bnuctrl+ 0 # encoding: [0x4c,0xe3,0x04,0x21] - bnsctrl+ - -# CHECK: bnu- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bns- 2, target -# CHECK: bnu- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bns- target -# CHECK: bnua- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsa- 2, target -# CHECK: bnua- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsa- target -# CHECK: bnulr- 2 # encoding: [0x4c,0xcb,0x00,0x20] - bnslr- 2 -# CHECK: bnulr- 0 # encoding: [0x4c,0xc3,0x00,0x20] - bnslr- -# CHECK: bnuctr- 2 # encoding: [0x4c,0xcb,0x04,0x20] - bnsctr- 2 -# CHECK: bnuctr- 0 # encoding: [0x4c,0xc3,0x04,0x20] - bnsctr- -# CHECK: bnul- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnsl- 2, target -# CHECK: bnul- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnsl- target -# CHECK: bnula- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsla- 2, target -# CHECK: bnula- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnsla- target -# CHECK: bnulrl- 2 # encoding: [0x4c,0xcb,0x00,0x21] - bnslrl- 2 -# CHECK: bnulrl- 0 # encoding: [0x4c,0xc3,0x00,0x21] - bnslrl- -# CHECK: bnuctrl- 2 # encoding: [0x4c,0xcb,0x04,0x21] - bnsctrl- 2 -# CHECK: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21] - bnsctrl- - -# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bun 2, target -# CHECK: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bun target -# CHECK: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - buna 2, target -# CHECK: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - buna target -# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20] - bunlr 2 -# CHECK: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20] - bunlr -# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20] - bunctr 2 -# CHECK: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20] - bunctr -# CHECK: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bunl 2, target -# CHECK: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bunl target -# CHECK: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bunla 2, target -# CHECK: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bunla target -# CHECK: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21] - bunlrl 2 -# CHECK: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21] - bunlrl -# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21] - bunctrl 2 -# CHECK: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21] - bunctrl - -# CHECK: bun+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bun+ 2, target -# CHECK: bun+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bun+ target -# CHECK: buna+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - buna+ 2, target -# CHECK: buna+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - buna+ target -# CHECK: bunlr+ 2 # encoding: [0x4d,0xeb,0x00,0x20] - bunlr+ 2 -# CHECK: bunlr+ 0 # encoding: [0x4d,0xe3,0x00,0x20] - bunlr+ -# CHECK: bunctr+ 2 # encoding: [0x4d,0xeb,0x04,0x20] - bunctr+ 2 -# CHECK: bunctr+ 0 # encoding: [0x4d,0xe3,0x04,0x20] - bunctr+ -# CHECK: bunl+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bunl+ 2, target -# CHECK: bunl+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bunl+ target -# CHECK: bunla+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bunla+ 2, target -# CHECK: bunla+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bunla+ target -# CHECK: bunlrl+ 2 # encoding: [0x4d,0xeb,0x00,0x21] - bunlrl+ 2 -# CHECK: bunlrl+ 0 # encoding: [0x4d,0xe3,0x00,0x21] - bunlrl+ -# CHECK: bunctrl+ 2 # encoding: [0x4d,0xeb,0x04,0x21] - bunctrl+ 2 -# CHECK: bunctrl+ 0 # encoding: [0x4d,0xe3,0x04,0x21] - bunctrl+ - -# CHECK: bun- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bun- 2, target -# CHECK: bun- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bun- target -# CHECK: buna- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - buna- 2, target -# CHECK: buna- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - buna- target -# CHECK: bunlr- 2 # encoding: [0x4d,0xcb,0x00,0x20] - bunlr- 2 -# CHECK: bunlr- 0 # encoding: [0x4d,0xc3,0x00,0x20] - bunlr- -# CHECK: bunctr- 2 # encoding: [0x4d,0xcb,0x04,0x20] - bunctr- 2 -# CHECK: bunctr- 0 # encoding: [0x4d,0xc3,0x04,0x20] - bunctr- -# CHECK: bunl- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bunl- 2, target -# CHECK: bunl- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bunl- target -# CHECK: bunla- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bunla- 2, target -# CHECK: bunla- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bunla- target -# CHECK: bunlrl- 2 # encoding: [0x4d,0xcb,0x00,0x21] - bunlrl- 2 -# CHECK: bunlrl- 0 # encoding: [0x4d,0xc3,0x00,0x21] - bunlrl- -# CHECK: bunctrl- 2 # encoding: [0x4d,0xcb,0x04,0x21] - bunctrl- 2 -# CHECK: bunctrl- 0 # encoding: [0x4d,0xc3,0x04,0x21] - bunctrl- - -# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnu 2, target -# CHECK: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnu target -# CHECK: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnua 2, target -# CHECK: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnua target -# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20] - bnulr 2 -# CHECK: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20] - bnulr -# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20] - bnuctr 2 -# CHECK: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20] - bnuctr -# CHECK: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnul 2, target -# CHECK: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnul target -# CHECK: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnula 2, target -# CHECK: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnula target -# CHECK: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21] - bnulrl 2 -# CHECK: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21] - bnulrl -# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21] - bnuctrl 2 -# CHECK: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21] - bnuctrl - -# CHECK: bnu+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnu+ 2, target -# CHECK: bnu+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnu+ target -# CHECK: bnua+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnua+ 2, target -# CHECK: bnua+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnua+ target -# CHECK: bnulr+ 2 # encoding: [0x4c,0xeb,0x00,0x20] - bnulr+ 2 -# CHECK: bnulr+ 0 # encoding: [0x4c,0xe3,0x00,0x20] - bnulr+ -# CHECK: bnuctr+ 2 # encoding: [0x4c,0xeb,0x04,0x20] - bnuctr+ 2 -# CHECK: bnuctr+ 0 # encoding: [0x4c,0xe3,0x04,0x20] - bnuctr+ -# CHECK: bnul+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnul+ 2, target -# CHECK: bnul+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnul+ target -# CHECK: bnula+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnula+ 2, target -# CHECK: bnula+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnula+ target -# CHECK: bnulrl+ 2 # encoding: [0x4c,0xeb,0x00,0x21] - bnulrl+ 2 -# CHECK: bnulrl+ 0 # encoding: [0x4c,0xe3,0x00,0x21] - bnulrl+ -# CHECK: bnuctrl+ 2 # encoding: [0x4c,0xeb,0x04,0x21] - bnuctrl+ 2 -# CHECK: bnuctrl+ 0 # encoding: [0x4c,0xe3,0x04,0x21] - bnuctrl+ - -# CHECK: bnu- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnu- 2, target -# CHECK: bnu- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnu- target -# CHECK: bnua- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnua- 2, target -# CHECK: bnua- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnua- target -# CHECK: bnulr- 2 # encoding: [0x4c,0xcb,0x00,0x20] - bnulr- 2 -# CHECK: bnulr- 0 # encoding: [0x4c,0xc3,0x00,0x20] - bnulr- -# CHECK: bnuctr- 2 # encoding: [0x4c,0xcb,0x04,0x20] - bnuctr- 2 -# CHECK: bnuctr- 0 # encoding: [0x4c,0xc3,0x04,0x20] - bnuctr- -# CHECK: bnul- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnul- 2, target -# CHECK: bnul- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bnul- target -# CHECK: bnula- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnula- 2, target -# CHECK: bnula- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bnula- target -# CHECK: bnulrl- 2 # encoding: [0x4c,0xcb,0x00,0x21] - bnulrl- 2 -# CHECK: bnulrl- 0 # encoding: [0x4c,0xc3,0x00,0x21] - bnulrl- -# CHECK: bnuctrl- 2 # encoding: [0x4c,0xcb,0x04,0x21] - bnuctrl- 2 -# CHECK: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21] - bnuctrl- +# CHECK-BE: blr # encoding: [0x4e,0x80,0x00,0x20] +# CHECK-LE: blr # encoding: [0x20,0x00,0x80,0x4e] + blr +# CHECK-BE: bctr # encoding: [0x4e,0x80,0x04,0x20] +# CHECK-LE: bctr # encoding: [0x20,0x04,0x80,0x4e] + bctr +# CHECK-BE: blrl # encoding: [0x4e,0x80,0x00,0x21] +# CHECK-LE: blrl # encoding: [0x21,0x00,0x80,0x4e] + blrl +# CHECK-BE: bctrl # encoding: [0x4e,0x80,0x04,0x21] +# CHECK-LE: bctrl # encoding: [0x21,0x04,0x80,0x4e] + bctrl + +# CHECK-BE: bc 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA00] +# CHECK-LE: bc 12, 2, target # encoding: [0bAAAAAA00,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bt 2, target +# CHECK-BE: bca 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA10] +# CHECK-LE: bca 12, 2, target # encoding: [0bAAAAAA10,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bta 2, target +# CHECK-BE: bclr 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x20] +# CHECK-LE: bclr 12, 2, 0 # encoding: [0x20,0x00,0x82,0x4d] + btlr 2 +# CHECK-BE: bcctr 12, 2, 0 # encoding: [0x4d,0x82,0x04,0x20] +# CHECK-LE: bcctr 12, 2, 0 # encoding: [0x20,0x04,0x82,0x4d] + btctr 2 +# CHECK-BE: bcl 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA01] +# CHECK-LE: bcl 12, 2, target # encoding: [0bAAAAAA01,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + btl 2, target +# CHECK-BE: bcla 12, 2, target # encoding: [0x41,0x82,A,0bAAAAAA11] +# CHECK-LE: bcla 12, 2, target # encoding: [0bAAAAAA11,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + btla 2, target +# CHECK-BE: bclrl 12, 2, 0 # encoding: [0x4d,0x82,0x00,0x21] +# CHECK-LE: bclrl 12, 2, 0 # encoding: [0x21,0x00,0x82,0x4d] + btlrl 2 +# CHECK-BE: bcctrl 12, 2, 0 # encoding: [0x4d,0x82,0x04,0x21] +# CHECK-LE: bcctrl 12, 2, 0 # encoding: [0x21,0x04,0x82,0x4d] + btctrl 2 + +# CHECK-BE: bc 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA00] +# CHECK-LE: bc 15, 2, target # encoding: [0bAAAAAA00,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bt+ 2, target +# CHECK-BE: bca 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA10] +# CHECK-LE: bca 15, 2, target # encoding: [0bAAAAAA10,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bta+ 2, target +# CHECK-BE: bclr 15, 2, 0 # encoding: [0x4d,0xe2,0x00,0x20] +# CHECK-LE: bclr 15, 2, 0 # encoding: [0x20,0x00,0xe2,0x4d] + btlr+ 2 +# CHECK-BE: bcctr 15, 2, 0 # encoding: [0x4d,0xe2,0x04,0x20] +# CHECK-LE: bcctr 15, 2, 0 # encoding: [0x20,0x04,0xe2,0x4d] + btctr+ 2 +# CHECK-BE: bcl 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA01] +# CHECK-LE: bcl 15, 2, target # encoding: [0bAAAAAA01,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + btl+ 2, target +# CHECK-BE: bcla 15, 2, target # encoding: [0x41,0xe2,A,0bAAAAAA11] +# CHECK-LE: bcla 15, 2, target # encoding: [0bAAAAAA11,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + btla+ 2, target +# CHECK-BE: bclrl 15, 2, 0 # encoding: [0x4d,0xe2,0x00,0x21] +# CHECK-LE: bclrl 15, 2, 0 # encoding: [0x21,0x00,0xe2,0x4d] + btlrl+ 2 +# CHECK-BE: bcctrl 15, 2, 0 # encoding: [0x4d,0xe2,0x04,0x21] +# CHECK-LE: bcctrl 15, 2, 0 # encoding: [0x21,0x04,0xe2,0x4d] + btctrl+ 2 + +# CHECK-BE: bc 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA00] +# CHECK-LE: bc 14, 2, target # encoding: [0bAAAAAA00,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bt- 2, target +# CHECK-BE: bca 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA10] +# CHECK-LE: bca 14, 2, target # encoding: [0bAAAAAA10,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bta- 2, target +# CHECK-BE: bclr 14, 2, 0 # encoding: [0x4d,0xc2,0x00,0x20] +# CHECK-LE: bclr 14, 2, 0 # encoding: [0x20,0x00,0xc2,0x4d] + btlr- 2 +# CHECK-BE: bcctr 14, 2, 0 # encoding: [0x4d,0xc2,0x04,0x20] +# CHECK-LE: bcctr 14, 2, 0 # encoding: [0x20,0x04,0xc2,0x4d] + btctr- 2 +# CHECK-BE: bcl 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA01] +# CHECK-LE: bcl 14, 2, target # encoding: [0bAAAAAA01,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + btl- 2, target +# CHECK-BE: bcla 14, 2, target # encoding: [0x41,0xc2,A,0bAAAAAA11] +# CHECK-LE: bcla 14, 2, target # encoding: [0bAAAAAA11,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + btla- 2, target +# CHECK-BE: bclrl 14, 2, 0 # encoding: [0x4d,0xc2,0x00,0x21] +# CHECK-LE: bclrl 14, 2, 0 # encoding: [0x21,0x00,0xc2,0x4d] + btlrl- 2 +# CHECK-BE: bcctrl 14, 2, 0 # encoding: [0x4d,0xc2,0x04,0x21] +# CHECK-LE: bcctrl 14, 2, 0 # encoding: [0x21,0x04,0xc2,0x4d] + btctrl- 2 + +# CHECK-BE: bc 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA00] +# CHECK-LE: bc 4, 2, target # encoding: [0bAAAAAA00,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bf 2, target +# CHECK-BE: bca 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA10] +# CHECK-LE: bca 4, 2, target # encoding: [0bAAAAAA10,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bfa 2, target +# CHECK-BE: bclr 4, 2, 0 # encoding: [0x4c,0x82,0x00,0x20] +# CHECK-LE: bclr 4, 2, 0 # encoding: [0x20,0x00,0x82,0x4c] + bflr 2 +# CHECK-BE: bcctr 4, 2, 0 # encoding: [0x4c,0x82,0x04,0x20] +# CHECK-LE: bcctr 4, 2, 0 # encoding: [0x20,0x04,0x82,0x4c] + bfctr 2 +# CHECK-BE: bcl 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA01] +# CHECK-LE: bcl 4, 2, target # encoding: [0bAAAAAA01,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bfl 2, target +# CHECK-BE: bcla 4, 2, target # encoding: [0x40,0x82,A,0bAAAAAA11] +# CHECK-LE: bcla 4, 2, target # encoding: [0bAAAAAA11,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bfla 2, target +# CHECK-BE: bclrl 4, 2, 0 # encoding: [0x4c,0x82,0x00,0x21] +# CHECK-LE: bclrl 4, 2, 0 # encoding: [0x21,0x00,0x82,0x4c] + bflrl 2 +# CHECK-BE: bcctrl 4, 2, 0 # encoding: [0x4c,0x82,0x04,0x21] +# CHECK-LE: bcctrl 4, 2, 0 # encoding: [0x21,0x04,0x82,0x4c] + bfctrl 2 + +# CHECK-BE: bc 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA00] +# CHECK-LE: bc 7, 2, target # encoding: [0bAAAAAA00,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bf+ 2, target +# CHECK-BE: bca 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA10] +# CHECK-LE: bca 7, 2, target # encoding: [0bAAAAAA10,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bfa+ 2, target +# CHECK-BE: bclr 7, 2, 0 # encoding: [0x4c,0xe2,0x00,0x20] +# CHECK-LE: bclr 7, 2, 0 # encoding: [0x20,0x00,0xe2,0x4c] + bflr+ 2 +# CHECK-BE: bcctr 7, 2, 0 # encoding: [0x4c,0xe2,0x04,0x20] +# CHECK-LE: bcctr 7, 2, 0 # encoding: [0x20,0x04,0xe2,0x4c] + bfctr+ 2 +# CHECK-BE: bcl 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA01] +# CHECK-LE: bcl 7, 2, target # encoding: [0bAAAAAA01,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bfl+ 2, target +# CHECK-BE: bcla 7, 2, target # encoding: [0x40,0xe2,A,0bAAAAAA11] +# CHECK-LE: bcla 7, 2, target # encoding: [0bAAAAAA11,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bfla+ 2, target +# CHECK-BE: bclrl 7, 2, 0 # encoding: [0x4c,0xe2,0x00,0x21] +# CHECK-LE: bclrl 7, 2, 0 # encoding: [0x21,0x00,0xe2,0x4c] + bflrl+ 2 +# CHECK-BE: bcctrl 7, 2, 0 # encoding: [0x4c,0xe2,0x04,0x21] +# CHECK-LE: bcctrl 7, 2, 0 # encoding: [0x21,0x04,0xe2,0x4c] + bfctrl+ 2 + +# CHECK-BE: bc 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA00] +# CHECK-LE: bc 6, 2, target # encoding: [0bAAAAAA00,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bf- 2, target +# CHECK-BE: bca 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA10] +# CHECK-LE: bca 6, 2, target # encoding: [0bAAAAAA10,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bfa- 2, target +# CHECK-BE: bclr 6, 2, 0 # encoding: [0x4c,0xc2,0x00,0x20] +# CHECK-LE: bclr 6, 2, 0 # encoding: [0x20,0x00,0xc2,0x4c] + bflr- 2 +# CHECK-BE: bcctr 6, 2, 0 # encoding: [0x4c,0xc2,0x04,0x20] +# CHECK-LE: bcctr 6, 2, 0 # encoding: [0x20,0x04,0xc2,0x4c] + bfctr- 2 +# CHECK-BE: bcl 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA01] +# CHECK-LE: bcl 6, 2, target # encoding: [0bAAAAAA01,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bfl- 2, target +# CHECK-BE: bcla 6, 2, target # encoding: [0x40,0xc2,A,0bAAAAAA11] +# CHECK-LE: bcla 6, 2, target # encoding: [0bAAAAAA11,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bfla- 2, target +# CHECK-BE: bclrl 6, 2, 0 # encoding: [0x4c,0xc2,0x00,0x21] +# CHECK-LE: bclrl 6, 2, 0 # encoding: [0x21,0x00,0xc2,0x4c] + bflrl- 2 +# CHECK-BE: bcctrl 6, 2, 0 # encoding: [0x4c,0xc2,0x04,0x21] +# CHECK-LE: bcctrl 6, 2, 0 # encoding: [0x21,0x04,0xc2,0x4c] + bfctrl- 2 + +# CHECK-BE: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00] +# CHECK-LE: bdnz target # encoding: [0bAAAAAA00,A,0x00,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnz target +# CHECK-BE: bdnza target # encoding: [0x42,0x00,A,0bAAAAAA10] +# CHECK-LE: bdnza target # encoding: [0bAAAAAA10,A,0x00,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnza target +# CHECK-BE: bdnzlr # encoding: [0x4e,0x00,0x00,0x20] +# CHECK-LE: bdnzlr # encoding: [0x20,0x00,0x00,0x4e] + bdnzlr +# CHECK-BE: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01] +# CHECK-LE: bdnzl target # encoding: [0bAAAAAA01,A,0x00,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzl target +# CHECK-BE: bdnzla target # encoding: [0x42,0x00,A,0bAAAAAA11] +# CHECK-LE: bdnzla target # encoding: [0bAAAAAA11,A,0x00,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnzla target +# CHECK-BE: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21] +# CHECK-LE: bdnzlrl # encoding: [0x21,0x00,0x00,0x4e] + bdnzlrl + +# CHECK-BE: bdnz+ target # encoding: [0x43,0x20,A,0bAAAAAA00] +# CHECK-LE: bdnz+ target # encoding: [0bAAAAAA00,A,0x20,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnz+ target +# CHECK-BE: bdnza+ target # encoding: [0x43,0x20,A,0bAAAAAA10] +# CHECK-LE: bdnza+ target # encoding: [0bAAAAAA10,A,0x20,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnza+ target +# CHECK-BE: bdnzlr+ # encoding: [0x4f,0x20,0x00,0x20] +# CHECK-LE: bdnzlr+ # encoding: [0x20,0x00,0x20,0x4f] + bdnzlr+ +# CHECK-BE: bdnzl+ target # encoding: [0x43,0x20,A,0bAAAAAA01] +# CHECK-LE: bdnzl+ target # encoding: [0bAAAAAA01,A,0x20,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzl+ target +# CHECK-BE: bdnzla+ target # encoding: [0x43,0x20,A,0bAAAAAA11] +# CHECK-LE: bdnzla+ target # encoding: [0bAAAAAA11,A,0x20,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnzla+ target +# CHECK-BE: bdnzlrl+ # encoding: [0x4f,0x20,0x00,0x21] +# CHECK-LE: bdnzlrl+ # encoding: [0x21,0x00,0x20,0x4f] + bdnzlrl+ + +# CHECK-BE: bdnz- target # encoding: [0x43,0x00,A,0bAAAAAA00] +# CHECK-LE: bdnz- target # encoding: [0bAAAAAA00,A,0x00,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnz- target +# CHECK-BE: bdnza- target # encoding: [0x43,0x00,A,0bAAAAAA10] +# CHECK-LE: bdnza- target # encoding: [0bAAAAAA10,A,0x00,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnza- target +# CHECK-BE: bdnzlr- # encoding: [0x4f,0x00,0x00,0x20] +# CHECK-LE: bdnzlr- # encoding: [0x20,0x00,0x00,0x4f] + bdnzlr- +# CHECK-BE: bdnzl- target # encoding: [0x43,0x00,A,0bAAAAAA01] +# CHECK-LE: bdnzl- target # encoding: [0bAAAAAA01,A,0x00,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzl- target +# CHECK-BE: bdnzla- target # encoding: [0x43,0x00,A,0bAAAAAA11] +# CHECK-LE: bdnzla- target # encoding: [0bAAAAAA11,A,0x00,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnzla- target +# CHECK-BE: bdnzlrl- # encoding: [0x4f,0x00,0x00,0x21] +# CHECK-LE: bdnzlrl- # encoding: [0x21,0x00,0x00,0x4f] + bdnzlrl- + +# CHECK-BE: bc 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA00] +# CHECK-LE: bc 8, 2, target # encoding: [0bAAAAAA00,A,0x02,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzt 2, target +# CHECK-BE: bca 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA10] +# CHECK-LE: bca 8, 2, target # encoding: [0bAAAAAA10,A,0x02,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnzta 2, target +# CHECK-BE: bclr 8, 2, 0 # encoding: [0x4d,0x02,0x00,0x20] +# CHECK-LE: bclr 8, 2, 0 # encoding: [0x20,0x00,0x02,0x4d] + bdnztlr 2 +# CHECK-BE: bcl 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA01] +# CHECK-LE: bcl 8, 2, target # encoding: [0bAAAAAA01,A,0x02,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnztl 2, target +# CHECK-BE: bcla 8, 2, target # encoding: [0x41,0x02,A,0bAAAAAA11] +# CHECK-LE: bcla 8, 2, target # encoding: [0bAAAAAA11,A,0x02,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnztla 2, target +# CHECK-BE: bclrl 8, 2, 0 # encoding: [0x4d,0x02,0x00,0x21] +# CHECK-LE: bclrl 8, 2, 0 # encoding: [0x21,0x00,0x02,0x4d] + bdnztlrl 2 + +# CHECK-BE: bc 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA00] +# CHECK-LE: bc 0, 2, target # encoding: [0bAAAAAA00,A,0x02,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzf 2, target +# CHECK-BE: bca 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA10] +# CHECK-LE: bca 0, 2, target # encoding: [0bAAAAAA10,A,0x02,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnzfa 2, target +# CHECK-BE: bclr 0, 2, 0 # encoding: [0x4c,0x02,0x00,0x20] +# CHECK-LE: bclr 0, 2, 0 # encoding: [0x20,0x00,0x02,0x4c] + bdnzflr 2 +# CHECK-BE: bcl 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA01] +# CHECK-LE: bcl 0, 2, target # encoding: [0bAAAAAA01,A,0x02,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnzfl 2, target +# CHECK-BE: bcla 0, 2, target # encoding: [0x40,0x02,A,0bAAAAAA11] +# CHECK-LE: bcla 0, 2, target # encoding: [0bAAAAAA11,A,0x02,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdnzfla 2, target +# CHECK-BE: bclrl 0, 2, 0 # encoding: [0x4c,0x02,0x00,0x21] +# CHECK-LE: bclrl 0, 2, 0 # encoding: [0x21,0x00,0x02,0x4c] + bdnzflrl 2 + +# CHECK-BE: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00] +# CHECK-LE: bdz target # encoding: [0bAAAAAA00,A,0x40,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdz target +# CHECK-BE: bdza target # encoding: [0x42,0x40,A,0bAAAAAA10] +# CHECK-LE: bdza target # encoding: [0bAAAAAA10,A,0x40,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdza target +# CHECK-BE: bdzlr # encoding: [0x4e,0x40,0x00,0x20] +# CHECK-LE: bdzlr # encoding: [0x20,0x00,0x40,0x4e] + bdzlr +# CHECK-BE: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01] +# CHECK-LE: bdzl target # encoding: [0bAAAAAA01,A,0x40,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzl target +# CHECK-BE: bdzla target # encoding: [0x42,0x40,A,0bAAAAAA11] +# CHECK-LE: bdzla target # encoding: [0bAAAAAA11,A,0x40,0x42] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdzla target +# CHECK-BE: bdzlrl # encoding: [0x4e,0x40,0x00,0x21] +# CHECK-LE: bdzlrl # encoding: [0x21,0x00,0x40,0x4e] + bdzlrl + +# CHECK-BE: bdz+ target # encoding: [0x43,0x60,A,0bAAAAAA00] +# CHECK-LE: bdz+ target # encoding: [0bAAAAAA00,A,0x60,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdz+ target +# CHECK-BE: bdza+ target # encoding: [0x43,0x60,A,0bAAAAAA10] +# CHECK-LE: bdza+ target # encoding: [0bAAAAAA10,A,0x60,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdza+ target +# CHECK-BE: bdzlr+ # encoding: [0x4f,0x60,0x00,0x20] +# CHECK-LE: bdzlr+ # encoding: [0x20,0x00,0x60,0x4f] + bdzlr+ +# CHECK-BE: bdzl+ target # encoding: [0x43,0x60,A,0bAAAAAA01] +# CHECK-LE: bdzl+ target # encoding: [0bAAAAAA01,A,0x60,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzl+ target +# CHECK-BE: bdzla+ target # encoding: [0x43,0x60,A,0bAAAAAA11] +# CHECK-LE: bdzla+ target # encoding: [0bAAAAAA11,A,0x60,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdzla+ target +# CHECK-BE: bdzlrl+ # encoding: [0x4f,0x60,0x00,0x21] +# CHECK-LE: bdzlrl+ # encoding: [0x21,0x00,0x60,0x4f] + bdzlrl+ + +# CHECK-BE: bdz- target # encoding: [0x43,0x40,A,0bAAAAAA00] +# CHECK-LE: bdz- target # encoding: [0bAAAAAA00,A,0x40,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdz- target +# CHECK-BE: bdza- target # encoding: [0x43,0x40,A,0bAAAAAA10] +# CHECK-LE: bdza- target # encoding: [0bAAAAAA10,A,0x40,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdza- target +# CHECK-BE: bdzlr- # encoding: [0x4f,0x40,0x00,0x20] +# CHECK-LE: bdzlr- # encoding: [0x20,0x00,0x40,0x4f] + bdzlr- +# CHECK-BE: bdzl- target # encoding: [0x43,0x40,A,0bAAAAAA01] +# CHECK-LE: bdzl- target # encoding: [0bAAAAAA01,A,0x40,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzl- target +# CHECK-BE: bdzla- target # encoding: [0x43,0x40,A,0bAAAAAA11] +# CHECK-LE: bdzla- target # encoding: [0bAAAAAA11,A,0x40,0x43] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdzla- target +# CHECK-BE: bdzlrl- # encoding: [0x4f,0x40,0x00,0x21] +# CHECK-LE: bdzlrl- # encoding: [0x21,0x00,0x40,0x4f] + bdzlrl- + +# CHECK-BE: bc 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA00] +# CHECK-LE: bc 10, 2, target # encoding: [0bAAAAAA00,A,0x42,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzt 2, target +# CHECK-BE: bca 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA10] +# CHECK-LE: bca 10, 2, target # encoding: [0bAAAAAA10,A,0x42,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdzta 2, target +# CHECK-BE: bclr 10, 2, 0 # encoding: [0x4d,0x42,0x00,0x20] +# CHECK-LE: bclr 10, 2, 0 # encoding: [0x20,0x00,0x42,0x4d] + bdztlr 2 +# CHECK-BE: bcl 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA01] +# CHECK-LE: bcl 10, 2, target # encoding: [0bAAAAAA01,A,0x42,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdztl 2, target +# CHECK-BE: bcla 10, 2, target # encoding: [0x41,0x42,A,0bAAAAAA11] +# CHECK-LE: bcla 10, 2, target # encoding: [0bAAAAAA11,A,0x42,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdztla 2, target +# CHECK-BE: bclrl 10, 2, 0 # encoding: [0x4d,0x42,0x00,0x21] +# CHECK-LE: bclrl 10, 2, 0 # encoding: [0x21,0x00,0x42,0x4d] + bdztlrl 2 + +# CHECK-BE: bc 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA00] +# CHECK-LE: bc 2, 2, target # encoding: [0bAAAAAA00,A,0x42,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzf 2, target +# CHECK-BE: bca 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA10] +# CHECK-LE: bca 2, 2, target # encoding: [0bAAAAAA10,A,0x42,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdzfa 2, target +# CHECK-BE: bclr 2, 2, 0 # encoding: [0x4c,0x42,0x00,0x20] +# CHECK-LE: bclr 2, 2, 0 # encoding: [0x20,0x00,0x42,0x4c] + bdzflr 2 +# CHECK-BE: bcl 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA01] +# CHECK-LE: bcl 2, 2, target # encoding: [0bAAAAAA01,A,0x42,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdzfl 2, target +# CHECK-BE: bcla 2, 2, target # encoding: [0x40,0x42,A,0bAAAAAA11] +# CHECK-LE: bcla 2, 2, target # encoding: [0bAAAAAA11,A,0x42,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bdzfla 2, target +# CHECK-BE: bclrl 2, 2, 0 # encoding: [0x4c,0x42,0x00,0x21] +# CHECK-LE: bclrl 2, 2, 0 # encoding: [0x21,0x00,0x42,0x4c] + bdzflrl 2 + +# CHECK-BE: blt 2, target # encoding: [0x41,0x88,A,0bAAAAAA00] +# CHECK-LE: blt 2, target # encoding: [0bAAAAAA00,A,0x88,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt 2, target +# CHECK-BE: blt 0, target # encoding: [0x41,0x80,A,0bAAAAAA00] +# CHECK-LE: blt 0, target # encoding: [0bAAAAAA00,A,0x80,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt target +# CHECK-BE: blta 2, target # encoding: [0x41,0x88,A,0bAAAAAA10] +# CHECK-LE: blta 2, target # encoding: [0bAAAAAA10,A,0x88,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blta 2, target +# CHECK-BE: blta 0, target # encoding: [0x41,0x80,A,0bAAAAAA10] +# CHECK-LE: blta 0, target # encoding: [0bAAAAAA10,A,0x80,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blta target +# CHECK-BE: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20] +# CHECK-LE: bltlr 2 # encoding: [0x20,0x00,0x88,0x4d] + bltlr 2 +# CHECK-BE: bltlr 0 # encoding: [0x4d,0x80,0x00,0x20] +# CHECK-LE: bltlr 0 # encoding: [0x20,0x00,0x80,0x4d] + bltlr +# CHECK-BE: bltctr 2 # encoding: [0x4d,0x88,0x04,0x20] +# CHECK-LE: bltctr 2 # encoding: [0x20,0x04,0x88,0x4d] + bltctr 2 +# CHECK-BE: bltctr 0 # encoding: [0x4d,0x80,0x04,0x20] +# CHECK-LE: bltctr 0 # encoding: [0x20,0x04,0x80,0x4d] + bltctr +# CHECK-BE: bltl 2, target # encoding: [0x41,0x88,A,0bAAAAAA01] +# CHECK-LE: bltl 2, target # encoding: [0bAAAAAA01,A,0x88,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bltl 2, target +# CHECK-BE: bltl 0, target # encoding: [0x41,0x80,A,0bAAAAAA01] +# CHECK-LE: bltl 0, target # encoding: [0bAAAAAA01,A,0x80,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bltl target +# CHECK-BE: bltla 2, target # encoding: [0x41,0x88,A,0bAAAAAA11] +# CHECK-LE: bltla 2, target # encoding: [0bAAAAAA11,A,0x88,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bltla 2, target +# CHECK-BE: bltla 0, target # encoding: [0x41,0x80,A,0bAAAAAA11] +# CHECK-LE: bltla 0, target # encoding: [0bAAAAAA11,A,0x80,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bltla target +# CHECK-BE: bltlrl 2 # encoding: [0x4d,0x88,0x00,0x21] +# CHECK-LE: bltlrl 2 # encoding: [0x21,0x00,0x88,0x4d] + bltlrl 2 +# CHECK-BE: bltlrl 0 # encoding: [0x4d,0x80,0x00,0x21] +# CHECK-LE: bltlrl 0 # encoding: [0x21,0x00,0x80,0x4d] + bltlrl +# CHECK-BE: bltctrl 2 # encoding: [0x4d,0x88,0x04,0x21] +# CHECK-LE: bltctrl 2 # encoding: [0x21,0x04,0x88,0x4d] + bltctrl 2 +# CHECK-BE: bltctrl 0 # encoding: [0x4d,0x80,0x04,0x21] +# CHECK-LE: bltctrl 0 # encoding: [0x21,0x04,0x80,0x4d] + bltctrl + +# CHECK-BE: blt+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA00] +# CHECK-LE: blt+ 2, target # encoding: [0bAAAAAA00,A,0xe8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt+ 2, target +# CHECK-BE: blt+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA00] +# CHECK-LE: blt+ 0, target # encoding: [0bAAAAAA00,A,0xe0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt+ target +# CHECK-BE: blta+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA10] +# CHECK-LE: blta+ 2, target # encoding: [0bAAAAAA10,A,0xe8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blta+ 2, target +# CHECK-BE: blta+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA10] +# CHECK-LE: blta+ 0, target # encoding: [0bAAAAAA10,A,0xe0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blta+ target +# CHECK-BE: bltlr+ 2 # encoding: [0x4d,0xe8,0x00,0x20] +# CHECK-LE: bltlr+ 2 # encoding: [0x20,0x00,0xe8,0x4d] + bltlr+ 2 +# CHECK-BE: bltlr+ 0 # encoding: [0x4d,0xe0,0x00,0x20] +# CHECK-LE: bltlr+ 0 # encoding: [0x20,0x00,0xe0,0x4d] + bltlr+ +# CHECK-BE: bltctr+ 2 # encoding: [0x4d,0xe8,0x04,0x20] +# CHECK-LE: bltctr+ 2 # encoding: [0x20,0x04,0xe8,0x4d] + bltctr+ 2 +# CHECK-BE: bltctr+ 0 # encoding: [0x4d,0xe0,0x04,0x20] +# CHECK-LE: bltctr+ 0 # encoding: [0x20,0x04,0xe0,0x4d] + bltctr+ +# CHECK-BE: bltl+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA01] +# CHECK-LE: bltl+ 2, target # encoding: [0bAAAAAA01,A,0xe8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bltl+ 2, target +# CHECK-BE: bltl+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA01] +# CHECK-LE: bltl+ 0, target # encoding: [0bAAAAAA01,A,0xe0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bltl+ target +# CHECK-BE: bltla+ 2, target # encoding: [0x41,0xe8,A,0bAAAAAA11] +# CHECK-LE: bltla+ 2, target # encoding: [0bAAAAAA11,A,0xe8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bltla+ 2, target +# CHECK-BE: bltla+ 0, target # encoding: [0x41,0xe0,A,0bAAAAAA11] +# CHECK-LE: bltla+ 0, target # encoding: [0bAAAAAA11,A,0xe0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bltla+ target +# CHECK-BE: bltlrl+ 2 # encoding: [0x4d,0xe8,0x00,0x21] +# CHECK-LE: bltlrl+ 2 # encoding: [0x21,0x00,0xe8,0x4d] + bltlrl+ 2 +# CHECK-BE: bltlrl+ 0 # encoding: [0x4d,0xe0,0x00,0x21] +# CHECK-LE: bltlrl+ 0 # encoding: [0x21,0x00,0xe0,0x4d] + bltlrl+ +# CHECK-BE: bltctrl+ 2 # encoding: [0x4d,0xe8,0x04,0x21] +# CHECK-LE: bltctrl+ 2 # encoding: [0x21,0x04,0xe8,0x4d] + bltctrl+ 2 +# CHECK-BE: bltctrl+ 0 # encoding: [0x4d,0xe0,0x04,0x21] +# CHECK-LE: bltctrl+ 0 # encoding: [0x21,0x04,0xe0,0x4d] + bltctrl+ + +# CHECK-BE: blt- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA00] +# CHECK-LE: blt- 2, target # encoding: [0bAAAAAA00,A,0xc8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt- 2, target +# CHECK-BE: blt- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA00] +# CHECK-LE: blt- 0, target # encoding: [0bAAAAAA00,A,0xc0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt- target +# CHECK-BE: blta- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA10] +# CHECK-LE: blta- 2, target # encoding: [0bAAAAAA10,A,0xc8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blta- 2, target +# CHECK-BE: blta- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA10] +# CHECK-LE: blta- 0, target # encoding: [0bAAAAAA10,A,0xc0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blta- target +# CHECK-BE: bltlr- 2 # encoding: [0x4d,0xc8,0x00,0x20] +# CHECK-LE: bltlr- 2 # encoding: [0x20,0x00,0xc8,0x4d] + bltlr- 2 +# CHECK-BE: bltlr- 0 # encoding: [0x4d,0xc0,0x00,0x20] +# CHECK-LE: bltlr- 0 # encoding: [0x20,0x00,0xc0,0x4d] + bltlr- +# CHECK-BE: bltctr- 2 # encoding: [0x4d,0xc8,0x04,0x20] +# CHECK-LE: bltctr- 2 # encoding: [0x20,0x04,0xc8,0x4d] + bltctr- 2 +# CHECK-BE: bltctr- 0 # encoding: [0x4d,0xc0,0x04,0x20] +# CHECK-LE: bltctr- 0 # encoding: [0x20,0x04,0xc0,0x4d] + bltctr- +# CHECK-BE: bltl- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA01] +# CHECK-LE: bltl- 2, target # encoding: [0bAAAAAA01,A,0xc8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bltl- 2, target +# CHECK-BE: bltl- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA01] +# CHECK-LE: bltl- 0, target # encoding: [0bAAAAAA01,A,0xc0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bltl- target +# CHECK-BE: bltla- 2, target # encoding: [0x41,0xc8,A,0bAAAAAA11] +# CHECK-LE: bltla- 2, target # encoding: [0bAAAAAA11,A,0xc8,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bltla- 2, target +# CHECK-BE: bltla- 0, target # encoding: [0x41,0xc0,A,0bAAAAAA11] +# CHECK-LE: bltla- 0, target # encoding: [0bAAAAAA11,A,0xc0,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bltla- target +# CHECK-BE: bltlrl- 2 # encoding: [0x4d,0xc8,0x00,0x21] +# CHECK-LE: bltlrl- 2 # encoding: [0x21,0x00,0xc8,0x4d] + bltlrl- 2 +# CHECK-BE: bltlrl- 0 # encoding: [0x4d,0xc0,0x00,0x21] +# CHECK-LE: bltlrl- 0 # encoding: [0x21,0x00,0xc0,0x4d] + bltlrl- +# CHECK-BE: bltctrl- 2 # encoding: [0x4d,0xc8,0x04,0x21] +# CHECK-LE: bltctrl- 2 # encoding: [0x21,0x04,0xc8,0x4d] + bltctrl- 2 +# CHECK-BE: bltctrl- 0 # encoding: [0x4d,0xc0,0x04,0x21] +# CHECK-LE: bltctrl- 0 # encoding: [0x21,0x04,0xc0,0x4d] + bltctrl- + +# CHECK-BE: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00] +# CHECK-LE: ble 2, target # encoding: [0bAAAAAA00,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble 2, target +# CHECK-BE: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00] +# CHECK-LE: ble 0, target # encoding: [0bAAAAAA00,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble target +# CHECK-BE: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10] +# CHECK-LE: blea 2, target # encoding: [0bAAAAAA10,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blea 2, target +# CHECK-BE: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10] +# CHECK-LE: blea 0, target # encoding: [0bAAAAAA10,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blea target +# CHECK-BE: blelr 2 # encoding: [0x4c,0x89,0x00,0x20] +# CHECK-LE: blelr 2 # encoding: [0x20,0x00,0x89,0x4c] + blelr 2 +# CHECK-BE: blelr 0 # encoding: [0x4c,0x81,0x00,0x20] +# CHECK-LE: blelr 0 # encoding: [0x20,0x00,0x81,0x4c] + blelr +# CHECK-BE: blectr 2 # encoding: [0x4c,0x89,0x04,0x20] +# CHECK-LE: blectr 2 # encoding: [0x20,0x04,0x89,0x4c] + blectr 2 +# CHECK-BE: blectr 0 # encoding: [0x4c,0x81,0x04,0x20] +# CHECK-LE: blectr 0 # encoding: [0x20,0x04,0x81,0x4c] + blectr +# CHECK-BE: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01] +# CHECK-LE: blel 2, target # encoding: [0bAAAAAA01,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blel 2, target +# CHECK-BE: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01] +# CHECK-LE: blel 0, target # encoding: [0bAAAAAA01,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blel target +# CHECK-BE: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11] +# CHECK-LE: blela 2, target # encoding: [0bAAAAAA11,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blela 2, target +# CHECK-BE: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11] +# CHECK-LE: blela 0, target # encoding: [0bAAAAAA11,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blela target +# CHECK-BE: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21] +# CHECK-LE: blelrl 2 # encoding: [0x21,0x00,0x89,0x4c] + blelrl 2 +# CHECK-BE: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21] +# CHECK-LE: blelrl 0 # encoding: [0x21,0x00,0x81,0x4c] + blelrl +# CHECK-BE: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21] +# CHECK-LE: blectrl 2 # encoding: [0x21,0x04,0x89,0x4c] + blectrl 2 +# CHECK-BE: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21] +# CHECK-LE: blectrl 0 # encoding: [0x21,0x04,0x81,0x4c] + blectrl + +# CHECK-BE: ble+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA00] +# CHECK-LE: ble+ 2, target # encoding: [0bAAAAAA00,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble+ 2, target +# CHECK-BE: ble+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA00] +# CHECK-LE: ble+ 0, target # encoding: [0bAAAAAA00,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble+ target +# CHECK-BE: blea+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA10] +# CHECK-LE: blea+ 2, target # encoding: [0bAAAAAA10,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blea+ 2, target +# CHECK-BE: blea+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA10] +# CHECK-LE: blea+ 0, target # encoding: [0bAAAAAA10,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blea+ target +# CHECK-BE: blelr+ 2 # encoding: [0x4c,0xe9,0x00,0x20] +# CHECK-LE: blelr+ 2 # encoding: [0x20,0x00,0xe9,0x4c] + blelr+ 2 +# CHECK-BE: blelr+ 0 # encoding: [0x4c,0xe1,0x00,0x20] +# CHECK-LE: blelr+ 0 # encoding: [0x20,0x00,0xe1,0x4c] + blelr+ +# CHECK-BE: blectr+ 2 # encoding: [0x4c,0xe9,0x04,0x20] +# CHECK-LE: blectr+ 2 # encoding: [0x20,0x04,0xe9,0x4c] + blectr+ 2 +# CHECK-BE: blectr+ 0 # encoding: [0x4c,0xe1,0x04,0x20] +# CHECK-LE: blectr+ 0 # encoding: [0x20,0x04,0xe1,0x4c] + blectr+ +# CHECK-BE: blel+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA01] +# CHECK-LE: blel+ 2, target # encoding: [0bAAAAAA01,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blel+ 2, target +# CHECK-BE: blel+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA01] +# CHECK-LE: blel+ 0, target # encoding: [0bAAAAAA01,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blel+ target +# CHECK-BE: blela+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA11] +# CHECK-LE: blela+ 2, target # encoding: [0bAAAAAA11,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blela+ 2, target +# CHECK-BE: blela+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA11] +# CHECK-LE: blela+ 0, target # encoding: [0bAAAAAA11,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blela+ target +# CHECK-BE: blelrl+ 2 # encoding: [0x4c,0xe9,0x00,0x21] +# CHECK-LE: blelrl+ 2 # encoding: [0x21,0x00,0xe9,0x4c] + blelrl+ 2 +# CHECK-BE: blelrl+ 0 # encoding: [0x4c,0xe1,0x00,0x21] +# CHECK-LE: blelrl+ 0 # encoding: [0x21,0x00,0xe1,0x4c] + blelrl+ +# CHECK-BE: blectrl+ 2 # encoding: [0x4c,0xe9,0x04,0x21] +# CHECK-LE: blectrl+ 2 # encoding: [0x21,0x04,0xe9,0x4c] + blectrl+ 2 +# CHECK-BE: blectrl+ 0 # encoding: [0x4c,0xe1,0x04,0x21] +# CHECK-LE: blectrl+ 0 # encoding: [0x21,0x04,0xe1,0x4c] + blectrl+ + +# CHECK-BE: ble- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA00] +# CHECK-LE: ble- 2, target # encoding: [0bAAAAAA00,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble- 2, target +# CHECK-BE: ble- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA00] +# CHECK-LE: ble- 0, target # encoding: [0bAAAAAA00,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble- target +# CHECK-BE: blea- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA10] +# CHECK-LE: blea- 2, target # encoding: [0bAAAAAA10,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blea- 2, target +# CHECK-BE: blea- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA10] +# CHECK-LE: blea- 0, target # encoding: [0bAAAAAA10,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blea- target +# CHECK-BE: blelr- 2 # encoding: [0x4c,0xc9,0x00,0x20] +# CHECK-LE: blelr- 2 # encoding: [0x20,0x00,0xc9,0x4c] + blelr- 2 +# CHECK-BE: blelr- 0 # encoding: [0x4c,0xc1,0x00,0x20] +# CHECK-LE: blelr- 0 # encoding: [0x20,0x00,0xc1,0x4c] + blelr- +# CHECK-BE: blectr- 2 # encoding: [0x4c,0xc9,0x04,0x20] +# CHECK-LE: blectr- 2 # encoding: [0x20,0x04,0xc9,0x4c] + blectr- 2 +# CHECK-BE: blectr- 0 # encoding: [0x4c,0xc1,0x04,0x20] +# CHECK-LE: blectr- 0 # encoding: [0x20,0x04,0xc1,0x4c] + blectr- +# CHECK-BE: blel- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA01] +# CHECK-LE: blel- 2, target # encoding: [0bAAAAAA01,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blel- 2, target +# CHECK-BE: blel- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA01] +# CHECK-LE: blel- 0, target # encoding: [0bAAAAAA01,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blel- target +# CHECK-BE: blela- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA11] +# CHECK-LE: blela- 2, target # encoding: [0bAAAAAA11,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blela- 2, target +# CHECK-BE: blela- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA11] +# CHECK-LE: blela- 0, target # encoding: [0bAAAAAA11,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + blela- target +# CHECK-BE: blelrl- 2 # encoding: [0x4c,0xc9,0x00,0x21] +# CHECK-LE: blelrl- 2 # encoding: [0x21,0x00,0xc9,0x4c] + blelrl- 2 +# CHECK-BE: blelrl- 0 # encoding: [0x4c,0xc1,0x00,0x21] +# CHECK-LE: blelrl- 0 # encoding: [0x21,0x00,0xc1,0x4c] + blelrl- +# CHECK-BE: blectrl- 2 # encoding: [0x4c,0xc9,0x04,0x21] +# CHECK-LE: blectrl- 2 # encoding: [0x21,0x04,0xc9,0x4c] + blectrl- 2 +# CHECK-BE: blectrl- 0 # encoding: [0x4c,0xc1,0x04,0x21] +# CHECK-LE: blectrl- 0 # encoding: [0x21,0x04,0xc1,0x4c] + blectrl- + +# CHECK-BE: beq 2, target # encoding: [0x41,0x8a,A,0bAAAAAA00] +# CHECK-LE: beq 2, target # encoding: [0bAAAAAA00,A,0x8a,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq 2, target +# CHECK-BE: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00] +# CHECK-LE: beq 0, target # encoding: [0bAAAAAA00,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq target +# CHECK-BE: beqa 2, target # encoding: [0x41,0x8a,A,0bAAAAAA10] +# CHECK-LE: beqa 2, target # encoding: [0bAAAAAA10,A,0x8a,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqa 2, target +# CHECK-BE: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10] +# CHECK-LE: beqa 0, target # encoding: [0bAAAAAA10,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqa target +# CHECK-BE: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20] +# CHECK-LE: beqlr 2 # encoding: [0x20,0x00,0x8a,0x4d] + beqlr 2 +# CHECK-BE: beqlr 0 # encoding: [0x4d,0x82,0x00,0x20] +# CHECK-LE: beqlr 0 # encoding: [0x20,0x00,0x82,0x4d] + beqlr +# CHECK-BE: beqctr 2 # encoding: [0x4d,0x8a,0x04,0x20] +# CHECK-LE: beqctr 2 # encoding: [0x20,0x04,0x8a,0x4d] + beqctr 2 +# CHECK-BE: beqctr 0 # encoding: [0x4d,0x82,0x04,0x20] +# CHECK-LE: beqctr 0 # encoding: [0x20,0x04,0x82,0x4d] + beqctr +# CHECK-BE: beql 2, target # encoding: [0x41,0x8a,A,0bAAAAAA01] +# CHECK-LE: beql 2, target # encoding: [0bAAAAAA01,A,0x8a,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beql 2, target +# CHECK-BE: beql 0, target # encoding: [0x41,0x82,A,0bAAAAAA01] +# CHECK-LE: beql 0, target # encoding: [0bAAAAAA01,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beql target +# CHECK-BE: beqla 2, target # encoding: [0x41,0x8a,A,0bAAAAAA11] +# CHECK-LE: beqla 2, target # encoding: [0bAAAAAA11,A,0x8a,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqla 2, target +# CHECK-BE: beqla 0, target # encoding: [0x41,0x82,A,0bAAAAAA11] +# CHECK-LE: beqla 0, target # encoding: [0bAAAAAA11,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqla target +# CHECK-BE: beqlrl 2 # encoding: [0x4d,0x8a,0x00,0x21] +# CHECK-LE: beqlrl 2 # encoding: [0x21,0x00,0x8a,0x4d] + beqlrl 2 +# CHECK-BE: beqlrl 0 # encoding: [0x4d,0x82,0x00,0x21] +# CHECK-LE: beqlrl 0 # encoding: [0x21,0x00,0x82,0x4d] + beqlrl +# CHECK-BE: beqctrl 2 # encoding: [0x4d,0x8a,0x04,0x21] +# CHECK-LE: beqctrl 2 # encoding: [0x21,0x04,0x8a,0x4d] + beqctrl 2 +# CHECK-BE: beqctrl 0 # encoding: [0x4d,0x82,0x04,0x21] +# CHECK-LE: beqctrl 0 # encoding: [0x21,0x04,0x82,0x4d] + beqctrl + +# CHECK-BE: beq+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA00] +# CHECK-LE: beq+ 2, target # encoding: [0bAAAAAA00,A,0xea,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq+ 2, target +# CHECK-BE: beq+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA00] +# CHECK-LE: beq+ 0, target # encoding: [0bAAAAAA00,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq+ target +# CHECK-BE: beqa+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA10] +# CHECK-LE: beqa+ 2, target # encoding: [0bAAAAAA10,A,0xea,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqa+ 2, target +# CHECK-BE: beqa+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA10] +# CHECK-LE: beqa+ 0, target # encoding: [0bAAAAAA10,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqa+ target +# CHECK-BE: beqlr+ 2 # encoding: [0x4d,0xea,0x00,0x20] +# CHECK-LE: beqlr+ 2 # encoding: [0x20,0x00,0xea,0x4d] + beqlr+ 2 +# CHECK-BE: beqlr+ 0 # encoding: [0x4d,0xe2,0x00,0x20] +# CHECK-LE: beqlr+ 0 # encoding: [0x20,0x00,0xe2,0x4d] + beqlr+ +# CHECK-BE: beqctr+ 2 # encoding: [0x4d,0xea,0x04,0x20] +# CHECK-LE: beqctr+ 2 # encoding: [0x20,0x04,0xea,0x4d] + beqctr+ 2 +# CHECK-BE: beqctr+ 0 # encoding: [0x4d,0xe2,0x04,0x20] +# CHECK-LE: beqctr+ 0 # encoding: [0x20,0x04,0xe2,0x4d] + beqctr+ +# CHECK-BE: beql+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA01] +# CHECK-LE: beql+ 2, target # encoding: [0bAAAAAA01,A,0xea,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beql+ 2, target +# CHECK-BE: beql+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA01] +# CHECK-LE: beql+ 0, target # encoding: [0bAAAAAA01,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beql+ target +# CHECK-BE: beqla+ 2, target # encoding: [0x41,0xea,A,0bAAAAAA11] +# CHECK-LE: beqla+ 2, target # encoding: [0bAAAAAA11,A,0xea,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqla+ 2, target +# CHECK-BE: beqla+ 0, target # encoding: [0x41,0xe2,A,0bAAAAAA11] +# CHECK-LE: beqla+ 0, target # encoding: [0bAAAAAA11,A,0xe2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqla+ target +# CHECK-BE: beqlrl+ 2 # encoding: [0x4d,0xea,0x00,0x21] +# CHECK-LE: beqlrl+ 2 # encoding: [0x21,0x00,0xea,0x4d] + beqlrl+ 2 +# CHECK-BE: beqlrl+ 0 # encoding: [0x4d,0xe2,0x00,0x21] +# CHECK-LE: beqlrl+ 0 # encoding: [0x21,0x00,0xe2,0x4d] + beqlrl+ +# CHECK-BE: beqctrl+ 2 # encoding: [0x4d,0xea,0x04,0x21] +# CHECK-LE: beqctrl+ 2 # encoding: [0x21,0x04,0xea,0x4d] + beqctrl+ 2 +# CHECK-BE: beqctrl+ 0 # encoding: [0x4d,0xe2,0x04,0x21] +# CHECK-LE: beqctrl+ 0 # encoding: [0x21,0x04,0xe2,0x4d] + beqctrl+ + +# CHECK-BE: beq- 2, target # encoding: [0x41,0xca,A,0bAAAAAA00] +# CHECK-LE: beq- 2, target # encoding: [0bAAAAAA00,A,0xca,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq- 2, target +# CHECK-BE: beq- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA00] +# CHECK-LE: beq- 0, target # encoding: [0bAAAAAA00,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq- target +# CHECK-BE: beqa- 2, target # encoding: [0x41,0xca,A,0bAAAAAA10] +# CHECK-LE: beqa- 2, target # encoding: [0bAAAAAA10,A,0xca,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqa- 2, target +# CHECK-BE: beqa- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA10] +# CHECK-LE: beqa- 0, target # encoding: [0bAAAAAA10,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqa- target +# CHECK-BE: beqlr- 2 # encoding: [0x4d,0xca,0x00,0x20] +# CHECK-LE: beqlr- 2 # encoding: [0x20,0x00,0xca,0x4d] + beqlr- 2 +# CHECK-BE: beqlr- 0 # encoding: [0x4d,0xc2,0x00,0x20] +# CHECK-LE: beqlr- 0 # encoding: [0x20,0x00,0xc2,0x4d] + beqlr- +# CHECK-BE: beqctr- 2 # encoding: [0x4d,0xca,0x04,0x20] +# CHECK-LE: beqctr- 2 # encoding: [0x20,0x04,0xca,0x4d] + beqctr- 2 +# CHECK-BE: beqctr- 0 # encoding: [0x4d,0xc2,0x04,0x20] +# CHECK-LE: beqctr- 0 # encoding: [0x20,0x04,0xc2,0x4d] + beqctr- +# CHECK-BE: beql- 2, target # encoding: [0x41,0xca,A,0bAAAAAA01] +# CHECK-LE: beql- 2, target # encoding: [0bAAAAAA01,A,0xca,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beql- 2, target +# CHECK-BE: beql- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA01] +# CHECK-LE: beql- 0, target # encoding: [0bAAAAAA01,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beql- target +# CHECK-BE: beqla- 2, target # encoding: [0x41,0xca,A,0bAAAAAA11] +# CHECK-LE: beqla- 2, target # encoding: [0bAAAAAA11,A,0xca,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqla- 2, target +# CHECK-BE: beqla- 0, target # encoding: [0x41,0xc2,A,0bAAAAAA11] +# CHECK-LE: beqla- 0, target # encoding: [0bAAAAAA11,A,0xc2,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + beqla- target +# CHECK-BE: beqlrl- 2 # encoding: [0x4d,0xca,0x00,0x21] +# CHECK-LE: beqlrl- 2 # encoding: [0x21,0x00,0xca,0x4d] + beqlrl- 2 +# CHECK-BE: beqlrl- 0 # encoding: [0x4d,0xc2,0x00,0x21] +# CHECK-LE: beqlrl- 0 # encoding: [0x21,0x00,0xc2,0x4d] + beqlrl- +# CHECK-BE: beqctrl- 2 # encoding: [0x4d,0xca,0x04,0x21] +# CHECK-LE: beqctrl- 2 # encoding: [0x21,0x04,0xca,0x4d] + beqctrl- 2 +# CHECK-BE: beqctrl- 0 # encoding: [0x4d,0xc2,0x04,0x21] +# CHECK-LE: beqctrl- 0 # encoding: [0x21,0x04,0xc2,0x4d] + beqctrl- + +# CHECK-BE: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00] +# CHECK-LE: bge 2, target # encoding: [0bAAAAAA00,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge 2, target +# CHECK-BE: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00] +# CHECK-LE: bge 0, target # encoding: [0bAAAAAA00,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge target +# CHECK-BE: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10] +# CHECK-LE: bgea 2, target # encoding: [0bAAAAAA10,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgea 2, target +# CHECK-BE: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10] +# CHECK-LE: bgea 0, target # encoding: [0bAAAAAA10,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgea target +# CHECK-BE: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20] +# CHECK-LE: bgelr 2 # encoding: [0x20,0x00,0x88,0x4c] + bgelr 2 +# CHECK-BE: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20] +# CHECK-LE: bgelr 0 # encoding: [0x20,0x00,0x80,0x4c] + bgelr +# CHECK-BE: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20] +# CHECK-LE: bgectr 2 # encoding: [0x20,0x04,0x88,0x4c] + bgectr 2 +# CHECK-BE: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20] +# CHECK-LE: bgectr 0 # encoding: [0x20,0x04,0x80,0x4c] + bgectr +# CHECK-BE: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01] +# CHECK-LE: bgel 2, target # encoding: [0bAAAAAA01,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgel 2, target +# CHECK-BE: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01] +# CHECK-LE: bgel 0, target # encoding: [0bAAAAAA01,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgel target +# CHECK-BE: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11] +# CHECK-LE: bgela 2, target # encoding: [0bAAAAAA11,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgela 2, target +# CHECK-BE: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11] +# CHECK-LE: bgela 0, target # encoding: [0bAAAAAA11,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgela target +# CHECK-BE: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21] +# CHECK-LE: bgelrl 2 # encoding: [0x21,0x00,0x88,0x4c] + bgelrl 2 +# CHECK-BE: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21] +# CHECK-LE: bgelrl 0 # encoding: [0x21,0x00,0x80,0x4c] + bgelrl +# CHECK-BE: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21] +# CHECK-LE: bgectrl 2 # encoding: [0x21,0x04,0x88,0x4c] + bgectrl 2 +# CHECK-BE: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21] +# CHECK-LE: bgectrl 0 # encoding: [0x21,0x04,0x80,0x4c] + bgectrl + +# CHECK-BE: bge+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA00] +# CHECK-LE: bge+ 2, target # encoding: [0bAAAAAA00,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge+ 2, target +# CHECK-BE: bge+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA00] +# CHECK-LE: bge+ 0, target # encoding: [0bAAAAAA00,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge+ target +# CHECK-BE: bgea+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA10] +# CHECK-LE: bgea+ 2, target # encoding: [0bAAAAAA10,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgea+ 2, target +# CHECK-BE: bgea+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA10] +# CHECK-LE: bgea+ 0, target # encoding: [0bAAAAAA10,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgea+ target +# CHECK-BE: bgelr+ 2 # encoding: [0x4c,0xe8,0x00,0x20] +# CHECK-LE: bgelr+ 2 # encoding: [0x20,0x00,0xe8,0x4c] + bgelr+ 2 +# CHECK-BE: bgelr+ 0 # encoding: [0x4c,0xe0,0x00,0x20] +# CHECK-LE: bgelr+ 0 # encoding: [0x20,0x00,0xe0,0x4c] + bgelr+ +# CHECK-BE: bgectr+ 2 # encoding: [0x4c,0xe8,0x04,0x20] +# CHECK-LE: bgectr+ 2 # encoding: [0x20,0x04,0xe8,0x4c] + bgectr+ 2 +# CHECK-BE: bgectr+ 0 # encoding: [0x4c,0xe0,0x04,0x20] +# CHECK-LE: bgectr+ 0 # encoding: [0x20,0x04,0xe0,0x4c] + bgectr+ +# CHECK-BE: bgel+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA01] +# CHECK-LE: bgel+ 2, target # encoding: [0bAAAAAA01,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgel+ 2, target +# CHECK-BE: bgel+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA01] +# CHECK-LE: bgel+ 0, target # encoding: [0bAAAAAA01,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgel+ target +# CHECK-BE: bgela+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA11] +# CHECK-LE: bgela+ 2, target # encoding: [0bAAAAAA11,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgela+ 2, target +# CHECK-BE: bgela+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA11] +# CHECK-LE: bgela+ 0, target # encoding: [0bAAAAAA11,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgela+ target +# CHECK-BE: bgelrl+ 2 # encoding: [0x4c,0xe8,0x00,0x21] +# CHECK-LE: bgelrl+ 2 # encoding: [0x21,0x00,0xe8,0x4c] + bgelrl+ 2 +# CHECK-BE: bgelrl+ 0 # encoding: [0x4c,0xe0,0x00,0x21] +# CHECK-LE: bgelrl+ 0 # encoding: [0x21,0x00,0xe0,0x4c] + bgelrl+ +# CHECK-BE: bgectrl+ 2 # encoding: [0x4c,0xe8,0x04,0x21] +# CHECK-LE: bgectrl+ 2 # encoding: [0x21,0x04,0xe8,0x4c] + bgectrl+ 2 +# CHECK-BE: bgectrl+ 0 # encoding: [0x4c,0xe0,0x04,0x21] +# CHECK-LE: bgectrl+ 0 # encoding: [0x21,0x04,0xe0,0x4c] + bgectrl+ + +# CHECK-BE: bge- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA00] +# CHECK-LE: bge- 2, target # encoding: [0bAAAAAA00,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge- 2, target +# CHECK-BE: bge- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA00] +# CHECK-LE: bge- 0, target # encoding: [0bAAAAAA00,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge- target +# CHECK-BE: bgea- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA10] +# CHECK-LE: bgea- 2, target # encoding: [0bAAAAAA10,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgea- 2, target +# CHECK-BE: bgea- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA10] +# CHECK-LE: bgea- 0, target # encoding: [0bAAAAAA10,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgea- target +# CHECK-BE: bgelr- 2 # encoding: [0x4c,0xc8,0x00,0x20] +# CHECK-LE: bgelr- 2 # encoding: [0x20,0x00,0xc8,0x4c] + bgelr- 2 +# CHECK-BE: bgelr- 0 # encoding: [0x4c,0xc0,0x00,0x20] +# CHECK-LE: bgelr- 0 # encoding: [0x20,0x00,0xc0,0x4c] + bgelr- +# CHECK-BE: bgectr- 2 # encoding: [0x4c,0xc8,0x04,0x20] +# CHECK-LE: bgectr- 2 # encoding: [0x20,0x04,0xc8,0x4c] + bgectr- 2 +# CHECK-BE: bgectr- 0 # encoding: [0x4c,0xc0,0x04,0x20] +# CHECK-LE: bgectr- 0 # encoding: [0x20,0x04,0xc0,0x4c] + bgectr- +# CHECK-BE: bgel- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA01] +# CHECK-LE: bgel- 2, target # encoding: [0bAAAAAA01,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgel- 2, target +# CHECK-BE: bgel- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA01] +# CHECK-LE: bgel- 0, target # encoding: [0bAAAAAA01,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgel- target +# CHECK-BE: bgela- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA11] +# CHECK-LE: bgela- 2, target # encoding: [0bAAAAAA11,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgela- 2, target +# CHECK-BE: bgela- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA11] +# CHECK-LE: bgela- 0, target # encoding: [0bAAAAAA11,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgela- target +# CHECK-BE: bgelrl- 2 # encoding: [0x4c,0xc8,0x00,0x21] +# CHECK-LE: bgelrl- 2 # encoding: [0x21,0x00,0xc8,0x4c] + bgelrl- 2 +# CHECK-BE: bgelrl- 0 # encoding: [0x4c,0xc0,0x00,0x21] +# CHECK-LE: bgelrl- 0 # encoding: [0x21,0x00,0xc0,0x4c] + bgelrl- +# CHECK-BE: bgectrl- 2 # encoding: [0x4c,0xc8,0x04,0x21] +# CHECK-LE: bgectrl- 2 # encoding: [0x21,0x04,0xc8,0x4c] + bgectrl- 2 +# CHECK-BE: bgectrl- 0 # encoding: [0x4c,0xc0,0x04,0x21] +# CHECK-LE: bgectrl- 0 # encoding: [0x21,0x04,0xc0,0x4c] + bgectrl- + +# CHECK-BE: bgt 2, target # encoding: [0x41,0x89,A,0bAAAAAA00] +# CHECK-LE: bgt 2, target # encoding: [0bAAAAAA00,A,0x89,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt 2, target +# CHECK-BE: bgt 0, target # encoding: [0x41,0x81,A,0bAAAAAA00] +# CHECK-LE: bgt 0, target # encoding: [0bAAAAAA00,A,0x81,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt target +# CHECK-BE: bgta 2, target # encoding: [0x41,0x89,A,0bAAAAAA10] +# CHECK-LE: bgta 2, target # encoding: [0bAAAAAA10,A,0x89,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgta 2, target +# CHECK-BE: bgta 0, target # encoding: [0x41,0x81,A,0bAAAAAA10] +# CHECK-LE: bgta 0, target # encoding: [0bAAAAAA10,A,0x81,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgta target +# CHECK-BE: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20] +# CHECK-LE: bgtlr 2 # encoding: [0x20,0x00,0x89,0x4d] + bgtlr 2 +# CHECK-BE: bgtlr 0 # encoding: [0x4d,0x81,0x00,0x20] +# CHECK-LE: bgtlr 0 # encoding: [0x20,0x00,0x81,0x4d] + bgtlr +# CHECK-BE: bgtctr 2 # encoding: [0x4d,0x89,0x04,0x20] +# CHECK-LE: bgtctr 2 # encoding: [0x20,0x04,0x89,0x4d] + bgtctr 2 +# CHECK-BE: bgtctr 0 # encoding: [0x4d,0x81,0x04,0x20] +# CHECK-LE: bgtctr 0 # encoding: [0x20,0x04,0x81,0x4d] + bgtctr +# CHECK-BE: bgtl 2, target # encoding: [0x41,0x89,A,0bAAAAAA01] +# CHECK-LE: bgtl 2, target # encoding: [0bAAAAAA01,A,0x89,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgtl 2, target +# CHECK-BE: bgtl 0, target # encoding: [0x41,0x81,A,0bAAAAAA01] +# CHECK-LE: bgtl 0, target # encoding: [0bAAAAAA01,A,0x81,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgtl target +# CHECK-BE: bgtla 2, target # encoding: [0x41,0x89,A,0bAAAAAA11] +# CHECK-LE: bgtla 2, target # encoding: [0bAAAAAA11,A,0x89,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgtla 2, target +# CHECK-BE: bgtla 0, target # encoding: [0x41,0x81,A,0bAAAAAA11] +# CHECK-LE: bgtla 0, target # encoding: [0bAAAAAA11,A,0x81,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgtla target +# CHECK-BE: bgtlrl 2 # encoding: [0x4d,0x89,0x00,0x21] +# CHECK-LE: bgtlrl 2 # encoding: [0x21,0x00,0x89,0x4d] + bgtlrl 2 +# CHECK-BE: bgtlrl 0 # encoding: [0x4d,0x81,0x00,0x21] +# CHECK-LE: bgtlrl 0 # encoding: [0x21,0x00,0x81,0x4d] + bgtlrl +# CHECK-BE: bgtctrl 2 # encoding: [0x4d,0x89,0x04,0x21] +# CHECK-LE: bgtctrl 2 # encoding: [0x21,0x04,0x89,0x4d] + bgtctrl 2 +# CHECK-BE: bgtctrl 0 # encoding: [0x4d,0x81,0x04,0x21] +# CHECK-LE: bgtctrl 0 # encoding: [0x21,0x04,0x81,0x4d] + bgtctrl + +# CHECK-BE: bgt+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA00] +# CHECK-LE: bgt+ 2, target # encoding: [0bAAAAAA00,A,0xe9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt+ 2, target +# CHECK-BE: bgt+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA00] +# CHECK-LE: bgt+ 0, target # encoding: [0bAAAAAA00,A,0xe1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt+ target +# CHECK-BE: bgta+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA10] +# CHECK-LE: bgta+ 2, target # encoding: [0bAAAAAA10,A,0xe9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgta+ 2, target +# CHECK-BE: bgta+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA10] +# CHECK-LE: bgta+ 0, target # encoding: [0bAAAAAA10,A,0xe1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgta+ target +# CHECK-BE: bgtlr+ 2 # encoding: [0x4d,0xe9,0x00,0x20] +# CHECK-LE: bgtlr+ 2 # encoding: [0x20,0x00,0xe9,0x4d] + bgtlr+ 2 +# CHECK-BE: bgtlr+ 0 # encoding: [0x4d,0xe1,0x00,0x20] +# CHECK-LE: bgtlr+ 0 # encoding: [0x20,0x00,0xe1,0x4d] + bgtlr+ +# CHECK-BE: bgtctr+ 2 # encoding: [0x4d,0xe9,0x04,0x20] +# CHECK-LE: bgtctr+ 2 # encoding: [0x20,0x04,0xe9,0x4d] + bgtctr+ 2 +# CHECK-BE: bgtctr+ 0 # encoding: [0x4d,0xe1,0x04,0x20] +# CHECK-LE: bgtctr+ 0 # encoding: [0x20,0x04,0xe1,0x4d] + bgtctr+ +# CHECK-BE: bgtl+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA01] +# CHECK-LE: bgtl+ 2, target # encoding: [0bAAAAAA01,A,0xe9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgtl+ 2, target +# CHECK-BE: bgtl+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA01] +# CHECK-LE: bgtl+ 0, target # encoding: [0bAAAAAA01,A,0xe1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgtl+ target +# CHECK-BE: bgtla+ 2, target # encoding: [0x41,0xe9,A,0bAAAAAA11] +# CHECK-LE: bgtla+ 2, target # encoding: [0bAAAAAA11,A,0xe9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgtla+ 2, target +# CHECK-BE: bgtla+ 0, target # encoding: [0x41,0xe1,A,0bAAAAAA11] +# CHECK-LE: bgtla+ 0, target # encoding: [0bAAAAAA11,A,0xe1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgtla+ target +# CHECK-BE: bgtlrl+ 2 # encoding: [0x4d,0xe9,0x00,0x21] +# CHECK-LE: bgtlrl+ 2 # encoding: [0x21,0x00,0xe9,0x4d] + bgtlrl+ 2 +# CHECK-BE: bgtlrl+ 0 # encoding: [0x4d,0xe1,0x00,0x21] +# CHECK-LE: bgtlrl+ 0 # encoding: [0x21,0x00,0xe1,0x4d] + bgtlrl+ +# CHECK-BE: bgtctrl+ 2 # encoding: [0x4d,0xe9,0x04,0x21] +# CHECK-LE: bgtctrl+ 2 # encoding: [0x21,0x04,0xe9,0x4d] + bgtctrl+ 2 +# CHECK-BE: bgtctrl+ 0 # encoding: [0x4d,0xe1,0x04,0x21] +# CHECK-LE: bgtctrl+ 0 # encoding: [0x21,0x04,0xe1,0x4d] + bgtctrl+ + +# CHECK-BE: bgt- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA00] +# CHECK-LE: bgt- 2, target # encoding: [0bAAAAAA00,A,0xc9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt- 2, target +# CHECK-BE: bgt- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA00] +# CHECK-LE: bgt- 0, target # encoding: [0bAAAAAA00,A,0xc1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt- target +# CHECK-BE: bgta- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA10] +# CHECK-LE: bgta- 2, target # encoding: [0bAAAAAA10,A,0xc9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgta- 2, target +# CHECK-BE: bgta- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA10] +# CHECK-LE: bgta- 0, target # encoding: [0bAAAAAA10,A,0xc1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgta- target +# CHECK-BE: bgtlr- 2 # encoding: [0x4d,0xc9,0x00,0x20] +# CHECK-LE: bgtlr- 2 # encoding: [0x20,0x00,0xc9,0x4d] + bgtlr- 2 +# CHECK-BE: bgtlr- 0 # encoding: [0x4d,0xc1,0x00,0x20] +# CHECK-LE: bgtlr- 0 # encoding: [0x20,0x00,0xc1,0x4d] + bgtlr- +# CHECK-BE: bgtctr- 2 # encoding: [0x4d,0xc9,0x04,0x20] +# CHECK-LE: bgtctr- 2 # encoding: [0x20,0x04,0xc9,0x4d] + bgtctr- 2 +# CHECK-BE: bgtctr- 0 # encoding: [0x4d,0xc1,0x04,0x20] +# CHECK-LE: bgtctr- 0 # encoding: [0x20,0x04,0xc1,0x4d] + bgtctr- +# CHECK-BE: bgtl- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA01] +# CHECK-LE: bgtl- 2, target # encoding: [0bAAAAAA01,A,0xc9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgtl- 2, target +# CHECK-BE: bgtl- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA01] +# CHECK-LE: bgtl- 0, target # encoding: [0bAAAAAA01,A,0xc1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgtl- target +# CHECK-BE: bgtla- 2, target # encoding: [0x41,0xc9,A,0bAAAAAA11] +# CHECK-LE: bgtla- 2, target # encoding: [0bAAAAAA11,A,0xc9,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgtla- 2, target +# CHECK-BE: bgtla- 0, target # encoding: [0x41,0xc1,A,0bAAAAAA11] +# CHECK-LE: bgtla- 0, target # encoding: [0bAAAAAA11,A,0xc1,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bgtla- target +# CHECK-BE: bgtlrl- 2 # encoding: [0x4d,0xc9,0x00,0x21] +# CHECK-LE: bgtlrl- 2 # encoding: [0x21,0x00,0xc9,0x4d] + bgtlrl- 2 +# CHECK-BE: bgtlrl- 0 # encoding: [0x4d,0xc1,0x00,0x21] +# CHECK-LE: bgtlrl- 0 # encoding: [0x21,0x00,0xc1,0x4d] + bgtlrl- +# CHECK-BE: bgtctrl- 2 # encoding: [0x4d,0xc9,0x04,0x21] +# CHECK-LE: bgtctrl- 2 # encoding: [0x21,0x04,0xc9,0x4d] + bgtctrl- 2 +# CHECK-BE: bgtctrl- 0 # encoding: [0x4d,0xc1,0x04,0x21] +# CHECK-LE: bgtctrl- 0 # encoding: [0x21,0x04,0xc1,0x4d] + bgtctrl- + +# CHECK-BE: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00] +# CHECK-LE: bge 2, target # encoding: [0bAAAAAA00,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl 2, target +# CHECK-BE: bge 0, target # encoding: [0x40,0x80,A,0bAAAAAA00] +# CHECK-LE: bge 0, target # encoding: [0bAAAAAA00,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl target +# CHECK-BE: bgea 2, target # encoding: [0x40,0x88,A,0bAAAAAA10] +# CHECK-LE: bgea 2, target # encoding: [0bAAAAAA10,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnla 2, target +# CHECK-BE: bgea 0, target # encoding: [0x40,0x80,A,0bAAAAAA10] +# CHECK-LE: bgea 0, target # encoding: [0bAAAAAA10,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnla target +# CHECK-BE: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20] +# CHECK-LE: bgelr 2 # encoding: [0x20,0x00,0x88,0x4c] + bnllr 2 +# CHECK-BE: bgelr 0 # encoding: [0x4c,0x80,0x00,0x20] +# CHECK-LE: bgelr 0 # encoding: [0x20,0x00,0x80,0x4c] + bnllr +# CHECK-BE: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20] +# CHECK-LE: bgectr 2 # encoding: [0x20,0x04,0x88,0x4c] + bnlctr 2 +# CHECK-BE: bgectr 0 # encoding: [0x4c,0x80,0x04,0x20] +# CHECK-LE: bgectr 0 # encoding: [0x20,0x04,0x80,0x4c] + bnlctr +# CHECK-BE: bgel 2, target # encoding: [0x40,0x88,A,0bAAAAAA01] +# CHECK-LE: bgel 2, target # encoding: [0bAAAAAA01,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnll 2, target +# CHECK-BE: bgel 0, target # encoding: [0x40,0x80,A,0bAAAAAA01] +# CHECK-LE: bgel 0, target # encoding: [0bAAAAAA01,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnll target +# CHECK-BE: bgela 2, target # encoding: [0x40,0x88,A,0bAAAAAA11] +# CHECK-LE: bgela 2, target # encoding: [0bAAAAAA11,A,0x88,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnlla 2, target +# CHECK-BE: bgela 0, target # encoding: [0x40,0x80,A,0bAAAAAA11] +# CHECK-LE: bgela 0, target # encoding: [0bAAAAAA11,A,0x80,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnlla target +# CHECK-BE: bgelrl 2 # encoding: [0x4c,0x88,0x00,0x21] +# CHECK-LE: bgelrl 2 # encoding: [0x21,0x00,0x88,0x4c] + bnllrl 2 +# CHECK-BE: bgelrl 0 # encoding: [0x4c,0x80,0x00,0x21] +# CHECK-LE: bgelrl 0 # encoding: [0x21,0x00,0x80,0x4c] + bnllrl +# CHECK-BE: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21] +# CHECK-LE: bgectrl 2 # encoding: [0x21,0x04,0x88,0x4c] + bnlctrl 2 +# CHECK-BE: bgectrl 0 # encoding: [0x4c,0x80,0x04,0x21] +# CHECK-LE: bgectrl 0 # encoding: [0x21,0x04,0x80,0x4c] + bnlctrl + +# CHECK-BE: bge+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA00] +# CHECK-LE: bge+ 2, target # encoding: [0bAAAAAA00,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl+ 2, target +# CHECK-BE: bge+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA00] +# CHECK-LE: bge+ 0, target # encoding: [0bAAAAAA00,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl+ target +# CHECK-BE: bgea+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA10] +# CHECK-LE: bgea+ 2, target # encoding: [0bAAAAAA10,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnla+ 2, target +# CHECK-BE: bgea+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA10] +# CHECK-LE: bgea+ 0, target # encoding: [0bAAAAAA10,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnla+ target +# CHECK-BE: bgelr+ 2 # encoding: [0x4c,0xe8,0x00,0x20] +# CHECK-LE: bgelr+ 2 # encoding: [0x20,0x00,0xe8,0x4c] + bnllr+ 2 +# CHECK-BE: bgelr+ 0 # encoding: [0x4c,0xe0,0x00,0x20] +# CHECK-LE: bgelr+ 0 # encoding: [0x20,0x00,0xe0,0x4c] + bnllr+ +# CHECK-BE: bgectr+ 2 # encoding: [0x4c,0xe8,0x04,0x20] +# CHECK-LE: bgectr+ 2 # encoding: [0x20,0x04,0xe8,0x4c] + bnlctr+ 2 +# CHECK-BE: bgectr+ 0 # encoding: [0x4c,0xe0,0x04,0x20] +# CHECK-LE: bgectr+ 0 # encoding: [0x20,0x04,0xe0,0x4c] + bnlctr+ +# CHECK-BE: bgel+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA01] +# CHECK-LE: bgel+ 2, target # encoding: [0bAAAAAA01,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnll+ 2, target +# CHECK-BE: bgel+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA01] +# CHECK-LE: bgel+ 0, target # encoding: [0bAAAAAA01,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnll+ target +# CHECK-BE: bgela+ 2, target # encoding: [0x40,0xe8,A,0bAAAAAA11] +# CHECK-LE: bgela+ 2, target # encoding: [0bAAAAAA11,A,0xe8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnlla+ 2, target +# CHECK-BE: bgela+ 0, target # encoding: [0x40,0xe0,A,0bAAAAAA11] +# CHECK-LE: bgela+ 0, target # encoding: [0bAAAAAA11,A,0xe0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnlla+ target +# CHECK-BE: bgelrl+ 2 # encoding: [0x4c,0xe8,0x00,0x21] +# CHECK-LE: bgelrl+ 2 # encoding: [0x21,0x00,0xe8,0x4c] + bnllrl+ 2 +# CHECK-BE: bgelrl+ 0 # encoding: [0x4c,0xe0,0x00,0x21] +# CHECK-LE: bgelrl+ 0 # encoding: [0x21,0x00,0xe0,0x4c] + bnllrl+ +# CHECK-BE: bgectrl+ 2 # encoding: [0x4c,0xe8,0x04,0x21] +# CHECK-LE: bgectrl+ 2 # encoding: [0x21,0x04,0xe8,0x4c] + bnlctrl+ 2 +# CHECK-BE: bgectrl+ 0 # encoding: [0x4c,0xe0,0x04,0x21] +# CHECK-LE: bgectrl+ 0 # encoding: [0x21,0x04,0xe0,0x4c] + bnlctrl+ + +# CHECK-BE: bge- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA00] +# CHECK-LE: bge- 2, target # encoding: [0bAAAAAA00,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl- 2, target +# CHECK-BE: bge- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA00] +# CHECK-LE: bge- 0, target # encoding: [0bAAAAAA00,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl- target +# CHECK-BE: bgea- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA10] +# CHECK-LE: bgea- 2, target # encoding: [0bAAAAAA10,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnla- 2, target +# CHECK-BE: bgea- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA10] +# CHECK-LE: bgea- 0, target # encoding: [0bAAAAAA10,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnla- target +# CHECK-BE: bgelr- 2 # encoding: [0x4c,0xc8,0x00,0x20] +# CHECK-LE: bgelr- 2 # encoding: [0x20,0x00,0xc8,0x4c] + bnllr- 2 +# CHECK-BE: bgelr- 0 # encoding: [0x4c,0xc0,0x00,0x20] +# CHECK-LE: bgelr- 0 # encoding: [0x20,0x00,0xc0,0x4c] + bnllr- +# CHECK-BE: bgectr- 2 # encoding: [0x4c,0xc8,0x04,0x20] +# CHECK-LE: bgectr- 2 # encoding: [0x20,0x04,0xc8,0x4c] + bnlctr- 2 +# CHECK-BE: bgectr- 0 # encoding: [0x4c,0xc0,0x04,0x20] +# CHECK-LE: bgectr- 0 # encoding: [0x20,0x04,0xc0,0x4c] + bnlctr- +# CHECK-BE: bgel- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA01] +# CHECK-LE: bgel- 2, target # encoding: [0bAAAAAA01,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnll- 2, target +# CHECK-BE: bgel- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA01] +# CHECK-LE: bgel- 0, target # encoding: [0bAAAAAA01,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnll- target +# CHECK-BE: bgela- 2, target # encoding: [0x40,0xc8,A,0bAAAAAA11] +# CHECK-LE: bgela- 2, target # encoding: [0bAAAAAA11,A,0xc8,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnlla- 2, target +# CHECK-BE: bgela- 0, target # encoding: [0x40,0xc0,A,0bAAAAAA11] +# CHECK-LE: bgela- 0, target # encoding: [0bAAAAAA11,A,0xc0,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnlla- target +# CHECK-BE: bgelrl- 2 # encoding: [0x4c,0xc8,0x00,0x21] +# CHECK-LE: bgelrl- 2 # encoding: [0x21,0x00,0xc8,0x4c] + bnllrl- 2 +# CHECK-BE: bgelrl- 0 # encoding: [0x4c,0xc0,0x00,0x21] +# CHECK-LE: bgelrl- 0 # encoding: [0x21,0x00,0xc0,0x4c] + bnllrl- +# CHECK-BE: bgectrl- 2 # encoding: [0x4c,0xc8,0x04,0x21] +# CHECK-LE: bgectrl- 2 # encoding: [0x21,0x04,0xc8,0x4c] + bnlctrl- 2 +# CHECK-BE: bgectrl- 0 # encoding: [0x4c,0xc0,0x04,0x21] +# CHECK-LE: bgectrl- 0 # encoding: [0x21,0x04,0xc0,0x4c] + bnlctrl- + +# CHECK-BE: bne 2, target # encoding: [0x40,0x8a,A,0bAAAAAA00] +# CHECK-LE: bne 2, target # encoding: [0bAAAAAA00,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne 2, target +# CHECK-BE: bne 0, target # encoding: [0x40,0x82,A,0bAAAAAA00] +# CHECK-LE: bne 0, target # encoding: [0bAAAAAA00,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne target +# CHECK-BE: bnea 2, target # encoding: [0x40,0x8a,A,0bAAAAAA10] +# CHECK-LE: bnea 2, target # encoding: [0bAAAAAA10,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnea 2, target +# CHECK-BE: bnea 0, target # encoding: [0x40,0x82,A,0bAAAAAA10] +# CHECK-LE: bnea 0, target # encoding: [0bAAAAAA10,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnea target +# CHECK-BE: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20] +# CHECK-LE: bnelr 2 # encoding: [0x20,0x00,0x8a,0x4c] + bnelr 2 +# CHECK-BE: bnelr 0 # encoding: [0x4c,0x82,0x00,0x20] +# CHECK-LE: bnelr 0 # encoding: [0x20,0x00,0x82,0x4c] + bnelr +# CHECK-BE: bnectr 2 # encoding: [0x4c,0x8a,0x04,0x20] +# CHECK-LE: bnectr 2 # encoding: [0x20,0x04,0x8a,0x4c] + bnectr 2 +# CHECK-BE: bnectr 0 # encoding: [0x4c,0x82,0x04,0x20] +# CHECK-LE: bnectr 0 # encoding: [0x20,0x04,0x82,0x4c] + bnectr +# CHECK-BE: bnel 2, target # encoding: [0x40,0x8a,A,0bAAAAAA01] +# CHECK-LE: bnel 2, target # encoding: [0bAAAAAA01,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnel 2, target +# CHECK-BE: bnel 0, target # encoding: [0x40,0x82,A,0bAAAAAA01] +# CHECK-LE: bnel 0, target # encoding: [0bAAAAAA01,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnel target +# CHECK-BE: bnela 2, target # encoding: [0x40,0x8a,A,0bAAAAAA11] +# CHECK-LE: bnela 2, target # encoding: [0bAAAAAA11,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnela 2, target +# CHECK-BE: bnela 0, target # encoding: [0x40,0x82,A,0bAAAAAA11] +# CHECK-LE: bnela 0, target # encoding: [0bAAAAAA11,A,0x82,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnela target +# CHECK-BE: bnelrl 2 # encoding: [0x4c,0x8a,0x00,0x21] +# CHECK-LE: bnelrl 2 # encoding: [0x21,0x00,0x8a,0x4c] + bnelrl 2 +# CHECK-BE: bnelrl 0 # encoding: [0x4c,0x82,0x00,0x21] +# CHECK-LE: bnelrl 0 # encoding: [0x21,0x00,0x82,0x4c] + bnelrl +# CHECK-BE: bnectrl 2 # encoding: [0x4c,0x8a,0x04,0x21] +# CHECK-LE: bnectrl 2 # encoding: [0x21,0x04,0x8a,0x4c] + bnectrl 2 +# CHECK-BE: bnectrl 0 # encoding: [0x4c,0x82,0x04,0x21] +# CHECK-LE: bnectrl 0 # encoding: [0x21,0x04,0x82,0x4c] + bnectrl + +# CHECK-BE: bne+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA00] +# CHECK-LE: bne+ 2, target # encoding: [0bAAAAAA00,A,0xea,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne+ 2, target +# CHECK-BE: bne+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA00] +# CHECK-LE: bne+ 0, target # encoding: [0bAAAAAA00,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne+ target +# CHECK-BE: bnea+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA10] +# CHECK-LE: bnea+ 2, target # encoding: [0bAAAAAA10,A,0xea,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnea+ 2, target +# CHECK-BE: bnea+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA10] +# CHECK-LE: bnea+ 0, target # encoding: [0bAAAAAA10,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnea+ target +# CHECK-BE: bnelr+ 2 # encoding: [0x4c,0xea,0x00,0x20] +# CHECK-LE: bnelr+ 2 # encoding: [0x20,0x00,0xea,0x4c] + bnelr+ 2 +# CHECK-BE: bnelr+ 0 # encoding: [0x4c,0xe2,0x00,0x20] +# CHECK-LE: bnelr+ 0 # encoding: [0x20,0x00,0xe2,0x4c] + bnelr+ +# CHECK-BE: bnectr+ 2 # encoding: [0x4c,0xea,0x04,0x20] +# CHECK-LE: bnectr+ 2 # encoding: [0x20,0x04,0xea,0x4c] + bnectr+ 2 +# CHECK-BE: bnectr+ 0 # encoding: [0x4c,0xe2,0x04,0x20] +# CHECK-LE: bnectr+ 0 # encoding: [0x20,0x04,0xe2,0x4c] + bnectr+ +# CHECK-BE: bnel+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA01] +# CHECK-LE: bnel+ 2, target # encoding: [0bAAAAAA01,A,0xea,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnel+ 2, target +# CHECK-BE: bnel+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA01] +# CHECK-LE: bnel+ 0, target # encoding: [0bAAAAAA01,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnel+ target +# CHECK-BE: bnela+ 2, target # encoding: [0x40,0xea,A,0bAAAAAA11] +# CHECK-LE: bnela+ 2, target # encoding: [0bAAAAAA11,A,0xea,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnela+ 2, target +# CHECK-BE: bnela+ 0, target # encoding: [0x40,0xe2,A,0bAAAAAA11] +# CHECK-LE: bnela+ 0, target # encoding: [0bAAAAAA11,A,0xe2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnela+ target +# CHECK-BE: bnelrl+ 2 # encoding: [0x4c,0xea,0x00,0x21] +# CHECK-LE: bnelrl+ 2 # encoding: [0x21,0x00,0xea,0x4c] + bnelrl+ 2 +# CHECK-BE: bnelrl+ 0 # encoding: [0x4c,0xe2,0x00,0x21] +# CHECK-LE: bnelrl+ 0 # encoding: [0x21,0x00,0xe2,0x4c] + bnelrl+ +# CHECK-BE: bnectrl+ 2 # encoding: [0x4c,0xea,0x04,0x21] +# CHECK-LE: bnectrl+ 2 # encoding: [0x21,0x04,0xea,0x4c] + bnectrl+ 2 +# CHECK-BE: bnectrl+ 0 # encoding: [0x4c,0xe2,0x04,0x21] +# CHECK-LE: bnectrl+ 0 # encoding: [0x21,0x04,0xe2,0x4c] + bnectrl+ + +# CHECK-BE: bne- 2, target # encoding: [0x40,0xca,A,0bAAAAAA00] +# CHECK-LE: bne- 2, target # encoding: [0bAAAAAA00,A,0xca,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne- 2, target +# CHECK-BE: bne- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA00] +# CHECK-LE: bne- 0, target # encoding: [0bAAAAAA00,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne- target +# CHECK-BE: bnea- 2, target # encoding: [0x40,0xca,A,0bAAAAAA10] +# CHECK-LE: bnea- 2, target # encoding: [0bAAAAAA10,A,0xca,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnea- 2, target +# CHECK-BE: bnea- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA10] +# CHECK-LE: bnea- 0, target # encoding: [0bAAAAAA10,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnea- target +# CHECK-BE: bnelr- 2 # encoding: [0x4c,0xca,0x00,0x20] +# CHECK-LE: bnelr- 2 # encoding: [0x20,0x00,0xca,0x4c] + bnelr- 2 +# CHECK-BE: bnelr- 0 # encoding: [0x4c,0xc2,0x00,0x20] +# CHECK-LE: bnelr- 0 # encoding: [0x20,0x00,0xc2,0x4c] + bnelr- +# CHECK-BE: bnectr- 2 # encoding: [0x4c,0xca,0x04,0x20] +# CHECK-LE: bnectr- 2 # encoding: [0x20,0x04,0xca,0x4c] + bnectr- 2 +# CHECK-BE: bnectr- 0 # encoding: [0x4c,0xc2,0x04,0x20] +# CHECK-LE: bnectr- 0 # encoding: [0x20,0x04,0xc2,0x4c] + bnectr- +# CHECK-BE: bnel- 2, target # encoding: [0x40,0xca,A,0bAAAAAA01] +# CHECK-LE: bnel- 2, target # encoding: [0bAAAAAA01,A,0xca,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnel- 2, target +# CHECK-BE: bnel- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA01] +# CHECK-LE: bnel- 0, target # encoding: [0bAAAAAA01,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnel- target +# CHECK-BE: bnela- 2, target # encoding: [0x40,0xca,A,0bAAAAAA11] +# CHECK-LE: bnela- 2, target # encoding: [0bAAAAAA11,A,0xca,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnela- 2, target +# CHECK-BE: bnela- 0, target # encoding: [0x40,0xc2,A,0bAAAAAA11] +# CHECK-LE: bnela- 0, target # encoding: [0bAAAAAA11,A,0xc2,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnela- target +# CHECK-BE: bnelrl- 2 # encoding: [0x4c,0xca,0x00,0x21] +# CHECK-LE: bnelrl- 2 # encoding: [0x21,0x00,0xca,0x4c] + bnelrl- 2 +# CHECK-BE: bnelrl- 0 # encoding: [0x4c,0xc2,0x00,0x21] +# CHECK-LE: bnelrl- 0 # encoding: [0x21,0x00,0xc2,0x4c] + bnelrl- +# CHECK-BE: bnectrl- 2 # encoding: [0x4c,0xca,0x04,0x21] +# CHECK-LE: bnectrl- 2 # encoding: [0x21,0x04,0xca,0x4c] + bnectrl- 2 +# CHECK-BE: bnectrl- 0 # encoding: [0x4c,0xc2,0x04,0x21] +# CHECK-LE: bnectrl- 0 # encoding: [0x21,0x04,0xc2,0x4c] + bnectrl- + +# CHECK-BE: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00] +# CHECK-LE: ble 2, target # encoding: [0bAAAAAA00,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng 2, target +# CHECK-BE: ble 0, target # encoding: [0x40,0x81,A,0bAAAAAA00] +# CHECK-LE: ble 0, target # encoding: [0bAAAAAA00,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng target +# CHECK-BE: blea 2, target # encoding: [0x40,0x89,A,0bAAAAAA10] +# CHECK-LE: blea 2, target # encoding: [0bAAAAAA10,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnga 2, target +# CHECK-BE: blea 0, target # encoding: [0x40,0x81,A,0bAAAAAA10] +# CHECK-LE: blea 0, target # encoding: [0bAAAAAA10,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnga target +# CHECK-BE: blelr 2 # encoding: [0x4c,0x89,0x00,0x20] +# CHECK-LE: blelr 2 # encoding: [0x20,0x00,0x89,0x4c] + bnglr 2 +# CHECK-BE: blelr 0 # encoding: [0x4c,0x81,0x00,0x20] +# CHECK-LE: blelr 0 # encoding: [0x20,0x00,0x81,0x4c] + bnglr +# CHECK-BE: blectr 2 # encoding: [0x4c,0x89,0x04,0x20] +# CHECK-LE: blectr 2 # encoding: [0x20,0x04,0x89,0x4c] + bngctr 2 +# CHECK-BE: blectr 0 # encoding: [0x4c,0x81,0x04,0x20] +# CHECK-LE: blectr 0 # encoding: [0x20,0x04,0x81,0x4c] + bngctr +# CHECK-BE: blel 2, target # encoding: [0x40,0x89,A,0bAAAAAA01] +# CHECK-LE: blel 2, target # encoding: [0bAAAAAA01,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bngl 2, target +# CHECK-BE: blel 0, target # encoding: [0x40,0x81,A,0bAAAAAA01] +# CHECK-LE: blel 0, target # encoding: [0bAAAAAA01,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bngl target +# CHECK-BE: blela 2, target # encoding: [0x40,0x89,A,0bAAAAAA11] +# CHECK-LE: blela 2, target # encoding: [0bAAAAAA11,A,0x89,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bngla 2, target +# CHECK-BE: blela 0, target # encoding: [0x40,0x81,A,0bAAAAAA11] +# CHECK-LE: blela 0, target # encoding: [0bAAAAAA11,A,0x81,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bngla target +# CHECK-BE: blelrl 2 # encoding: [0x4c,0x89,0x00,0x21] +# CHECK-LE: blelrl 2 # encoding: [0x21,0x00,0x89,0x4c] + bnglrl 2 +# CHECK-BE: blelrl 0 # encoding: [0x4c,0x81,0x00,0x21] +# CHECK-LE: blelrl 0 # encoding: [0x21,0x00,0x81,0x4c] + bnglrl +# CHECK-BE: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21] +# CHECK-LE: blectrl 2 # encoding: [0x21,0x04,0x89,0x4c] + bngctrl 2 +# CHECK-BE: blectrl 0 # encoding: [0x4c,0x81,0x04,0x21] +# CHECK-LE: blectrl 0 # encoding: [0x21,0x04,0x81,0x4c] + bngctrl + +# CHECK-BE: ble+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA00] +# CHECK-LE: ble+ 2, target # encoding: [0bAAAAAA00,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng+ 2, target +# CHECK-BE: ble+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA00] +# CHECK-LE: ble+ 0, target # encoding: [0bAAAAAA00,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng+ target +# CHECK-BE: blea+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA10] +# CHECK-LE: blea+ 2, target # encoding: [0bAAAAAA10,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnga+ 2, target +# CHECK-BE: blea+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA10] +# CHECK-LE: blea+ 0, target # encoding: [0bAAAAAA10,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnga+ target +# CHECK-BE: blelr+ 2 # encoding: [0x4c,0xe9,0x00,0x20] +# CHECK-LE: blelr+ 2 # encoding: [0x20,0x00,0xe9,0x4c] + bnglr+ 2 +# CHECK-BE: blelr+ 0 # encoding: [0x4c,0xe1,0x00,0x20] +# CHECK-LE: blelr+ 0 # encoding: [0x20,0x00,0xe1,0x4c] + bnglr+ +# CHECK-BE: blectr+ 2 # encoding: [0x4c,0xe9,0x04,0x20] +# CHECK-LE: blectr+ 2 # encoding: [0x20,0x04,0xe9,0x4c] + bngctr+ 2 +# CHECK-BE: blectr+ 0 # encoding: [0x4c,0xe1,0x04,0x20] +# CHECK-LE: blectr+ 0 # encoding: [0x20,0x04,0xe1,0x4c] + bngctr+ +# CHECK-BE: blel+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA01] +# CHECK-LE: blel+ 2, target # encoding: [0bAAAAAA01,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bngl+ 2, target +# CHECK-BE: blel+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA01] +# CHECK-LE: blel+ 0, target # encoding: [0bAAAAAA01,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bngl+ target +# CHECK-BE: blela+ 2, target # encoding: [0x40,0xe9,A,0bAAAAAA11] +# CHECK-LE: blela+ 2, target # encoding: [0bAAAAAA11,A,0xe9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bngla+ 2, target +# CHECK-BE: blela+ 0, target # encoding: [0x40,0xe1,A,0bAAAAAA11] +# CHECK-LE: blela+ 0, target # encoding: [0bAAAAAA11,A,0xe1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bngla+ target +# CHECK-BE: blelrl+ 2 # encoding: [0x4c,0xe9,0x00,0x21] +# CHECK-LE: blelrl+ 2 # encoding: [0x21,0x00,0xe9,0x4c] + bnglrl+ 2 +# CHECK-BE: blelrl+ 0 # encoding: [0x4c,0xe1,0x00,0x21] +# CHECK-LE: blelrl+ 0 # encoding: [0x21,0x00,0xe1,0x4c] + bnglrl+ +# CHECK-BE: blectrl+ 2 # encoding: [0x4c,0xe9,0x04,0x21] +# CHECK-LE: blectrl+ 2 # encoding: [0x21,0x04,0xe9,0x4c] + bngctrl+ 2 +# CHECK-BE: blectrl+ 0 # encoding: [0x4c,0xe1,0x04,0x21] +# CHECK-LE: blectrl+ 0 # encoding: [0x21,0x04,0xe1,0x4c] + bngctrl+ + +# CHECK-BE: ble- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA00] +# CHECK-LE: ble- 2, target # encoding: [0bAAAAAA00,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng- 2, target +# CHECK-BE: ble- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA00] +# CHECK-LE: ble- 0, target # encoding: [0bAAAAAA00,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng- target +# CHECK-BE: blea- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA10] +# CHECK-LE: blea- 2, target # encoding: [0bAAAAAA10,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnga- 2, target +# CHECK-BE: blea- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA10] +# CHECK-LE: blea- 0, target # encoding: [0bAAAAAA10,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnga- target +# CHECK-BE: blelr- 2 # encoding: [0x4c,0xc9,0x00,0x20] +# CHECK-LE: blelr- 2 # encoding: [0x20,0x00,0xc9,0x4c] + bnglr- 2 +# CHECK-BE: blelr- 0 # encoding: [0x4c,0xc1,0x00,0x20] +# CHECK-LE: blelr- 0 # encoding: [0x20,0x00,0xc1,0x4c] + bnglr- +# CHECK-BE: blectr- 2 # encoding: [0x4c,0xc9,0x04,0x20] +# CHECK-LE: blectr- 2 # encoding: [0x20,0x04,0xc9,0x4c] + bngctr- 2 +# CHECK-BE: blectr- 0 # encoding: [0x4c,0xc1,0x04,0x20] +# CHECK-LE: blectr- 0 # encoding: [0x20,0x04,0xc1,0x4c] + bngctr- +# CHECK-BE: blel- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA01] +# CHECK-LE: blel- 2, target # encoding: [0bAAAAAA01,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bngl- 2, target +# CHECK-BE: blel- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA01] +# CHECK-LE: blel- 0, target # encoding: [0bAAAAAA01,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bngl- target +# CHECK-BE: blela- 2, target # encoding: [0x40,0xc9,A,0bAAAAAA11] +# CHECK-LE: blela- 2, target # encoding: [0bAAAAAA11,A,0xc9,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bngla- 2, target +# CHECK-BE: blela- 0, target # encoding: [0x40,0xc1,A,0bAAAAAA11] +# CHECK-LE: blela- 0, target # encoding: [0bAAAAAA11,A,0xc1,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bngla- target +# CHECK-BE: blelrl- 2 # encoding: [0x4c,0xc9,0x00,0x21] +# CHECK-LE: blelrl- 2 # encoding: [0x21,0x00,0xc9,0x4c] + bnglrl- 2 +# CHECK-BE: blelrl- 0 # encoding: [0x4c,0xc1,0x00,0x21] +# CHECK-LE: blelrl- 0 # encoding: [0x21,0x00,0xc1,0x4c] + bnglrl- +# CHECK-BE: blectrl- 2 # encoding: [0x4c,0xc9,0x04,0x21] +# CHECK-LE: blectrl- 2 # encoding: [0x21,0x04,0xc9,0x4c] + bngctrl- 2 +# CHECK-BE: blectrl- 0 # encoding: [0x4c,0xc1,0x04,0x21] +# CHECK-LE: blectrl- 0 # encoding: [0x21,0x04,0xc1,0x4c] + bngctrl- + +# CHECK-BE: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00] +# CHECK-LE: bun 2, target # encoding: [0bAAAAAA00,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso 2, target +# CHECK-BE: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00] +# CHECK-LE: bun 0, target # encoding: [0bAAAAAA00,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso target +# CHECK-BE: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10] +# CHECK-LE: buna 2, target # encoding: [0bAAAAAA10,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsoa 2, target +# CHECK-BE: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10] +# CHECK-LE: buna 0, target # encoding: [0bAAAAAA10,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsoa target +# CHECK-BE: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20] +# CHECK-LE: bunlr 2 # encoding: [0x20,0x00,0x8b,0x4d] + bsolr 2 +# CHECK-BE: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20] +# CHECK-LE: bunlr 0 # encoding: [0x20,0x00,0x83,0x4d] + bsolr +# CHECK-BE: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20] +# CHECK-LE: bunctr 2 # encoding: [0x20,0x04,0x8b,0x4d] + bsoctr 2 +# CHECK-BE: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20] +# CHECK-LE: bunctr 0 # encoding: [0x20,0x04,0x83,0x4d] + bsoctr +# CHECK-BE: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01] +# CHECK-LE: bunl 2, target # encoding: [0bAAAAAA01,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bsol 2, target +# CHECK-BE: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01] +# CHECK-LE: bunl 0, target # encoding: [0bAAAAAA01,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bsol target +# CHECK-BE: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11] +# CHECK-LE: bunla 2, target # encoding: [0bAAAAAA11,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsola 2, target +# CHECK-BE: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11] +# CHECK-LE: bunla 0, target # encoding: [0bAAAAAA11,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsola target +# CHECK-BE: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21] +# CHECK-LE: bunlrl 2 # encoding: [0x21,0x00,0x8b,0x4d] + bsolrl 2 +# CHECK-BE: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21] +# CHECK-LE: bunlrl 0 # encoding: [0x21,0x00,0x83,0x4d] + bsolrl +# CHECK-BE: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21] +# CHECK-LE: bunctrl 2 # encoding: [0x21,0x04,0x8b,0x4d] + bsoctrl 2 +# CHECK-BE: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21] +# CHECK-LE: bunctrl 0 # encoding: [0x21,0x04,0x83,0x4d] + bsoctrl + +# CHECK-BE: bun+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA00] +# CHECK-LE: bun+ 2, target # encoding: [0bAAAAAA00,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso+ 2, target +# CHECK-BE: bun+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA00] +# CHECK-LE: bun+ 0, target # encoding: [0bAAAAAA00,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso+ target +# CHECK-BE: buna+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA10] +# CHECK-LE: buna+ 2, target # encoding: [0bAAAAAA10,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsoa+ 2, target +# CHECK-BE: buna+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA10] +# CHECK-LE: buna+ 0, target # encoding: [0bAAAAAA10,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsoa+ target +# CHECK-BE: bunlr+ 2 # encoding: [0x4d,0xeb,0x00,0x20] +# CHECK-LE: bunlr+ 2 # encoding: [0x20,0x00,0xeb,0x4d] + bsolr+ 2 +# CHECK-BE: bunlr+ 0 # encoding: [0x4d,0xe3,0x00,0x20] +# CHECK-LE: bunlr+ 0 # encoding: [0x20,0x00,0xe3,0x4d] + bsolr+ +# CHECK-BE: bunctr+ 2 # encoding: [0x4d,0xeb,0x04,0x20] +# CHECK-LE: bunctr+ 2 # encoding: [0x20,0x04,0xeb,0x4d] + bsoctr+ 2 +# CHECK-BE: bunctr+ 0 # encoding: [0x4d,0xe3,0x04,0x20] +# CHECK-LE: bunctr+ 0 # encoding: [0x20,0x04,0xe3,0x4d] + bsoctr+ +# CHECK-BE: bunl+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA01] +# CHECK-LE: bunl+ 2, target # encoding: [0bAAAAAA01,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bsol+ 2, target +# CHECK-BE: bunl+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA01] +# CHECK-LE: bunl+ 0, target # encoding: [0bAAAAAA01,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bsol+ target +# CHECK-BE: bunla+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA11] +# CHECK-LE: bunla+ 2, target # encoding: [0bAAAAAA11,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsola+ 2, target +# CHECK-BE: bunla+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA11] +# CHECK-LE: bunla+ 0, target # encoding: [0bAAAAAA11,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsola+ target +# CHECK-BE: bunlrl+ 2 # encoding: [0x4d,0xeb,0x00,0x21] +# CHECK-LE: bunlrl+ 2 # encoding: [0x21,0x00,0xeb,0x4d] + bsolrl+ 2 +# CHECK-BE: bunlrl+ 0 # encoding: [0x4d,0xe3,0x00,0x21] +# CHECK-LE: bunlrl+ 0 # encoding: [0x21,0x00,0xe3,0x4d] + bsolrl+ +# CHECK-BE: bunctrl+ 2 # encoding: [0x4d,0xeb,0x04,0x21] +# CHECK-LE: bunctrl+ 2 # encoding: [0x21,0x04,0xeb,0x4d] + bsoctrl+ 2 +# CHECK-BE: bunctrl+ 0 # encoding: [0x4d,0xe3,0x04,0x21] +# CHECK-LE: bunctrl+ 0 # encoding: [0x21,0x04,0xe3,0x4d] + bsoctrl+ + +# CHECK-BE: bun- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA00] +# CHECK-LE: bun- 2, target # encoding: [0bAAAAAA00,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso- 2, target +# CHECK-BE: bun- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA00] +# CHECK-LE: bun- 0, target # encoding: [0bAAAAAA00,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso- target +# CHECK-BE: buna- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA10] +# CHECK-LE: buna- 2, target # encoding: [0bAAAAAA10,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsoa- 2, target +# CHECK-BE: buna- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA10] +# CHECK-LE: buna- 0, target # encoding: [0bAAAAAA10,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsoa- target +# CHECK-BE: bunlr- 2 # encoding: [0x4d,0xcb,0x00,0x20] +# CHECK-LE: bunlr- 2 # encoding: [0x20,0x00,0xcb,0x4d] + bsolr- 2 +# CHECK-BE: bunlr- 0 # encoding: [0x4d,0xc3,0x00,0x20] +# CHECK-LE: bunlr- 0 # encoding: [0x20,0x00,0xc3,0x4d] + bsolr- +# CHECK-BE: bunctr- 2 # encoding: [0x4d,0xcb,0x04,0x20] +# CHECK-LE: bunctr- 2 # encoding: [0x20,0x04,0xcb,0x4d] + bsoctr- 2 +# CHECK-BE: bunctr- 0 # encoding: [0x4d,0xc3,0x04,0x20] +# CHECK-LE: bunctr- 0 # encoding: [0x20,0x04,0xc3,0x4d] + bsoctr- +# CHECK-BE: bunl- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA01] +# CHECK-LE: bunl- 2, target # encoding: [0bAAAAAA01,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bsol- 2, target +# CHECK-BE: bunl- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA01] +# CHECK-LE: bunl- 0, target # encoding: [0bAAAAAA01,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bsol- target +# CHECK-BE: bunla- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA11] +# CHECK-LE: bunla- 2, target # encoding: [0bAAAAAA11,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsola- 2, target +# CHECK-BE: bunla- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA11] +# CHECK-LE: bunla- 0, target # encoding: [0bAAAAAA11,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bsola- target +# CHECK-BE: bunlrl- 2 # encoding: [0x4d,0xcb,0x00,0x21] +# CHECK-LE: bunlrl- 2 # encoding: [0x21,0x00,0xcb,0x4d] + bsolrl- 2 +# CHECK-BE: bunlrl- 0 # encoding: [0x4d,0xc3,0x00,0x21] +# CHECK-LE: bunlrl- 0 # encoding: [0x21,0x00,0xc3,0x4d] + bsolrl- +# CHECK-BE: bunctrl- 2 # encoding: [0x4d,0xcb,0x04,0x21] +# CHECK-LE: bunctrl- 2 # encoding: [0x21,0x04,0xcb,0x4d] + bsoctrl- 2 +# CHECK-BE: bunctrl- 0 # encoding: [0x4d,0xc3,0x04,0x21] +# CHECK-LE: bunctrl- 0 # encoding: [0x21,0x04,0xc3,0x4d] + bsoctrl- + +# CHECK-BE: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00] +# CHECK-LE: bnu 2, target # encoding: [0bAAAAAA00,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns 2, target +# CHECK-BE: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00] +# CHECK-LE: bnu 0, target # encoding: [0bAAAAAA00,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns target +# CHECK-BE: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10] +# CHECK-LE: bnua 2, target # encoding: [0bAAAAAA10,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsa 2, target +# CHECK-BE: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10] +# CHECK-LE: bnua 0, target # encoding: [0bAAAAAA10,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsa target +# CHECK-BE: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20] +# CHECK-LE: bnulr 2 # encoding: [0x20,0x00,0x8b,0x4c] + bnslr 2 +# CHECK-BE: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20] +# CHECK-LE: bnulr 0 # encoding: [0x20,0x00,0x83,0x4c] + bnslr +# CHECK-BE: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20] +# CHECK-LE: bnuctr 2 # encoding: [0x20,0x04,0x8b,0x4c] + bnsctr 2 +# CHECK-BE: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20] +# CHECK-LE: bnuctr 0 # encoding: [0x20,0x04,0x83,0x4c] + bnsctr +# CHECK-BE: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01] +# CHECK-LE: bnul 2, target # encoding: [0bAAAAAA01,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnsl 2, target +# CHECK-BE: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01] +# CHECK-LE: bnul 0, target # encoding: [0bAAAAAA01,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnsl target +# CHECK-BE: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11] +# CHECK-LE: bnula 2, target # encoding: [0bAAAAAA11,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsla 2, target +# CHECK-BE: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11] +# CHECK-LE: bnula 0, target # encoding: [0bAAAAAA11,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsla target +# CHECK-BE: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21] +# CHECK-LE: bnulrl 2 # encoding: [0x21,0x00,0x8b,0x4c] + bnslrl 2 +# CHECK-BE: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21] +# CHECK-LE: bnulrl 0 # encoding: [0x21,0x00,0x83,0x4c] + bnslrl +# CHECK-BE: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21] +# CHECK-LE: bnuctrl 2 # encoding: [0x21,0x04,0x8b,0x4c] + bnsctrl 2 +# CHECK-BE: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21] +# CHECK-LE: bnuctrl 0 # encoding: [0x21,0x04,0x83,0x4c] + bnsctrl + +# CHECK-BE: bnu+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA00] +# CHECK-LE: bnu+ 2, target # encoding: [0bAAAAAA00,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns+ 2, target +# CHECK-BE: bnu+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA00] +# CHECK-LE: bnu+ 0, target # encoding: [0bAAAAAA00,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns+ target +# CHECK-BE: bnua+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA10] +# CHECK-LE: bnua+ 2, target # encoding: [0bAAAAAA10,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsa+ 2, target +# CHECK-BE: bnua+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA10] +# CHECK-LE: bnua+ 0, target # encoding: [0bAAAAAA10,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsa+ target +# CHECK-BE: bnulr+ 2 # encoding: [0x4c,0xeb,0x00,0x20] +# CHECK-LE: bnulr+ 2 # encoding: [0x20,0x00,0xeb,0x4c] + bnslr+ 2 +# CHECK-BE: bnulr+ 0 # encoding: [0x4c,0xe3,0x00,0x20] +# CHECK-LE: bnulr+ 0 # encoding: [0x20,0x00,0xe3,0x4c] + bnslr+ +# CHECK-BE: bnuctr+ 2 # encoding: [0x4c,0xeb,0x04,0x20] +# CHECK-LE: bnuctr+ 2 # encoding: [0x20,0x04,0xeb,0x4c] + bnsctr+ 2 +# CHECK-BE: bnuctr+ 0 # encoding: [0x4c,0xe3,0x04,0x20] +# CHECK-LE: bnuctr+ 0 # encoding: [0x20,0x04,0xe3,0x4c] + bnsctr+ +# CHECK-BE: bnul+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA01] +# CHECK-LE: bnul+ 2, target # encoding: [0bAAAAAA01,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnsl+ 2, target +# CHECK-BE: bnul+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA01] +# CHECK-LE: bnul+ 0, target # encoding: [0bAAAAAA01,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnsl+ target +# CHECK-BE: bnula+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA11] +# CHECK-LE: bnula+ 2, target # encoding: [0bAAAAAA11,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsla+ 2, target +# CHECK-BE: bnula+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA11] +# CHECK-LE: bnula+ 0, target # encoding: [0bAAAAAA11,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsla+ target +# CHECK-BE: bnulrl+ 2 # encoding: [0x4c,0xeb,0x00,0x21] +# CHECK-LE: bnulrl+ 2 # encoding: [0x21,0x00,0xeb,0x4c] + bnslrl+ 2 +# CHECK-BE: bnulrl+ 0 # encoding: [0x4c,0xe3,0x00,0x21] +# CHECK-LE: bnulrl+ 0 # encoding: [0x21,0x00,0xe3,0x4c] + bnslrl+ +# CHECK-BE: bnuctrl+ 2 # encoding: [0x4c,0xeb,0x04,0x21] +# CHECK-LE: bnuctrl+ 2 # encoding: [0x21,0x04,0xeb,0x4c] + bnsctrl+ 2 +# CHECK-BE: bnuctrl+ 0 # encoding: [0x4c,0xe3,0x04,0x21] +# CHECK-LE: bnuctrl+ 0 # encoding: [0x21,0x04,0xe3,0x4c] + bnsctrl+ + +# CHECK-BE: bnu- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA00] +# CHECK-LE: bnu- 2, target # encoding: [0bAAAAAA00,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns- 2, target +# CHECK-BE: bnu- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA00] +# CHECK-LE: bnu- 0, target # encoding: [0bAAAAAA00,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns- target +# CHECK-BE: bnua- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA10] +# CHECK-LE: bnua- 2, target # encoding: [0bAAAAAA10,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsa- 2, target +# CHECK-BE: bnua- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA10] +# CHECK-LE: bnua- 0, target # encoding: [0bAAAAAA10,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsa- target +# CHECK-BE: bnulr- 2 # encoding: [0x4c,0xcb,0x00,0x20] +# CHECK-LE: bnulr- 2 # encoding: [0x20,0x00,0xcb,0x4c] + bnslr- 2 +# CHECK-BE: bnulr- 0 # encoding: [0x4c,0xc3,0x00,0x20] +# CHECK-LE: bnulr- 0 # encoding: [0x20,0x00,0xc3,0x4c] + bnslr- +# CHECK-BE: bnuctr- 2 # encoding: [0x4c,0xcb,0x04,0x20] +# CHECK-LE: bnuctr- 2 # encoding: [0x20,0x04,0xcb,0x4c] + bnsctr- 2 +# CHECK-BE: bnuctr- 0 # encoding: [0x4c,0xc3,0x04,0x20] +# CHECK-LE: bnuctr- 0 # encoding: [0x20,0x04,0xc3,0x4c] + bnsctr- +# CHECK-BE: bnul- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA01] +# CHECK-LE: bnul- 2, target # encoding: [0bAAAAAA01,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnsl- 2, target +# CHECK-BE: bnul- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA01] +# CHECK-LE: bnul- 0, target # encoding: [0bAAAAAA01,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnsl- target +# CHECK-BE: bnula- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA11] +# CHECK-LE: bnula- 2, target # encoding: [0bAAAAAA11,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsla- 2, target +# CHECK-BE: bnula- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA11] +# CHECK-LE: bnula- 0, target # encoding: [0bAAAAAA11,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnsla- target +# CHECK-BE: bnulrl- 2 # encoding: [0x4c,0xcb,0x00,0x21] +# CHECK-LE: bnulrl- 2 # encoding: [0x21,0x00,0xcb,0x4c] + bnslrl- 2 +# CHECK-BE: bnulrl- 0 # encoding: [0x4c,0xc3,0x00,0x21] +# CHECK-LE: bnulrl- 0 # encoding: [0x21,0x00,0xc3,0x4c] + bnslrl- +# CHECK-BE: bnuctrl- 2 # encoding: [0x4c,0xcb,0x04,0x21] +# CHECK-LE: bnuctrl- 2 # encoding: [0x21,0x04,0xcb,0x4c] + bnsctrl- 2 +# CHECK-BE: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21] +# CHECK-LE: bnuctrl- 0 # encoding: [0x21,0x04,0xc3,0x4c] + bnsctrl- + +# CHECK-BE: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00] +# CHECK-LE: bun 2, target # encoding: [0bAAAAAA00,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun 2, target +# CHECK-BE: bun 0, target # encoding: [0x41,0x83,A,0bAAAAAA00] +# CHECK-LE: bun 0, target # encoding: [0bAAAAAA00,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun target +# CHECK-BE: buna 2, target # encoding: [0x41,0x8b,A,0bAAAAAA10] +# CHECK-LE: buna 2, target # encoding: [0bAAAAAA10,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + buna 2, target +# CHECK-BE: buna 0, target # encoding: [0x41,0x83,A,0bAAAAAA10] +# CHECK-LE: buna 0, target # encoding: [0bAAAAAA10,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + buna target +# CHECK-BE: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20] +# CHECK-LE: bunlr 2 # encoding: [0x20,0x00,0x8b,0x4d] + bunlr 2 +# CHECK-BE: bunlr 0 # encoding: [0x4d,0x83,0x00,0x20] +# CHECK-LE: bunlr 0 # encoding: [0x20,0x00,0x83,0x4d] + bunlr +# CHECK-BE: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20] +# CHECK-LE: bunctr 2 # encoding: [0x20,0x04,0x8b,0x4d] + bunctr 2 +# CHECK-BE: bunctr 0 # encoding: [0x4d,0x83,0x04,0x20] +# CHECK-LE: bunctr 0 # encoding: [0x20,0x04,0x83,0x4d] + bunctr +# CHECK-BE: bunl 2, target # encoding: [0x41,0x8b,A,0bAAAAAA01] +# CHECK-LE: bunl 2, target # encoding: [0bAAAAAA01,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bunl 2, target +# CHECK-BE: bunl 0, target # encoding: [0x41,0x83,A,0bAAAAAA01] +# CHECK-LE: bunl 0, target # encoding: [0bAAAAAA01,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bunl target +# CHECK-BE: bunla 2, target # encoding: [0x41,0x8b,A,0bAAAAAA11] +# CHECK-LE: bunla 2, target # encoding: [0bAAAAAA11,A,0x8b,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bunla 2, target +# CHECK-BE: bunla 0, target # encoding: [0x41,0x83,A,0bAAAAAA11] +# CHECK-LE: bunla 0, target # encoding: [0bAAAAAA11,A,0x83,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bunla target +# CHECK-BE: bunlrl 2 # encoding: [0x4d,0x8b,0x00,0x21] +# CHECK-LE: bunlrl 2 # encoding: [0x21,0x00,0x8b,0x4d] + bunlrl 2 +# CHECK-BE: bunlrl 0 # encoding: [0x4d,0x83,0x00,0x21] +# CHECK-LE: bunlrl 0 # encoding: [0x21,0x00,0x83,0x4d] + bunlrl +# CHECK-BE: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21] +# CHECK-LE: bunctrl 2 # encoding: [0x21,0x04,0x8b,0x4d] + bunctrl 2 +# CHECK-BE: bunctrl 0 # encoding: [0x4d,0x83,0x04,0x21] +# CHECK-LE: bunctrl 0 # encoding: [0x21,0x04,0x83,0x4d] + bunctrl + +# CHECK-BE: bun+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA00] +# CHECK-LE: bun+ 2, target # encoding: [0bAAAAAA00,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun+ 2, target +# CHECK-BE: bun+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA00] +# CHECK-LE: bun+ 0, target # encoding: [0bAAAAAA00,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun+ target +# CHECK-BE: buna+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA10] +# CHECK-LE: buna+ 2, target # encoding: [0bAAAAAA10,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + buna+ 2, target +# CHECK-BE: buna+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA10] +# CHECK-LE: buna+ 0, target # encoding: [0bAAAAAA10,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + buna+ target +# CHECK-BE: bunlr+ 2 # encoding: [0x4d,0xeb,0x00,0x20] +# CHECK-LE: bunlr+ 2 # encoding: [0x20,0x00,0xeb,0x4d] + bunlr+ 2 +# CHECK-BE: bunlr+ 0 # encoding: [0x4d,0xe3,0x00,0x20] +# CHECK-LE: bunlr+ 0 # encoding: [0x20,0x00,0xe3,0x4d] + bunlr+ +# CHECK-BE: bunctr+ 2 # encoding: [0x4d,0xeb,0x04,0x20] +# CHECK-LE: bunctr+ 2 # encoding: [0x20,0x04,0xeb,0x4d] + bunctr+ 2 +# CHECK-BE: bunctr+ 0 # encoding: [0x4d,0xe3,0x04,0x20] +# CHECK-LE: bunctr+ 0 # encoding: [0x20,0x04,0xe3,0x4d] + bunctr+ +# CHECK-BE: bunl+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA01] +# CHECK-LE: bunl+ 2, target # encoding: [0bAAAAAA01,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bunl+ 2, target +# CHECK-BE: bunl+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA01] +# CHECK-LE: bunl+ 0, target # encoding: [0bAAAAAA01,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bunl+ target +# CHECK-BE: bunla+ 2, target # encoding: [0x41,0xeb,A,0bAAAAAA11] +# CHECK-LE: bunla+ 2, target # encoding: [0bAAAAAA11,A,0xeb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bunla+ 2, target +# CHECK-BE: bunla+ 0, target # encoding: [0x41,0xe3,A,0bAAAAAA11] +# CHECK-LE: bunla+ 0, target # encoding: [0bAAAAAA11,A,0xe3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bunla+ target +# CHECK-BE: bunlrl+ 2 # encoding: [0x4d,0xeb,0x00,0x21] +# CHECK-LE: bunlrl+ 2 # encoding: [0x21,0x00,0xeb,0x4d] + bunlrl+ 2 +# CHECK-BE: bunlrl+ 0 # encoding: [0x4d,0xe3,0x00,0x21] +# CHECK-LE: bunlrl+ 0 # encoding: [0x21,0x00,0xe3,0x4d] + bunlrl+ +# CHECK-BE: bunctrl+ 2 # encoding: [0x4d,0xeb,0x04,0x21] +# CHECK-LE: bunctrl+ 2 # encoding: [0x21,0x04,0xeb,0x4d] + bunctrl+ 2 +# CHECK-BE: bunctrl+ 0 # encoding: [0x4d,0xe3,0x04,0x21] +# CHECK-LE: bunctrl+ 0 # encoding: [0x21,0x04,0xe3,0x4d] + bunctrl+ + +# CHECK-BE: bun- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA00] +# CHECK-LE: bun- 2, target # encoding: [0bAAAAAA00,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun- 2, target +# CHECK-BE: bun- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA00] +# CHECK-LE: bun- 0, target # encoding: [0bAAAAAA00,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun- target +# CHECK-BE: buna- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA10] +# CHECK-LE: buna- 2, target # encoding: [0bAAAAAA10,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + buna- 2, target +# CHECK-BE: buna- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA10] +# CHECK-LE: buna- 0, target # encoding: [0bAAAAAA10,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + buna- target +# CHECK-BE: bunlr- 2 # encoding: [0x4d,0xcb,0x00,0x20] +# CHECK-LE: bunlr- 2 # encoding: [0x20,0x00,0xcb,0x4d] + bunlr- 2 +# CHECK-BE: bunlr- 0 # encoding: [0x4d,0xc3,0x00,0x20] +# CHECK-LE: bunlr- 0 # encoding: [0x20,0x00,0xc3,0x4d] + bunlr- +# CHECK-BE: bunctr- 2 # encoding: [0x4d,0xcb,0x04,0x20] +# CHECK-LE: bunctr- 2 # encoding: [0x20,0x04,0xcb,0x4d] + bunctr- 2 +# CHECK-BE: bunctr- 0 # encoding: [0x4d,0xc3,0x04,0x20] +# CHECK-LE: bunctr- 0 # encoding: [0x20,0x04,0xc3,0x4d] + bunctr- +# CHECK-BE: bunl- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA01] +# CHECK-LE: bunl- 2, target # encoding: [0bAAAAAA01,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bunl- 2, target +# CHECK-BE: bunl- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA01] +# CHECK-LE: bunl- 0, target # encoding: [0bAAAAAA01,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bunl- target +# CHECK-BE: bunla- 2, target # encoding: [0x41,0xcb,A,0bAAAAAA11] +# CHECK-LE: bunla- 2, target # encoding: [0bAAAAAA11,A,0xcb,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bunla- 2, target +# CHECK-BE: bunla- 0, target # encoding: [0x41,0xc3,A,0bAAAAAA11] +# CHECK-LE: bunla- 0, target # encoding: [0bAAAAAA11,A,0xc3,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bunla- target +# CHECK-BE: bunlrl- 2 # encoding: [0x4d,0xcb,0x00,0x21] +# CHECK-LE: bunlrl- 2 # encoding: [0x21,0x00,0xcb,0x4d] + bunlrl- 2 +# CHECK-BE: bunlrl- 0 # encoding: [0x4d,0xc3,0x00,0x21] +# CHECK-LE: bunlrl- 0 # encoding: [0x21,0x00,0xc3,0x4d] + bunlrl- +# CHECK-BE: bunctrl- 2 # encoding: [0x4d,0xcb,0x04,0x21] +# CHECK-LE: bunctrl- 2 # encoding: [0x21,0x04,0xcb,0x4d] + bunctrl- 2 +# CHECK-BE: bunctrl- 0 # encoding: [0x4d,0xc3,0x04,0x21] +# CHECK-LE: bunctrl- 0 # encoding: [0x21,0x04,0xc3,0x4d] + bunctrl- + +# CHECK-BE: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00] +# CHECK-LE: bnu 2, target # encoding: [0bAAAAAA00,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu 2, target +# CHECK-BE: bnu 0, target # encoding: [0x40,0x83,A,0bAAAAAA00] +# CHECK-LE: bnu 0, target # encoding: [0bAAAAAA00,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu target +# CHECK-BE: bnua 2, target # encoding: [0x40,0x8b,A,0bAAAAAA10] +# CHECK-LE: bnua 2, target # encoding: [0bAAAAAA10,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnua 2, target +# CHECK-BE: bnua 0, target # encoding: [0x40,0x83,A,0bAAAAAA10] +# CHECK-LE: bnua 0, target # encoding: [0bAAAAAA10,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnua target +# CHECK-BE: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20] +# CHECK-LE: bnulr 2 # encoding: [0x20,0x00,0x8b,0x4c] + bnulr 2 +# CHECK-BE: bnulr 0 # encoding: [0x4c,0x83,0x00,0x20] +# CHECK-LE: bnulr 0 # encoding: [0x20,0x00,0x83,0x4c] + bnulr +# CHECK-BE: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20] +# CHECK-LE: bnuctr 2 # encoding: [0x20,0x04,0x8b,0x4c] + bnuctr 2 +# CHECK-BE: bnuctr 0 # encoding: [0x4c,0x83,0x04,0x20] +# CHECK-LE: bnuctr 0 # encoding: [0x20,0x04,0x83,0x4c] + bnuctr +# CHECK-BE: bnul 2, target # encoding: [0x40,0x8b,A,0bAAAAAA01] +# CHECK-LE: bnul 2, target # encoding: [0bAAAAAA01,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnul 2, target +# CHECK-BE: bnul 0, target # encoding: [0x40,0x83,A,0bAAAAAA01] +# CHECK-LE: bnul 0, target # encoding: [0bAAAAAA01,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnul target +# CHECK-BE: bnula 2, target # encoding: [0x40,0x8b,A,0bAAAAAA11] +# CHECK-LE: bnula 2, target # encoding: [0bAAAAAA11,A,0x8b,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnula 2, target +# CHECK-BE: bnula 0, target # encoding: [0x40,0x83,A,0bAAAAAA11] +# CHECK-LE: bnula 0, target # encoding: [0bAAAAAA11,A,0x83,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnula target +# CHECK-BE: bnulrl 2 # encoding: [0x4c,0x8b,0x00,0x21] +# CHECK-LE: bnulrl 2 # encoding: [0x21,0x00,0x8b,0x4c] + bnulrl 2 +# CHECK-BE: bnulrl 0 # encoding: [0x4c,0x83,0x00,0x21] +# CHECK-LE: bnulrl 0 # encoding: [0x21,0x00,0x83,0x4c] + bnulrl +# CHECK-BE: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21] +# CHECK-LE: bnuctrl 2 # encoding: [0x21,0x04,0x8b,0x4c] + bnuctrl 2 +# CHECK-BE: bnuctrl 0 # encoding: [0x4c,0x83,0x04,0x21] +# CHECK-LE: bnuctrl 0 # encoding: [0x21,0x04,0x83,0x4c] + bnuctrl + +# CHECK-BE: bnu+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA00] +# CHECK-LE: bnu+ 2, target # encoding: [0bAAAAAA00,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu+ 2, target +# CHECK-BE: bnu+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA00] +# CHECK-LE: bnu+ 0, target # encoding: [0bAAAAAA00,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu+ target +# CHECK-BE: bnua+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA10] +# CHECK-LE: bnua+ 2, target # encoding: [0bAAAAAA10,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnua+ 2, target +# CHECK-BE: bnua+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA10] +# CHECK-LE: bnua+ 0, target # encoding: [0bAAAAAA10,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnua+ target +# CHECK-BE: bnulr+ 2 # encoding: [0x4c,0xeb,0x00,0x20] +# CHECK-LE: bnulr+ 2 # encoding: [0x20,0x00,0xeb,0x4c] + bnulr+ 2 +# CHECK-BE: bnulr+ 0 # encoding: [0x4c,0xe3,0x00,0x20] +# CHECK-LE: bnulr+ 0 # encoding: [0x20,0x00,0xe3,0x4c] + bnulr+ +# CHECK-BE: bnuctr+ 2 # encoding: [0x4c,0xeb,0x04,0x20] +# CHECK-LE: bnuctr+ 2 # encoding: [0x20,0x04,0xeb,0x4c] + bnuctr+ 2 +# CHECK-BE: bnuctr+ 0 # encoding: [0x4c,0xe3,0x04,0x20] +# CHECK-LE: bnuctr+ 0 # encoding: [0x20,0x04,0xe3,0x4c] + bnuctr+ +# CHECK-BE: bnul+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA01] +# CHECK-LE: bnul+ 2, target # encoding: [0bAAAAAA01,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnul+ 2, target +# CHECK-BE: bnul+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA01] +# CHECK-LE: bnul+ 0, target # encoding: [0bAAAAAA01,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnul+ target +# CHECK-BE: bnula+ 2, target # encoding: [0x40,0xeb,A,0bAAAAAA11] +# CHECK-LE: bnula+ 2, target # encoding: [0bAAAAAA11,A,0xeb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnula+ 2, target +# CHECK-BE: bnula+ 0, target # encoding: [0x40,0xe3,A,0bAAAAAA11] +# CHECK-LE: bnula+ 0, target # encoding: [0bAAAAAA11,A,0xe3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnula+ target +# CHECK-BE: bnulrl+ 2 # encoding: [0x4c,0xeb,0x00,0x21] +# CHECK-LE: bnulrl+ 2 # encoding: [0x21,0x00,0xeb,0x4c] + bnulrl+ 2 +# CHECK-BE: bnulrl+ 0 # encoding: [0x4c,0xe3,0x00,0x21] +# CHECK-LE: bnulrl+ 0 # encoding: [0x21,0x00,0xe3,0x4c] + bnulrl+ +# CHECK-BE: bnuctrl+ 2 # encoding: [0x4c,0xeb,0x04,0x21] +# CHECK-LE: bnuctrl+ 2 # encoding: [0x21,0x04,0xeb,0x4c] + bnuctrl+ 2 +# CHECK-BE: bnuctrl+ 0 # encoding: [0x4c,0xe3,0x04,0x21] +# CHECK-LE: bnuctrl+ 0 # encoding: [0x21,0x04,0xe3,0x4c] + bnuctrl+ + +# CHECK-BE: bnu- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA00] +# CHECK-LE: bnu- 2, target # encoding: [0bAAAAAA00,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu- 2, target +# CHECK-BE: bnu- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA00] +# CHECK-LE: bnu- 0, target # encoding: [0bAAAAAA00,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu- target +# CHECK-BE: bnua- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA10] +# CHECK-LE: bnua- 2, target # encoding: [0bAAAAAA10,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnua- 2, target +# CHECK-BE: bnua- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA10] +# CHECK-LE: bnua- 0, target # encoding: [0bAAAAAA10,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnua- target +# CHECK-BE: bnulr- 2 # encoding: [0x4c,0xcb,0x00,0x20] +# CHECK-LE: bnulr- 2 # encoding: [0x20,0x00,0xcb,0x4c] + bnulr- 2 +# CHECK-BE: bnulr- 0 # encoding: [0x4c,0xc3,0x00,0x20] +# CHECK-LE: bnulr- 0 # encoding: [0x20,0x00,0xc3,0x4c] + bnulr- +# CHECK-BE: bnuctr- 2 # encoding: [0x4c,0xcb,0x04,0x20] +# CHECK-LE: bnuctr- 2 # encoding: [0x20,0x04,0xcb,0x4c] + bnuctr- 2 +# CHECK-BE: bnuctr- 0 # encoding: [0x4c,0xc3,0x04,0x20] +# CHECK-LE: bnuctr- 0 # encoding: [0x20,0x04,0xc3,0x4c] + bnuctr- +# CHECK-BE: bnul- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA01] +# CHECK-LE: bnul- 2, target # encoding: [0bAAAAAA01,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnul- 2, target +# CHECK-BE: bnul- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA01] +# CHECK-LE: bnul- 0, target # encoding: [0bAAAAAA01,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnul- target +# CHECK-BE: bnula- 2, target # encoding: [0x40,0xcb,A,0bAAAAAA11] +# CHECK-LE: bnula- 2, target # encoding: [0bAAAAAA11,A,0xcb,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnula- 2, target +# CHECK-BE: bnula- 0, target # encoding: [0x40,0xc3,A,0bAAAAAA11] +# CHECK-LE: bnula- 0, target # encoding: [0bAAAAAA11,A,0xc3,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bnula- target +# CHECK-BE: bnulrl- 2 # encoding: [0x4c,0xcb,0x00,0x21] +# CHECK-LE: bnulrl- 2 # encoding: [0x21,0x00,0xcb,0x4c] + bnulrl- 2 +# CHECK-BE: bnulrl- 0 # encoding: [0x4c,0xc3,0x00,0x21] +# CHECK-LE: bnulrl- 0 # encoding: [0x21,0x00,0xc3,0x4c] + bnulrl- +# CHECK-BE: bnuctrl- 2 # encoding: [0x4c,0xcb,0x04,0x21] +# CHECK-LE: bnuctrl- 2 # encoding: [0x21,0x04,0xcb,0x4c] + bnuctrl- 2 +# CHECK-BE: bnuctrl- 0 # encoding: [0x4c,0xc3,0x04,0x21] +# CHECK-LE: bnuctrl- 0 # encoding: [0x21,0x04,0xc3,0x4c] + bnuctrl- # Condition register logical mnemonics -# CHECK: creqv 2, 2, 2 # encoding: [0x4c,0x42,0x12,0x42] - crset 2 -# CHECK: crxor 2, 2, 2 # encoding: [0x4c,0x42,0x11,0x82] - crclr 2 -# CHECK: cror 2, 3, 3 # encoding: [0x4c,0x43,0x1b,0x82] - crmove 2, 3 -# CHECK: crnor 2, 3, 3 # encoding: [0x4c,0x43,0x18,0x42] - crnot 2, 3 +# CHECK-BE: creqv 2, 2, 2 # encoding: [0x4c,0x42,0x12,0x42] +# CHECK-LE: creqv 2, 2, 2 # encoding: [0x42,0x12,0x42,0x4c] + crset 2 +# CHECK-BE: crxor 2, 2, 2 # encoding: [0x4c,0x42,0x11,0x82] +# CHECK-LE: crxor 2, 2, 2 # encoding: [0x82,0x11,0x42,0x4c] + crclr 2 +# CHECK-BE: cror 2, 3, 3 # encoding: [0x4c,0x43,0x1b,0x82] +# CHECK-LE: cror 2, 3, 3 # encoding: [0x82,0x1b,0x43,0x4c] + crmove 2, 3 +# CHECK-BE: crnor 2, 3, 3 # encoding: [0x4c,0x43,0x18,0x42] +# CHECK-LE: crnor 2, 3, 3 # encoding: [0x42,0x18,0x43,0x4c] + crnot 2, 3 # Subtract mnemonics -# CHECK: addi 2, 3, -128 # encoding: [0x38,0x43,0xff,0x80] - subi 2, 3, 128 -# CHECK: addis 2, 3, -128 # encoding: [0x3c,0x43,0xff,0x80] - subis 2, 3, 128 -# CHECK: addic 2, 3, -128 # encoding: [0x30,0x43,0xff,0x80] - subic 2, 3, 128 -# CHECK: addic. 2, 3, -128 # encoding: [0x34,0x43,0xff,0x80] - subic. 2, 3, 128 - -# CHECK: subf 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x50] - sub 2, 3, 4 -# CHECK: subf. 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x51] - sub. 2, 3, 4 -# CHECK: subfc 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x10] - subc 2, 3, 4 -# CHECK: subfc. 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x11] - subc. 2, 3, 4 +# CHECK-BE: addi 2, 3, -128 # encoding: [0x38,0x43,0xff,0x80] +# CHECK-LE: addi 2, 3, -128 # encoding: [0x80,0xff,0x43,0x38] + subi 2, 3, 128 +# CHECK-BE: addis 2, 3, -128 # encoding: [0x3c,0x43,0xff,0x80] +# CHECK-LE: addis 2, 3, -128 # encoding: [0x80,0xff,0x43,0x3c] + subis 2, 3, 128 +# CHECK-BE: addic 2, 3, -128 # encoding: [0x30,0x43,0xff,0x80] +# CHECK-LE: addic 2, 3, -128 # encoding: [0x80,0xff,0x43,0x30] + subic 2, 3, 128 +# CHECK-BE: addic. 2, 3, -128 # encoding: [0x34,0x43,0xff,0x80] +# CHECK-LE: addic. 2, 3, -128 # encoding: [0x80,0xff,0x43,0x34] + subic. 2, 3, 128 + +# CHECK-BE: subf 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x50] +# CHECK-LE: subf 2, 4, 3 # encoding: [0x50,0x18,0x44,0x7c] + sub 2, 3, 4 +# CHECK-BE: subf. 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x51] +# CHECK-LE: subf. 2, 4, 3 # encoding: [0x51,0x18,0x44,0x7c] + sub. 2, 3, 4 +# CHECK-BE: subfc 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x10] +# CHECK-LE: subfc 2, 4, 3 # encoding: [0x10,0x18,0x44,0x7c] + subc 2, 3, 4 +# CHECK-BE: subfc. 2, 4, 3 # encoding: [0x7c,0x44,0x18,0x11] +# CHECK-LE: subfc. 2, 4, 3 # encoding: [0x11,0x18,0x44,0x7c] + subc. 2, 3, 4 # Compare mnemonics -# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] - cmpdi 2, 3, 128 -# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] - cmpdi 3, 128 -# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] - cmpd 2, 3, 4 -# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] - cmpd 3, 4 -# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] - cmpldi 2, 3, 128 -# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] - cmpldi 3, 128 -# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] - cmpld 2, 3, 4 -# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] - cmpld 3, 4 - -# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] - cmpwi 2, 3, 128 -# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] - cmpwi 3, 128 -# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] - cmpw 2, 3, 4 -# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] - cmpw 3, 4 -# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] - cmplwi 2, 3, 128 -# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] - cmplwi 3, 128 -# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] - cmplw 2, 3, 4 -# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] - cmplw 3, 4 +# CHECK-BE: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] +# CHECK-LE: cmpdi 2, 3, 128 # encoding: [0x80,0x00,0x23,0x2d] + cmpdi 2, 3, 128 +# CHECK-BE: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] +# CHECK-LE: cmpdi 0, 3, 128 # encoding: [0x80,0x00,0x23,0x2c] + cmpdi 3, 128 +# CHECK-BE: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] +# CHECK-LE: cmpd 2, 3, 4 # encoding: [0x00,0x20,0x23,0x7d] + cmpd 2, 3, 4 +# CHECK-BE: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] +# CHECK-LE: cmpd 0, 3, 4 # encoding: [0x00,0x20,0x23,0x7c] + cmpd 3, 4 +# CHECK-BE: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] +# CHECK-LE: cmpldi 2, 3, 128 # encoding: [0x80,0x00,0x23,0x29] + cmpldi 2, 3, 128 +# CHECK-BE: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] +# CHECK-LE: cmpldi 0, 3, 128 # encoding: [0x80,0x00,0x23,0x28] + cmpldi 3, 128 +# CHECK-BE: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] +# CHECK-LE: cmpld 2, 3, 4 # encoding: [0x40,0x20,0x23,0x7d] + cmpld 2, 3, 4 +# CHECK-BE: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] +# CHECK-LE: cmpld 0, 3, 4 # encoding: [0x40,0x20,0x23,0x7c] + cmpld 3, 4 + +# CHECK-BE: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] +# CHECK-LE: cmpwi 2, 3, 128 # encoding: [0x80,0x00,0x03,0x2d] + cmpwi 2, 3, 128 +# CHECK-BE: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] +# CHECK-LE: cmpwi 0, 3, 128 # encoding: [0x80,0x00,0x03,0x2c] + cmpwi 3, 128 +# CHECK-BE: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] +# CHECK-LE: cmpw 2, 3, 4 # encoding: [0x00,0x20,0x03,0x7d] + cmpw 2, 3, 4 +# CHECK-BE: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] +# CHECK-LE: cmpw 0, 3, 4 # encoding: [0x00,0x20,0x03,0x7c] + cmpw 3, 4 +# CHECK-BE: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] +# CHECK-LE: cmplwi 2, 3, 128 # encoding: [0x80,0x00,0x03,0x29] + cmplwi 2, 3, 128 +# CHECK-BE: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] +# CHECK-LE: cmplwi 0, 3, 128 # encoding: [0x80,0x00,0x03,0x28] + cmplwi 3, 128 +# CHECK-BE: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] +# CHECK-LE: cmplw 2, 3, 4 # encoding: [0x40,0x20,0x03,0x7d] + cmplw 2, 3, 4 +# CHECK-BE: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] +# CHECK-LE: cmplw 0, 3, 4 # encoding: [0x40,0x20,0x03,0x7c] + cmplw 3, 4 # Trap mnemonics -# CHECK: twi 16, 3, 4 # encoding: [0x0e,0x03,0x00,0x04] - twlti 3, 4 -# CHECK: tw 16, 3, 4 # encoding: [0x7e,0x03,0x20,0x08] - twlt 3, 4 -# CHECK: tdi 16, 3, 4 # encoding: [0x0a,0x03,0x00,0x04] - tdlti 3, 4 -# CHECK: td 16, 3, 4 # encoding: [0x7e,0x03,0x20,0x88] - tdlt 3, 4 - -# CHECK: twi 20, 3, 4 # encoding: [0x0e,0x83,0x00,0x04] - twlei 3, 4 -# CHECK: tw 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x08] - twle 3, 4 -# CHECK: tdi 20, 3, 4 # encoding: [0x0a,0x83,0x00,0x04] - tdlei 3, 4 -# CHECK: td 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x88] - tdle 3, 4 - -# CHECK: twi 4, 3, 4 # encoding: [0x0c,0x83,0x00,0x04] - tweqi 3, 4 -# CHECK: tw 4, 3, 4 # encoding: [0x7c,0x83,0x20,0x08] - tweq 3, 4 -# CHECK: tdi 4, 3, 4 # encoding: [0x08,0x83,0x00,0x04] - tdeqi 3, 4 -# CHECK: td 4, 3, 4 # encoding: [0x7c,0x83,0x20,0x88] - tdeq 3, 4 - -# CHECK: twi 12, 3, 4 # encoding: [0x0d,0x83,0x00,0x04] - twgei 3, 4 -# CHECK: tw 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x08] - twge 3, 4 -# CHECK: tdi 12, 3, 4 # encoding: [0x09,0x83,0x00,0x04] - tdgei 3, 4 -# CHECK: td 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x88] - tdge 3, 4 - -# CHECK: twi 8, 3, 4 # encoding: [0x0d,0x03,0x00,0x04] - twgti 3, 4 -# CHECK: tw 8, 3, 4 # encoding: [0x7d,0x03,0x20,0x08] - twgt 3, 4 -# CHECK: tdi 8, 3, 4 # encoding: [0x09,0x03,0x00,0x04] - tdgti 3, 4 -# CHECK: td 8, 3, 4 # encoding: [0x7d,0x03,0x20,0x88] - tdgt 3, 4 - -# CHECK: twi 12, 3, 4 # encoding: [0x0d,0x83,0x00,0x04] - twnli 3, 4 -# CHECK: tw 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x08] - twnl 3, 4 -# CHECK: tdi 12, 3, 4 # encoding: [0x09,0x83,0x00,0x04] - tdnli 3, 4 -# CHECK: td 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x88] - tdnl 3, 4 - -# CHECK: twi 24, 3, 4 # encoding: [0x0f,0x03,0x00,0x04] - twnei 3, 4 -# CHECK: tw 24, 3, 4 # encoding: [0x7f,0x03,0x20,0x08] - twne 3, 4 -# CHECK: tdi 24, 3, 4 # encoding: [0x0b,0x03,0x00,0x04] - tdnei 3, 4 -# CHECK: td 24, 3, 4 # encoding: [0x7f,0x03,0x20,0x88] - tdne 3, 4 - -# CHECK: twi 20, 3, 4 # encoding: [0x0e,0x83,0x00,0x04] - twngi 3, 4 -# CHECK: tw 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x08] - twng 3, 4 -# CHECK: tdi 20, 3, 4 # encoding: [0x0a,0x83,0x00,0x04] - tdngi 3, 4 -# CHECK: td 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x88] - tdng 3, 4 - -# CHECK: twi 2, 3, 4 # encoding: [0x0c,0x43,0x00,0x04] - twllti 3, 4 -# CHECK: tw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x08] - twllt 3, 4 -# CHECK: tdi 2, 3, 4 # encoding: [0x08,0x43,0x00,0x04] - tdllti 3, 4 -# CHECK: td 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x88] - tdllt 3, 4 - -# CHECK: twi 6, 3, 4 # encoding: [0x0c,0xc3,0x00,0x04] - twllei 3, 4 -# CHECK: tw 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x08] - twlle 3, 4 -# CHECK: tdi 6, 3, 4 # encoding: [0x08,0xc3,0x00,0x04] - tdllei 3, 4 -# CHECK: td 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x88] - tdlle 3, 4 - -# CHECK: twi 5, 3, 4 # encoding: [0x0c,0xa3,0x00,0x04] - twlgei 3, 4 -# CHECK: tw 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x08] - twlge 3, 4 -# CHECK: tdi 5, 3, 4 # encoding: [0x08,0xa3,0x00,0x04] - tdlgei 3, 4 -# CHECK: td 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x88] - tdlge 3, 4 - -# CHECK: twi 1, 3, 4 # encoding: [0x0c,0x23,0x00,0x04] - twlgti 3, 4 -# CHECK: tw 1, 3, 4 # encoding: [0x7c,0x23,0x20,0x08] - twlgt 3, 4 -# CHECK: tdi 1, 3, 4 # encoding: [0x08,0x23,0x00,0x04] - tdlgti 3, 4 -# CHECK: td 1, 3, 4 # encoding: [0x7c,0x23,0x20,0x88] - tdlgt 3, 4 - -# CHECK: twi 5, 3, 4 # encoding: [0x0c,0xa3,0x00,0x04] - twlnli 3, 4 -# CHECK: tw 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x08] - twlnl 3, 4 -# CHECK: tdi 5, 3, 4 # encoding: [0x08,0xa3,0x00,0x04] - tdlnli 3, 4 -# CHECK: td 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x88] - tdlnl 3, 4 - -# CHECK: twi 6, 3, 4 # encoding: [0x0c,0xc3,0x00,0x04] - twlngi 3, 4 -# CHECK: tw 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x08] - twlng 3, 4 -# CHECK: tdi 6, 3, 4 # encoding: [0x08,0xc3,0x00,0x04] - tdlngi 3, 4 -# CHECK: td 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x88] - tdlng 3, 4 - -# CHECK: twi 31, 3, 4 # encoding: [0x0f,0xe3,0x00,0x04] - twui 3, 4 -# CHECK: tw 31, 3, 4 # encoding: [0x7f,0xe3,0x20,0x08] - twu 3, 4 -# CHECK: tdi 31, 3, 4 # encoding: [0x0b,0xe3,0x00,0x04] - tdui 3, 4 -# CHECK: td 31, 3, 4 # encoding: [0x7f,0xe3,0x20,0x88] - tdu 3, 4 - -# CHECK: trap # encoding: [0x7f,0xe0,0x00,0x08] - trap +# CHECK-BE: twi 16, 3, 4 # encoding: [0x0e,0x03,0x00,0x04] +# CHECK-LE: twi 16, 3, 4 # encoding: [0x04,0x00,0x03,0x0e] + twlti 3, 4 +# CHECK-BE: tw 16, 3, 4 # encoding: [0x7e,0x03,0x20,0x08] +# CHECK-LE: tw 16, 3, 4 # encoding: [0x08,0x20,0x03,0x7e] + twlt 3, 4 +# CHECK-BE: tdi 16, 3, 4 # encoding: [0x0a,0x03,0x00,0x04] +# CHECK-LE: tdi 16, 3, 4 # encoding: [0x04,0x00,0x03,0x0a] + tdlti 3, 4 +# CHECK-BE: td 16, 3, 4 # encoding: [0x7e,0x03,0x20,0x88] +# CHECK-LE: td 16, 3, 4 # encoding: [0x88,0x20,0x03,0x7e] + tdlt 3, 4 + +# CHECK-BE: twi 20, 3, 4 # encoding: [0x0e,0x83,0x00,0x04] +# CHECK-LE: twi 20, 3, 4 # encoding: [0x04,0x00,0x83,0x0e] + twlei 3, 4 +# CHECK-BE: tw 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x08] +# CHECK-LE: tw 20, 3, 4 # encoding: [0x08,0x20,0x83,0x7e] + twle 3, 4 +# CHECK-BE: tdi 20, 3, 4 # encoding: [0x0a,0x83,0x00,0x04] +# CHECK-LE: tdi 20, 3, 4 # encoding: [0x04,0x00,0x83,0x0a] + tdlei 3, 4 +# CHECK-BE: td 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x88] +# CHECK-LE: td 20, 3, 4 # encoding: [0x88,0x20,0x83,0x7e] + tdle 3, 4 + +# CHECK-BE: twi 4, 3, 4 # encoding: [0x0c,0x83,0x00,0x04] +# CHECK-LE: twi 4, 3, 4 # encoding: [0x04,0x00,0x83,0x0c] + tweqi 3, 4 +# CHECK-BE: tw 4, 3, 4 # encoding: [0x7c,0x83,0x20,0x08] +# CHECK-LE: tw 4, 3, 4 # encoding: [0x08,0x20,0x83,0x7c] + tweq 3, 4 +# CHECK-BE: tdi 4, 3, 4 # encoding: [0x08,0x83,0x00,0x04] +# CHECK-LE: tdi 4, 3, 4 # encoding: [0x04,0x00,0x83,0x08] + tdeqi 3, 4 +# CHECK-BE: td 4, 3, 4 # encoding: [0x7c,0x83,0x20,0x88] +# CHECK-LE: td 4, 3, 4 # encoding: [0x88,0x20,0x83,0x7c] + tdeq 3, 4 + +# CHECK-BE: twi 12, 3, 4 # encoding: [0x0d,0x83,0x00,0x04] +# CHECK-LE: twi 12, 3, 4 # encoding: [0x04,0x00,0x83,0x0d] + twgei 3, 4 +# CHECK-BE: tw 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x08] +# CHECK-LE: tw 12, 3, 4 # encoding: [0x08,0x20,0x83,0x7d] + twge 3, 4 +# CHECK-BE: tdi 12, 3, 4 # encoding: [0x09,0x83,0x00,0x04] +# CHECK-LE: tdi 12, 3, 4 # encoding: [0x04,0x00,0x83,0x09] + tdgei 3, 4 +# CHECK-BE: td 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x88] +# CHECK-LE: td 12, 3, 4 # encoding: [0x88,0x20,0x83,0x7d] + tdge 3, 4 + +# CHECK-BE: twi 8, 3, 4 # encoding: [0x0d,0x03,0x00,0x04] +# CHECK-LE: twi 8, 3, 4 # encoding: [0x04,0x00,0x03,0x0d] + twgti 3, 4 +# CHECK-BE: tw 8, 3, 4 # encoding: [0x7d,0x03,0x20,0x08] +# CHECK-LE: tw 8, 3, 4 # encoding: [0x08,0x20,0x03,0x7d] + twgt 3, 4 +# CHECK-BE: tdi 8, 3, 4 # encoding: [0x09,0x03,0x00,0x04] +# CHECK-LE: tdi 8, 3, 4 # encoding: [0x04,0x00,0x03,0x09] + tdgti 3, 4 +# CHECK-BE: td 8, 3, 4 # encoding: [0x7d,0x03,0x20,0x88] +# CHECK-LE: td 8, 3, 4 # encoding: [0x88,0x20,0x03,0x7d] + tdgt 3, 4 + +# CHECK-BE: twi 12, 3, 4 # encoding: [0x0d,0x83,0x00,0x04] +# CHECK-LE: twi 12, 3, 4 # encoding: [0x04,0x00,0x83,0x0d] + twnli 3, 4 +# CHECK-BE: tw 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x08] +# CHECK-LE: tw 12, 3, 4 # encoding: [0x08,0x20,0x83,0x7d] + twnl 3, 4 +# CHECK-BE: tdi 12, 3, 4 # encoding: [0x09,0x83,0x00,0x04] +# CHECK-LE: tdi 12, 3, 4 # encoding: [0x04,0x00,0x83,0x09] + tdnli 3, 4 +# CHECK-BE: td 12, 3, 4 # encoding: [0x7d,0x83,0x20,0x88] +# CHECK-LE: td 12, 3, 4 # encoding: [0x88,0x20,0x83,0x7d] + tdnl 3, 4 + +# CHECK-BE: twi 24, 3, 4 # encoding: [0x0f,0x03,0x00,0x04] +# CHECK-LE: twi 24, 3, 4 # encoding: [0x04,0x00,0x03,0x0f] + twnei 3, 4 +# CHECK-BE: tw 24, 3, 4 # encoding: [0x7f,0x03,0x20,0x08] +# CHECK-LE: tw 24, 3, 4 # encoding: [0x08,0x20,0x03,0x7f] + twne 3, 4 +# CHECK-BE: tdi 24, 3, 4 # encoding: [0x0b,0x03,0x00,0x04] +# CHECK-LE: tdi 24, 3, 4 # encoding: [0x04,0x00,0x03,0x0b] + tdnei 3, 4 +# CHECK-BE: td 24, 3, 4 # encoding: [0x7f,0x03,0x20,0x88] +# CHECK-LE: td 24, 3, 4 # encoding: [0x88,0x20,0x03,0x7f] + tdne 3, 4 + +# CHECK-BE: twi 20, 3, 4 # encoding: [0x0e,0x83,0x00,0x04] +# CHECK-LE: twi 20, 3, 4 # encoding: [0x04,0x00,0x83,0x0e] + twngi 3, 4 +# CHECK-BE: tw 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x08] +# CHECK-LE: tw 20, 3, 4 # encoding: [0x08,0x20,0x83,0x7e] + twng 3, 4 +# CHECK-BE: tdi 20, 3, 4 # encoding: [0x0a,0x83,0x00,0x04] +# CHECK-LE: tdi 20, 3, 4 # encoding: [0x04,0x00,0x83,0x0a] + tdngi 3, 4 +# CHECK-BE: td 20, 3, 4 # encoding: [0x7e,0x83,0x20,0x88] +# CHECK-LE: td 20, 3, 4 # encoding: [0x88,0x20,0x83,0x7e] + tdng 3, 4 + +# CHECK-BE: twi 2, 3, 4 # encoding: [0x0c,0x43,0x00,0x04] +# CHECK-LE: twi 2, 3, 4 # encoding: [0x04,0x00,0x43,0x0c] + twllti 3, 4 +# CHECK-BE: tw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x08] +# CHECK-LE: tw 2, 3, 4 # encoding: [0x08,0x20,0x43,0x7c] + twllt 3, 4 +# CHECK-BE: tdi 2, 3, 4 # encoding: [0x08,0x43,0x00,0x04] +# CHECK-LE: tdi 2, 3, 4 # encoding: [0x04,0x00,0x43,0x08] + tdllti 3, 4 +# CHECK-BE: td 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x88] +# CHECK-LE: td 2, 3, 4 # encoding: [0x88,0x20,0x43,0x7c] + tdllt 3, 4 + +# CHECK-BE: twi 6, 3, 4 # encoding: [0x0c,0xc3,0x00,0x04] +# CHECK-LE: twi 6, 3, 4 # encoding: [0x04,0x00,0xc3,0x0c] + twllei 3, 4 +# CHECK-BE: tw 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x08] +# CHECK-LE: tw 6, 3, 4 # encoding: [0x08,0x20,0xc3,0x7c] + twlle 3, 4 +# CHECK-BE: tdi 6, 3, 4 # encoding: [0x08,0xc3,0x00,0x04] +# CHECK-LE: tdi 6, 3, 4 # encoding: [0x04,0x00,0xc3,0x08] + tdllei 3, 4 +# CHECK-BE: td 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x88] +# CHECK-LE: td 6, 3, 4 # encoding: [0x88,0x20,0xc3,0x7c] + tdlle 3, 4 + +# CHECK-BE: twi 5, 3, 4 # encoding: [0x0c,0xa3,0x00,0x04] +# CHECK-LE: twi 5, 3, 4 # encoding: [0x04,0x00,0xa3,0x0c] + twlgei 3, 4 +# CHECK-BE: tw 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x08] +# CHECK-LE: tw 5, 3, 4 # encoding: [0x08,0x20,0xa3,0x7c] + twlge 3, 4 +# CHECK-BE: tdi 5, 3, 4 # encoding: [0x08,0xa3,0x00,0x04] +# CHECK-LE: tdi 5, 3, 4 # encoding: [0x04,0x00,0xa3,0x08] + tdlgei 3, 4 +# CHECK-BE: td 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x88] +# CHECK-LE: td 5, 3, 4 # encoding: [0x88,0x20,0xa3,0x7c] + tdlge 3, 4 + +# CHECK-BE: twi 1, 3, 4 # encoding: [0x0c,0x23,0x00,0x04] +# CHECK-LE: twi 1, 3, 4 # encoding: [0x04,0x00,0x23,0x0c] + twlgti 3, 4 +# CHECK-BE: tw 1, 3, 4 # encoding: [0x7c,0x23,0x20,0x08] +# CHECK-LE: tw 1, 3, 4 # encoding: [0x08,0x20,0x23,0x7c] + twlgt 3, 4 +# CHECK-BE: tdi 1, 3, 4 # encoding: [0x08,0x23,0x00,0x04] +# CHECK-LE: tdi 1, 3, 4 # encoding: [0x04,0x00,0x23,0x08] + tdlgti 3, 4 +# CHECK-BE: td 1, 3, 4 # encoding: [0x7c,0x23,0x20,0x88] +# CHECK-LE: td 1, 3, 4 # encoding: [0x88,0x20,0x23,0x7c] + tdlgt 3, 4 + +# CHECK-BE: twi 5, 3, 4 # encoding: [0x0c,0xa3,0x00,0x04] +# CHECK-LE: twi 5, 3, 4 # encoding: [0x04,0x00,0xa3,0x0c] + twlnli 3, 4 +# CHECK-BE: tw 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x08] +# CHECK-LE: tw 5, 3, 4 # encoding: [0x08,0x20,0xa3,0x7c] + twlnl 3, 4 +# CHECK-BE: tdi 5, 3, 4 # encoding: [0x08,0xa3,0x00,0x04] +# CHECK-LE: tdi 5, 3, 4 # encoding: [0x04,0x00,0xa3,0x08] + tdlnli 3, 4 +# CHECK-BE: td 5, 3, 4 # encoding: [0x7c,0xa3,0x20,0x88] +# CHECK-LE: td 5, 3, 4 # encoding: [0x88,0x20,0xa3,0x7c] + tdlnl 3, 4 + +# CHECK-BE: twi 6, 3, 4 # encoding: [0x0c,0xc3,0x00,0x04] +# CHECK-LE: twi 6, 3, 4 # encoding: [0x04,0x00,0xc3,0x0c] + twlngi 3, 4 +# CHECK-BE: tw 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x08] +# CHECK-LE: tw 6, 3, 4 # encoding: [0x08,0x20,0xc3,0x7c] + twlng 3, 4 +# CHECK-BE: tdi 6, 3, 4 # encoding: [0x08,0xc3,0x00,0x04] +# CHECK-LE: tdi 6, 3, 4 # encoding: [0x04,0x00,0xc3,0x08] + tdlngi 3, 4 +# CHECK-BE: td 6, 3, 4 # encoding: [0x7c,0xc3,0x20,0x88] +# CHECK-LE: td 6, 3, 4 # encoding: [0x88,0x20,0xc3,0x7c] + tdlng 3, 4 + +# CHECK-BE: twi 31, 3, 4 # encoding: [0x0f,0xe3,0x00,0x04] +# CHECK-LE: twi 31, 3, 4 # encoding: [0x04,0x00,0xe3,0x0f] + twui 3, 4 +# CHECK-BE: tw 31, 3, 4 # encoding: [0x7f,0xe3,0x20,0x08] +# CHECK-LE: tw 31, 3, 4 # encoding: [0x08,0x20,0xe3,0x7f] + twu 3, 4 +# CHECK-BE: tdi 31, 3, 4 # encoding: [0x0b,0xe3,0x00,0x04] +# CHECK-LE: tdi 31, 3, 4 # encoding: [0x04,0x00,0xe3,0x0b] + tdui 3, 4 +# CHECK-BE: td 31, 3, 4 # encoding: [0x7f,0xe3,0x20,0x88] +# CHECK-LE: td 31, 3, 4 # encoding: [0x88,0x20,0xe3,0x7f] + tdu 3, 4 + +# CHECK-BE: trap # encoding: [0x7f,0xe0,0x00,0x08] +# CHECK-LE: trap # encoding: [0x08,0x00,0xe0,0x7f] + trap # Rotate and shift mnemonics -# CHECK: rldicr 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc4] - extldi 2, 3, 4, 5 -# CHECK: rldicr. 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc5] - extldi. 2, 3, 4, 5 -# CHECK: rldicl 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x20] - extrdi 2, 3, 4, 5 -# CHECK: rldicl. 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x21] - extrdi. 2, 3, 4, 5 -# CHECK: rldimi 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4e] - insrdi 2, 3, 4, 5 -# CHECK: rldimi. 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4f] - insrdi. 2, 3, 4, 5 -# CHECK: rldicl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x00] - rotldi 2, 3, 4 -# CHECK: rldicl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x01] - rotldi. 2, 3, 4 -# CHECK: rldicl 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x02] - rotrdi 2, 3, 4 -# CHECK: rldicl. 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x03] - rotrdi. 2, 3, 4 -# CHECK: rldcl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x10] - rotld 2, 3, 4 -# CHECK: rldcl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x11] - rotld. 2, 3, 4 -# CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4] - sldi 2, 3, 4 -# CHECK: rldicr. 2, 3, 4, 59 # encoding: [0x78,0x62,0x26,0xe5] - sldi. 2, 3, 4 -# CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02] - srdi 2, 3, 4 -# CHECK: rldicl. 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x03] - srdi. 2, 3, 4 -# CHECK: rldicl 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x00] - clrldi 2, 3, 4 -# CHECK: rldicl. 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x01] - clrldi. 2, 3, 4 -# CHECK: rldicr 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe4] - clrrdi 2, 3, 4 -# CHECK: rldicr. 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe5] - clrrdi. 2, 3, 4 -# CHECK: rldic 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x48] - clrlsldi 2, 3, 5, 4 -# CHECK: rldic. 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x49] - clrlsldi. 2, 3, 5, 4 - -# CHECK: rlwinm 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x06] - extlwi 2, 3, 4, 5 -# CHECK: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x07] - extlwi. 2, 3, 4, 5 -# CHECK: rlwinm 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3e] - extrwi 2, 3, 4, 5 -# CHECK: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3f] - extrwi. 2, 3, 4, 5 -# CHECK: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x50] - inslwi 2, 3, 4, 5 -# CHECK: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x51] - inslwi. 2, 3, 4, 5 -# CHECK: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x50] - insrwi 2, 3, 4, 5 -# CHECK: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x51] - insrwi. 2, 3, 4, 5 -# CHECK: rlwinm 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3e] - rotlwi 2, 3, 4 -# CHECK: rlwinm. 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3f] - rotlwi. 2, 3, 4 -# CHECK: rlwinm 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3e] - rotrwi 2, 3, 4 -# CHECK: rlwinm. 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3f] - rotrwi. 2, 3, 4 -# CHECK: rlwnm 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3e] - rotlw 2, 3, 4 -# CHECK: rlwnm. 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3f] - rotlw. 2, 3, 4 -# CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36] - slwi 2, 3, 4 -# CHECK: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x54,0x62,0x20,0x37] - slwi. 2, 3, 4 -# CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e] - srwi 2, 3, 4 -# CHECK: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x54,0x62,0xe1,0x3f] - srwi. 2, 3, 4 -# CHECK: rlwinm 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3e] - clrlwi 2, 3, 4 -# CHECK: rlwinm. 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3f] - clrlwi. 2, 3, 4 -# CHECK: rlwinm 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x36] - clrrwi 2, 3, 4 -# CHECK: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x37] - clrrwi. 2, 3, 4 -# CHECK: rlwinm 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x76] - clrlslwi 2, 3, 5, 4 -# CHECK: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x77] - clrlslwi. 2, 3, 5, 4 +# CHECK-BE: rldicr 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc4] +# CHECK-LE: rldicr 2, 3, 5, 3 # encoding: [0xc4,0x28,0x62,0x78] + extldi 2, 3, 4, 5 +# CHECK-BE: rldicr. 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc5] +# CHECK-LE: rldicr. 2, 3, 5, 3 # encoding: [0xc5,0x28,0x62,0x78] + extldi. 2, 3, 4, 5 +# CHECK-BE: rldicl 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x20] +# CHECK-LE: rldicl 2, 3, 9, 60 # encoding: [0x20,0x4f,0x62,0x78] + extrdi 2, 3, 4, 5 +# CHECK-BE: rldicl. 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x21] +# CHECK-LE: rldicl. 2, 3, 9, 60 # encoding: [0x21,0x4f,0x62,0x78] + extrdi. 2, 3, 4, 5 +# CHECK-BE: rldimi 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4e] +# CHECK-LE: rldimi 2, 3, 55, 5 # encoding: [0x4e,0xb9,0x62,0x78] + insrdi 2, 3, 4, 5 +# CHECK-BE: rldimi. 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4f] +# CHECK-LE: rldimi. 2, 3, 55, 5 # encoding: [0x4f,0xb9,0x62,0x78] + insrdi. 2, 3, 4, 5 +# CHECK-BE: rldicl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x00] +# CHECK-LE: rldicl 2, 3, 4, 0 # encoding: [0x00,0x20,0x62,0x78] + rotldi 2, 3, 4 +# CHECK-BE: rldicl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x01] +# CHECK-LE: rldicl. 2, 3, 4, 0 # encoding: [0x01,0x20,0x62,0x78] + rotldi. 2, 3, 4 +# CHECK-BE: rldicl 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x02] +# CHECK-LE: rldicl 2, 3, 60, 0 # encoding: [0x02,0xe0,0x62,0x78] + rotrdi 2, 3, 4 +# CHECK-BE: rldicl. 2, 3, 60, 0 # encoding: [0x78,0x62,0xe0,0x03] +# CHECK-LE: rldicl. 2, 3, 60, 0 # encoding: [0x03,0xe0,0x62,0x78] + rotrdi. 2, 3, 4 +# CHECK-BE: rldcl 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x10] +# CHECK-LE: rldcl 2, 3, 4, 0 # encoding: [0x10,0x20,0x62,0x78] + rotld 2, 3, 4 +# CHECK-BE: rldcl. 2, 3, 4, 0 # encoding: [0x78,0x62,0x20,0x11] +# CHECK-LE: rldcl. 2, 3, 4, 0 # encoding: [0x11,0x20,0x62,0x78] + rotld. 2, 3, 4 +# CHECK-BE: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4] +# CHECK-LE: sldi 2, 3, 4 # encoding: [0xe4,0x26,0x62,0x78] + sldi 2, 3, 4 +# CHECK-BE: rldicr. 2, 3, 4, 59 # encoding: [0x78,0x62,0x26,0xe5] +# CHECK-LE: rldicr. 2, 3, 4, 59 # encoding: [0xe5,0x26,0x62,0x78] + sldi. 2, 3, 4 +# CHECK-BE: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02] +# CHECK-LE: rldicl 2, 3, 60, 4 # encoding: [0x02,0xe1,0x62,0x78] + srdi 2, 3, 4 +# CHECK-BE: rldicl. 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x03] +# CHECK-LE: rldicl. 2, 3, 60, 4 # encoding: [0x03,0xe1,0x62,0x78] + srdi. 2, 3, 4 +# CHECK-BE: rldicl 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x00] +# CHECK-LE: rldicl 2, 3, 0, 4 # encoding: [0x00,0x01,0x62,0x78] + clrldi 2, 3, 4 +# CHECK-BE: rldicl. 2, 3, 0, 4 # encoding: [0x78,0x62,0x01,0x01] +# CHECK-LE: rldicl. 2, 3, 0, 4 # encoding: [0x01,0x01,0x62,0x78] + clrldi. 2, 3, 4 +# CHECK-BE: rldicr 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe4] +# CHECK-LE: rldicr 2, 3, 0, 59 # encoding: [0xe4,0x06,0x62,0x78] + clrrdi 2, 3, 4 +# CHECK-BE: rldicr. 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe5] +# CHECK-LE: rldicr. 2, 3, 0, 59 # encoding: [0xe5,0x06,0x62,0x78] + clrrdi. 2, 3, 4 +# CHECK-BE: rldic 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x48] +# CHECK-LE: rldic 2, 3, 4, 1 # encoding: [0x48,0x20,0x62,0x78] + clrlsldi 2, 3, 5, 4 +# CHECK-BE: rldic. 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x49] +# CHECK-LE: rldic. 2, 3, 4, 1 # encoding: [0x49,0x20,0x62,0x78] + clrlsldi. 2, 3, 5, 4 + +# CHECK-BE: rlwinm 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x06] +# CHECK-LE: rlwinm 2, 3, 5, 0, 3 # encoding: [0x06,0x28,0x62,0x54] + extlwi 2, 3, 4, 5 +# CHECK-BE: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x07] +# CHECK-LE: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x07,0x28,0x62,0x54] + extlwi. 2, 3, 4, 5 +# CHECK-BE: rlwinm 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3e] +# CHECK-LE: rlwinm 2, 3, 9, 28, 31 # encoding: [0x3e,0x4f,0x62,0x54] + extrwi 2, 3, 4, 5 +# CHECK-BE: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3f] +# CHECK-LE: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x3f,0x4f,0x62,0x54] + extrwi. 2, 3, 4, 5 +# CHECK-BE: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x50] +# CHECK-LE: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0xd9,0x62,0x50] + inslwi 2, 3, 4, 5 +# CHECK-BE: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x51] +# CHECK-LE: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x51,0xd9,0x62,0x50] + inslwi. 2, 3, 4, 5 +# CHECK-BE: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x50] +# CHECK-LE: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0xb9,0x62,0x50] + insrwi 2, 3, 4, 5 +# CHECK-BE: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x51] +# CHECK-LE: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x51,0xb9,0x62,0x50] + insrwi. 2, 3, 4, 5 +# CHECK-BE: rlwinm 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3e] +# CHECK-LE: rlwinm 2, 3, 4, 0, 31 # encoding: [0x3e,0x20,0x62,0x54] + rotlwi 2, 3, 4 +# CHECK-BE: rlwinm. 2, 3, 4, 0, 31 # encoding: [0x54,0x62,0x20,0x3f] +# CHECK-LE: rlwinm. 2, 3, 4, 0, 31 # encoding: [0x3f,0x20,0x62,0x54] + rotlwi. 2, 3, 4 +# CHECK-BE: rlwinm 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3e] +# CHECK-LE: rlwinm 2, 3, 28, 0, 31 # encoding: [0x3e,0xe0,0x62,0x54] + rotrwi 2, 3, 4 +# CHECK-BE: rlwinm. 2, 3, 28, 0, 31 # encoding: [0x54,0x62,0xe0,0x3f] +# CHECK-LE: rlwinm. 2, 3, 28, 0, 31 # encoding: [0x3f,0xe0,0x62,0x54] + rotrwi. 2, 3, 4 +# CHECK-BE: rlwnm 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3e] +# CHECK-LE: rlwnm 2, 3, 4, 0, 31 # encoding: [0x3e,0x20,0x62,0x5c] + rotlw 2, 3, 4 +# CHECK-BE: rlwnm. 2, 3, 4, 0, 31 # encoding: [0x5c,0x62,0x20,0x3f] +# CHECK-LE: rlwnm. 2, 3, 4, 0, 31 # encoding: [0x3f,0x20,0x62,0x5c] + rotlw. 2, 3, 4 +# CHECK-BE: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36] +# CHECK-LE: slwi 2, 3, 4 # encoding: [0x36,0x20,0x62,0x54] + slwi 2, 3, 4 +# CHECK-BE: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x54,0x62,0x20,0x37] +# CHECK-LE: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x37,0x20,0x62,0x54] + slwi. 2, 3, 4 +# CHECK-BE: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e] +# CHECK-LE: srwi 2, 3, 4 # encoding: [0x3e,0xe1,0x62,0x54] + srwi 2, 3, 4 +# CHECK-BE: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x54,0x62,0xe1,0x3f] +# CHECK-LE: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x3f,0xe1,0x62,0x54] + srwi. 2, 3, 4 +# CHECK-BE: rlwinm 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3e] +# CHECK-LE: rlwinm 2, 3, 0, 4, 31 # encoding: [0x3e,0x01,0x62,0x54] + clrlwi 2, 3, 4 +# CHECK-BE: rlwinm. 2, 3, 0, 4, 31 # encoding: [0x54,0x62,0x01,0x3f] +# CHECK-LE: rlwinm. 2, 3, 0, 4, 31 # encoding: [0x3f,0x01,0x62,0x54] + clrlwi. 2, 3, 4 +# CHECK-BE: rlwinm 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x36] +# CHECK-LE: rlwinm 2, 3, 0, 0, 27 # encoding: [0x36,0x00,0x62,0x54] + clrrwi 2, 3, 4 +# CHECK-BE: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x37] +# CHECK-LE: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x37,0x00,0x62,0x54] + clrrwi. 2, 3, 4 +# CHECK-BE: rlwinm 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x76] +# CHECK-LE: rlwinm 2, 3, 4, 1, 27 # encoding: [0x76,0x20,0x62,0x54] + clrlslwi 2, 3, 5, 4 +# CHECK-BE: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x77] +# CHECK-LE: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x77,0x20,0x62,0x54] + clrlslwi. 2, 3, 5, 4 # Move to/from special purpose register mnemonics -# CHECK: mtspr 1, 2 # encoding: [0x7c,0x41,0x03,0xa6] - mtxer 2 -# CHECK: mfspr 2, 1 # encoding: [0x7c,0x41,0x02,0xa6] - mfxer 2 -# CHECK: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6] - mtlr 2 -# CHECK: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6] - mflr 2 -# CHECK: mtctr 2 # encoding: [0x7c,0x49,0x03,0xa6] - mtctr 2 -# CHECK: mfctr 2 # encoding: [0x7c,0x49,0x02,0xa6] - mfctr 2 +# CHECK-BE: mtspr 1, 2 # encoding: [0x7c,0x41,0x03,0xa6] +# CHECK-LE: mtspr 1, 2 # encoding: [0xa6,0x03,0x41,0x7c] + mtxer 2 +# CHECK-BE: mfspr 2, 1 # encoding: [0x7c,0x41,0x02,0xa6] +# CHECK-LE: mfspr 2, 1 # encoding: [0xa6,0x02,0x41,0x7c] + mfxer 2 +# CHECK-BE: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6] +# CHECK-LE: mtlr 2 # encoding: [0xa6,0x03,0x48,0x7c] + mtlr 2 +# CHECK-BE: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6] +# CHECK-LE: mflr 2 # encoding: [0xa6,0x02,0x48,0x7c] + mflr 2 +# CHECK-BE: mtctr 2 # encoding: [0x7c,0x49,0x03,0xa6] +# CHECK-LE: mtctr 2 # encoding: [0xa6,0x03,0x49,0x7c] + mtctr 2 +# CHECK-BE: mfctr 2 # encoding: [0x7c,0x49,0x02,0xa6] +# CHECK-LE: mfctr 2 # encoding: [0xa6,0x02,0x49,0x7c] + mfctr 2 # Miscellaneous mnemonics -# CHECK: nop # encoding: [0x60,0x00,0x00,0x00] - nop -# CHECK: xori 0, 0, 0 # encoding: [0x68,0x00,0x00,0x00] - xnop -# CHECK: li 2, 128 # encoding: [0x38,0x40,0x00,0x80] - li 2, 128 -# CHECK: lis 2, 128 # encoding: [0x3c,0x40,0x00,0x80] - lis 2, 128 -# CHECK: la 2, 128(4) - la 2, 128(4) -# CHECK: mr 2, 3 # encoding: [0x7c,0x62,0x1b,0x78] - mr 2, 3 -# CHECK: or. 2, 3, 3 # encoding: [0x7c,0x62,0x1b,0x79] - mr. 2, 3 -# CHECK: nor 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf8] - not 2, 3 -# CHECK: nor. 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf9] - not. 2, 3 -# CHECK: mtcrf 255, 2 # encoding: [0x7c,0x4f,0xf1,0x20] - mtcr 2 +# CHECK-BE: nop # encoding: [0x60,0x00,0x00,0x00] +# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x60] + nop +# CHECK-BE: xori 0, 0, 0 # encoding: [0x68,0x00,0x00,0x00] +# CHECK-LE: xori 0, 0, 0 # encoding: [0x00,0x00,0x00,0x68] + xnop +# CHECK-BE: li 2, 128 # encoding: [0x38,0x40,0x00,0x80] +# CHECK-LE: li 2, 128 # encoding: [0x80,0x00,0x40,0x38] + li 2, 128 +# CHECK-BE: lis 2, 128 # encoding: [0x3c,0x40,0x00,0x80] +# CHECK-LE: lis 2, 128 # encoding: [0x80,0x00,0x40,0x3c] + lis 2, 128 +# CHECK-BE: la 2, 128(4) +# CHECK-LE: la 2, 128(4) + la 2, 128(4) +# CHECK-BE: mr 2, 3 # encoding: [0x7c,0x62,0x1b,0x78] +# CHECK-LE: mr 2, 3 # encoding: [0x78,0x1b,0x62,0x7c] + mr 2, 3 +# CHECK-BE: or. 2, 3, 3 # encoding: [0x7c,0x62,0x1b,0x79] +# CHECK-LE: or. 2, 3, 3 # encoding: [0x79,0x1b,0x62,0x7c] + mr. 2, 3 +# CHECK-BE: nor 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf8] +# CHECK-LE: nor 2, 3, 3 # encoding: [0xf8,0x18,0x62,0x7c] + not 2, 3 +# CHECK-BE: nor. 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf9] +# CHECK-LE: nor. 2, 3, 3 # encoding: [0xf9,0x18,0x62,0x7c] + not. 2, 3 +# CHECK-BE: mtcrf 255, 2 # encoding: [0x7c,0x4f,0xf1,0x20] +# CHECK-LE: mtcrf 255, 2 # encoding: [0x20,0xf1,0x4f,0x7c] + mtcr 2 Index: llvm-suse/test/MC/PowerPC/ppc64-encoding-fp.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-encoding-fp.s +++ llvm-suse/test/MC/PowerPC/ppc64-encoding-fp.s @@ -1,269 +1,379 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Floating-point facility # Floating-point load instructions -# CHECK: lfs 2, 128(4) # encoding: [0xc0,0x44,0x00,0x80] - lfs 2, 128(4) -# CHECK: lfsx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x2e] - lfsx 2, 3, 4 -# CHECK: lfsu 2, 128(4) # encoding: [0xc4,0x44,0x00,0x80] - lfsu 2, 128(4) -# CHECK: lfsux 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x6e] - lfsux 2, 3, 4 -# CHECK: lfd 2, 128(4) # encoding: [0xc8,0x44,0x00,0x80] - lfd 2, 128(4) -# CHECK: lfdx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0xae] - lfdx 2, 3, 4 -# CHECK: lfdu 2, 128(4) # encoding: [0xcc,0x44,0x00,0x80] - lfdu 2, 128(4) -# CHECK: lfdux 2, 3, 4 # encoding: [0x7c,0x43,0x24,0xee] - lfdux 2, 3, 4 -# CHECK: lfiwax 2, 3, 4 # encoding: [0x7c,0x43,0x26,0xae] - lfiwax 2, 3, 4 -# CHECK: lfiwzx 2, 3, 4 # encoding: [0x7c,0x43,0x26,0xee] - lfiwzx 2, 3, 4 +# CHECK-BE: lfs 2, 128(4) # encoding: [0xc0,0x44,0x00,0x80] +# CHECK-LE: lfs 2, 128(4) # encoding: [0x80,0x00,0x44,0xc0] + lfs 2, 128(4) +# CHECK-BE: lfsx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x2e] +# CHECK-LE: lfsx 2, 3, 4 # encoding: [0x2e,0x24,0x43,0x7c] + lfsx 2, 3, 4 +# CHECK-BE: lfsu 2, 128(4) # encoding: [0xc4,0x44,0x00,0x80] +# CHECK-LE: lfsu 2, 128(4) # encoding: [0x80,0x00,0x44,0xc4] + lfsu 2, 128(4) +# CHECK-BE: lfsux 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x6e] +# CHECK-LE: lfsux 2, 3, 4 # encoding: [0x6e,0x24,0x43,0x7c] + lfsux 2, 3, 4 +# CHECK-BE: lfd 2, 128(4) # encoding: [0xc8,0x44,0x00,0x80] +# CHECK-LE: lfd 2, 128(4) # encoding: [0x80,0x00,0x44,0xc8] + lfd 2, 128(4) +# CHECK-BE: lfdx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0xae] +# CHECK-LE: lfdx 2, 3, 4 # encoding: [0xae,0x24,0x43,0x7c] + lfdx 2, 3, 4 +# CHECK-BE: lfdu 2, 128(4) # encoding: [0xcc,0x44,0x00,0x80] +# CHECK-LE: lfdu 2, 128(4) # encoding: [0x80,0x00,0x44,0xcc] + lfdu 2, 128(4) +# CHECK-BE: lfdux 2, 3, 4 # encoding: [0x7c,0x43,0x24,0xee] +# CHECK-LE: lfdux 2, 3, 4 # encoding: [0xee,0x24,0x43,0x7c] + lfdux 2, 3, 4 +# CHECK-BE: lfiwax 2, 3, 4 # encoding: [0x7c,0x43,0x26,0xae] +# CHECK-LE: lfiwax 2, 3, 4 # encoding: [0xae,0x26,0x43,0x7c] + lfiwax 2, 3, 4 +# CHECK-BE: lfiwzx 2, 3, 4 # encoding: [0x7c,0x43,0x26,0xee] +# CHECK-LE: lfiwzx 2, 3, 4 # encoding: [0xee,0x26,0x43,0x7c] + lfiwzx 2, 3, 4 # Floating-point store instructions -# CHECK: stfs 2, 128(4) # encoding: [0xd0,0x44,0x00,0x80] - stfs 2, 128(4) -# CHECK: stfsx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x2e] - stfsx 2, 3, 4 -# CHECK: stfsu 2, 128(4) # encoding: [0xd4,0x44,0x00,0x80] - stfsu 2, 128(4) -# CHECK: stfsux 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x6e] - stfsux 2, 3, 4 -# CHECK: stfd 2, 128(4) # encoding: [0xd8,0x44,0x00,0x80] - stfd 2, 128(4) -# CHECK: stfdx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0xae] - stfdx 2, 3, 4 -# CHECK: stfdu 2, 128(4) # encoding: [0xdc,0x44,0x00,0x80] - stfdu 2, 128(4) -# CHECK: stfdux 2, 3, 4 # encoding: [0x7c,0x43,0x25,0xee] - stfdux 2, 3, 4 -# CHECK: stfiwx 2, 3, 4 # encoding: [0x7c,0x43,0x27,0xae] - stfiwx 2, 3, 4 +# CHECK-BE: stfs 2, 128(4) # encoding: [0xd0,0x44,0x00,0x80] +# CHECK-LE: stfs 2, 128(4) # encoding: [0x80,0x00,0x44,0xd0] + stfs 2, 128(4) +# CHECK-BE: stfsx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x2e] +# CHECK-LE: stfsx 2, 3, 4 # encoding: [0x2e,0x25,0x43,0x7c] + stfsx 2, 3, 4 +# CHECK-BE: stfsu 2, 128(4) # encoding: [0xd4,0x44,0x00,0x80] +# CHECK-LE: stfsu 2, 128(4) # encoding: [0x80,0x00,0x44,0xd4] + stfsu 2, 128(4) +# CHECK-BE: stfsux 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x6e] +# CHECK-LE: stfsux 2, 3, 4 # encoding: [0x6e,0x25,0x43,0x7c] + stfsux 2, 3, 4 +# CHECK-BE: stfd 2, 128(4) # encoding: [0xd8,0x44,0x00,0x80] +# CHECK-LE: stfd 2, 128(4) # encoding: [0x80,0x00,0x44,0xd8] + stfd 2, 128(4) +# CHECK-BE: stfdx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0xae] +# CHECK-LE: stfdx 2, 3, 4 # encoding: [0xae,0x25,0x43,0x7c] + stfdx 2, 3, 4 +# CHECK-BE: stfdu 2, 128(4) # encoding: [0xdc,0x44,0x00,0x80] +# CHECK-LE: stfdu 2, 128(4) # encoding: [0x80,0x00,0x44,0xdc] + stfdu 2, 128(4) +# CHECK-BE: stfdux 2, 3, 4 # encoding: [0x7c,0x43,0x25,0xee] +# CHECK-LE: stfdux 2, 3, 4 # encoding: [0xee,0x25,0x43,0x7c] + stfdux 2, 3, 4 +# CHECK-BE: stfiwx 2, 3, 4 # encoding: [0x7c,0x43,0x27,0xae] +# CHECK-LE: stfiwx 2, 3, 4 # encoding: [0xae,0x27,0x43,0x7c] + stfiwx 2, 3, 4 # Floating-point move instructions -# CHECK: fmr 2, 3 # encoding: [0xfc,0x40,0x18,0x90] - fmr 2, 3 -# CHECK: fmr. 2, 3 # encoding: [0xfc,0x40,0x18,0x91] - fmr. 2, 3 -# CHECK: fneg 2, 3 # encoding: [0xfc,0x40,0x18,0x50] - fneg 2, 3 -# CHECK: fneg. 2, 3 # encoding: [0xfc,0x40,0x18,0x51] - fneg. 2, 3 -# CHECK: fabs 2, 3 # encoding: [0xfc,0x40,0x1a,0x10] - fabs 2, 3 -# CHECK: fabs. 2, 3 # encoding: [0xfc,0x40,0x1a,0x11] - fabs. 2, 3 -# CHECK: fnabs 2, 3 # encoding: [0xfc,0x40,0x19,0x10] - fnabs 2, 3 -# CHECK: fnabs. 2, 3 # encoding: [0xfc,0x40,0x19,0x11] - fnabs. 2, 3 -# CHECK: fcpsgn 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x10] - fcpsgn 2, 3, 4 -# CHECK: fcpsgn. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x11] - fcpsgn. 2, 3, 4 +# CHECK-BE: fmr 2, 3 # encoding: [0xfc,0x40,0x18,0x90] +# CHECK-LE: fmr 2, 3 # encoding: [0x90,0x18,0x40,0xfc] + fmr 2, 3 +# CHECK-BE: fmr. 2, 3 # encoding: [0xfc,0x40,0x18,0x91] +# CHECK-LE: fmr. 2, 3 # encoding: [0x91,0x18,0x40,0xfc] + fmr. 2, 3 +# CHECK-BE: fneg 2, 3 # encoding: [0xfc,0x40,0x18,0x50] +# CHECK-LE: fneg 2, 3 # encoding: [0x50,0x18,0x40,0xfc] + fneg 2, 3 +# CHECK-BE: fneg. 2, 3 # encoding: [0xfc,0x40,0x18,0x51] +# CHECK-LE: fneg. 2, 3 # encoding: [0x51,0x18,0x40,0xfc] + fneg. 2, 3 +# CHECK-BE: fabs 2, 3 # encoding: [0xfc,0x40,0x1a,0x10] +# CHECK-LE: fabs 2, 3 # encoding: [0x10,0x1a,0x40,0xfc] + fabs 2, 3 +# CHECK-BE: fabs. 2, 3 # encoding: [0xfc,0x40,0x1a,0x11] +# CHECK-LE: fabs. 2, 3 # encoding: [0x11,0x1a,0x40,0xfc] + fabs. 2, 3 +# CHECK-BE: fnabs 2, 3 # encoding: [0xfc,0x40,0x19,0x10] +# CHECK-LE: fnabs 2, 3 # encoding: [0x10,0x19,0x40,0xfc] + fnabs 2, 3 +# CHECK-BE: fnabs. 2, 3 # encoding: [0xfc,0x40,0x19,0x11] +# CHECK-LE: fnabs. 2, 3 # encoding: [0x11,0x19,0x40,0xfc] + fnabs. 2, 3 +# CHECK-BE: fcpsgn 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x10] +# CHECK-LE: fcpsgn 2, 3, 4 # encoding: [0x10,0x20,0x43,0xfc] + fcpsgn 2, 3, 4 +# CHECK-BE: fcpsgn. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x11] +# CHECK-LE: fcpsgn. 2, 3, 4 # encoding: [0x11,0x20,0x43,0xfc] + fcpsgn. 2, 3, 4 # Floating-point arithmetic instructions -# CHECK: fadd 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x2a] - fadd 2, 3, 4 -# CHECK: fadd. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x2b] - fadd. 2, 3, 4 -# CHECK: fadds 2, 3, 4 # encoding: [0xec,0x43,0x20,0x2a] - fadds 2, 3, 4 -# CHECK: fadds. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x2b] - fadds. 2, 3, 4 -# CHECK: fsub 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x28] - fsub 2, 3, 4 -# CHECK: fsub. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x29] - fsub. 2, 3, 4 -# CHECK: fsubs 2, 3, 4 # encoding: [0xec,0x43,0x20,0x28] - fsubs 2, 3, 4 -# CHECK: fsubs. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x29] - fsubs. 2, 3, 4 - -# CHECK: fmul 2, 3, 4 # encoding: [0xfc,0x43,0x01,0x32] - fmul 2, 3, 4 -# CHECK: fmul. 2, 3, 4 # encoding: [0xfc,0x43,0x01,0x33] - fmul. 2, 3, 4 -# CHECK: fmuls 2, 3, 4 # encoding: [0xec,0x43,0x01,0x32] - fmuls 2, 3, 4 -# CHECK: fmuls. 2, 3, 4 # encoding: [0xec,0x43,0x01,0x33] - fmuls. 2, 3, 4 -# CHECK: fdiv 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x24] - fdiv 2, 3, 4 -# CHECK: fdiv. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x25] - fdiv. 2, 3, 4 -# CHECK: fdivs 2, 3, 4 # encoding: [0xec,0x43,0x20,0x24] - fdivs 2, 3, 4 -# CHECK: fdivs. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x25] - fdivs. 2, 3, 4 -# CHECK: fsqrt 2, 3 # encoding: [0xfc,0x40,0x18,0x2c] - fsqrt 2, 3 -# CHECK: fsqrt. 2, 3 # encoding: [0xfc,0x40,0x18,0x2d] - fsqrt. 2, 3 -# CHECK: fsqrts 2, 3 # encoding: [0xec,0x40,0x18,0x2c] - fsqrts 2, 3 -# CHECK: fsqrts. 2, 3 # encoding: [0xec,0x40,0x18,0x2d] - fsqrts. 2, 3 - -# CHECK: fre 2, 3 # encoding: [0xfc,0x40,0x18,0x30] - fre 2, 3 -# CHECK: fre. 2, 3 # encoding: [0xfc,0x40,0x18,0x31] - fre. 2, 3 -# CHECK: fres 2, 3 # encoding: [0xec,0x40,0x18,0x30] - fres 2, 3 -# CHECK: fres. 2, 3 # encoding: [0xec,0x40,0x18,0x31] - fres. 2, 3 -# CHECK: frsqrte 2, 3 # encoding: [0xfc,0x40,0x18,0x34] - frsqrte 2, 3 -# CHECK: frsqrte. 2, 3 # encoding: [0xfc,0x40,0x18,0x35] - frsqrte. 2, 3 -# CHECK: frsqrtes 2, 3 # encoding: [0xec,0x40,0x18,0x34] - frsqrtes 2, 3 -# CHECK: frsqrtes. 2, 3 # encoding: [0xec,0x40,0x18,0x35] - frsqrtes. 2, 3 -# FIXME: ftdiv 2, 3, 4 -# FIXME: ftsqrt 2, 3, 4 - -# CHECK: fmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3a] - fmadd 2, 3, 4, 5 -# CHECK: fmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3b] - fmadd. 2, 3, 4, 5 -# CHECK: fmadds 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3a] - fmadds 2, 3, 4, 5 -# CHECK: fmadds. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3b] - fmadds. 2, 3, 4, 5 -# CHECK: fmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x38] - fmsub 2, 3, 4, 5 -# CHECK: fmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x39] - fmsub. 2, 3, 4, 5 -# CHECK: fmsubs 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x38] - fmsubs 2, 3, 4, 5 -# CHECK: fmsubs. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x39] - fmsubs. 2, 3, 4, 5 -# CHECK: fnmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3e] - fnmadd 2, 3, 4, 5 -# CHECK: fnmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3f] - fnmadd. 2, 3, 4, 5 -# CHECK: fnmadds 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3e] - fnmadds 2, 3, 4, 5 -# CHECK: fnmadds. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3f] - fnmadds. 2, 3, 4, 5 -# CHECK: fnmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3c] - fnmsub 2, 3, 4, 5 -# CHECK: fnmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3d] - fnmsub. 2, 3, 4, 5 -# CHECK: fnmsubs 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3c] - fnmsubs 2, 3, 4, 5 -# CHECK: fnmsubs. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3d] - fnmsubs. 2, 3, 4, 5 +# CHECK-BE: fadd 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x2a] +# CHECK-LE: fadd 2, 3, 4 # encoding: [0x2a,0x20,0x43,0xfc] + fadd 2, 3, 4 +# CHECK-BE: fadd. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x2b] +# CHECK-LE: fadd. 2, 3, 4 # encoding: [0x2b,0x20,0x43,0xfc] + fadd. 2, 3, 4 +# CHECK-BE: fadds 2, 3, 4 # encoding: [0xec,0x43,0x20,0x2a] +# CHECK-LE: fadds 2, 3, 4 # encoding: [0x2a,0x20,0x43,0xec] + fadds 2, 3, 4 +# CHECK-BE: fadds. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x2b] +# CHECK-LE: fadds. 2, 3, 4 # encoding: [0x2b,0x20,0x43,0xec] + fadds. 2, 3, 4 +# CHECK-BE: fsub 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x28] +# CHECK-LE: fsub 2, 3, 4 # encoding: [0x28,0x20,0x43,0xfc] + fsub 2, 3, 4 +# CHECK-BE: fsub. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x29] +# CHECK-LE: fsub. 2, 3, 4 # encoding: [0x29,0x20,0x43,0xfc] + fsub. 2, 3, 4 +# CHECK-BE: fsubs 2, 3, 4 # encoding: [0xec,0x43,0x20,0x28] +# CHECK-LE: fsubs 2, 3, 4 # encoding: [0x28,0x20,0x43,0xec] + fsubs 2, 3, 4 +# CHECK-BE: fsubs. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x29] +# CHECK-LE: fsubs. 2, 3, 4 # encoding: [0x29,0x20,0x43,0xec] + fsubs. 2, 3, 4 + +# CHECK-BE: fmul 2, 3, 4 # encoding: [0xfc,0x43,0x01,0x32] +# CHECK-LE: fmul 2, 3, 4 # encoding: [0x32,0x01,0x43,0xfc] + fmul 2, 3, 4 +# CHECK-BE: fmul. 2, 3, 4 # encoding: [0xfc,0x43,0x01,0x33] +# CHECK-LE: fmul. 2, 3, 4 # encoding: [0x33,0x01,0x43,0xfc] + fmul. 2, 3, 4 +# CHECK-BE: fmuls 2, 3, 4 # encoding: [0xec,0x43,0x01,0x32] +# CHECK-LE: fmuls 2, 3, 4 # encoding: [0x32,0x01,0x43,0xec] + fmuls 2, 3, 4 +# CHECK-BE: fmuls. 2, 3, 4 # encoding: [0xec,0x43,0x01,0x33] +# CHECK-LE: fmuls. 2, 3, 4 # encoding: [0x33,0x01,0x43,0xec] + fmuls. 2, 3, 4 +# CHECK-BE: fdiv 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x24] +# CHECK-LE: fdiv 2, 3, 4 # encoding: [0x24,0x20,0x43,0xfc] + fdiv 2, 3, 4 +# CHECK-BE: fdiv. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x25] +# CHECK-LE: fdiv. 2, 3, 4 # encoding: [0x25,0x20,0x43,0xfc] + fdiv. 2, 3, 4 +# CHECK-BE: fdivs 2, 3, 4 # encoding: [0xec,0x43,0x20,0x24] +# CHECK-LE: fdivs 2, 3, 4 # encoding: [0x24,0x20,0x43,0xec] + fdivs 2, 3, 4 +# CHECK-BE: fdivs. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x25] +# CHECK-LE: fdivs. 2, 3, 4 # encoding: [0x25,0x20,0x43,0xec] + fdivs. 2, 3, 4 +# CHECK-BE: fsqrt 2, 3 # encoding: [0xfc,0x40,0x18,0x2c] +# CHECK-LE: fsqrt 2, 3 # encoding: [0x2c,0x18,0x40,0xfc] + fsqrt 2, 3 +# CHECK-BE: fsqrt. 2, 3 # encoding: [0xfc,0x40,0x18,0x2d] +# CHECK-LE: fsqrt. 2, 3 # encoding: [0x2d,0x18,0x40,0xfc] + fsqrt. 2, 3 +# CHECK-BE: fsqrts 2, 3 # encoding: [0xec,0x40,0x18,0x2c] +# CHECK-LE: fsqrts 2, 3 # encoding: [0x2c,0x18,0x40,0xec] + fsqrts 2, 3 +# CHECK-BE: fsqrts. 2, 3 # encoding: [0xec,0x40,0x18,0x2d] +# CHECK-LE: fsqrts. 2, 3 # encoding: [0x2d,0x18,0x40,0xec] + fsqrts. 2, 3 + +# CHECK-BE: fre 2, 3 # encoding: [0xfc,0x40,0x18,0x30] +# CHECK-LE: fre 2, 3 # encoding: [0x30,0x18,0x40,0xfc] + fre 2, 3 +# CHECK-BE: fre. 2, 3 # encoding: [0xfc,0x40,0x18,0x31] +# CHECK-LE: fre. 2, 3 # encoding: [0x31,0x18,0x40,0xfc] + fre. 2, 3 +# CHECK-BE: fres 2, 3 # encoding: [0xec,0x40,0x18,0x30] +# CHECK-LE: fres 2, 3 # encoding: [0x30,0x18,0x40,0xec] + fres 2, 3 +# CHECK-BE: fres. 2, 3 # encoding: [0xec,0x40,0x18,0x31] +# CHECK-LE: fres. 2, 3 # encoding: [0x31,0x18,0x40,0xec] + fres. 2, 3 +# CHECK-BE: frsqrte 2, 3 # encoding: [0xfc,0x40,0x18,0x34] +# CHECK-LE: frsqrte 2, 3 # encoding: [0x34,0x18,0x40,0xfc] + frsqrte 2, 3 +# CHECK-BE: frsqrte. 2, 3 # encoding: [0xfc,0x40,0x18,0x35] +# CHECK-LE: frsqrte. 2, 3 # encoding: [0x35,0x18,0x40,0xfc] + frsqrte. 2, 3 +# CHECK-BE: frsqrtes 2, 3 # encoding: [0xec,0x40,0x18,0x34] +# CHECK-LE: frsqrtes 2, 3 # encoding: [0x34,0x18,0x40,0xec] + frsqrtes 2, 3 +# CHECK-BE: frsqrtes. 2, 3 # encoding: [0xec,0x40,0x18,0x35] +# CHECK-LE: frsqrtes. 2, 3 # encoding: [0x35,0x18,0x40,0xec] + frsqrtes. 2, 3 +# FIXME: ftdiv 2, 3, 4 +# FIXME: ftsqrt 2, 3, 4 + +# CHECK-BE: fmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3a] +# CHECK-LE: fmadd 2, 3, 4, 5 # encoding: [0x3a,0x29,0x43,0xfc] + fmadd 2, 3, 4, 5 +# CHECK-BE: fmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3b] +# CHECK-LE: fmadd. 2, 3, 4, 5 # encoding: [0x3b,0x29,0x43,0xfc] + fmadd. 2, 3, 4, 5 +# CHECK-BE: fmadds 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3a] +# CHECK-LE: fmadds 2, 3, 4, 5 # encoding: [0x3a,0x29,0x43,0xec] + fmadds 2, 3, 4, 5 +# CHECK-BE: fmadds. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3b] +# CHECK-LE: fmadds. 2, 3, 4, 5 # encoding: [0x3b,0x29,0x43,0xec] + fmadds. 2, 3, 4, 5 +# CHECK-BE: fmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x38] +# CHECK-LE: fmsub 2, 3, 4, 5 # encoding: [0x38,0x29,0x43,0xfc] + fmsub 2, 3, 4, 5 +# CHECK-BE: fmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x39] +# CHECK-LE: fmsub. 2, 3, 4, 5 # encoding: [0x39,0x29,0x43,0xfc] + fmsub. 2, 3, 4, 5 +# CHECK-BE: fmsubs 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x38] +# CHECK-LE: fmsubs 2, 3, 4, 5 # encoding: [0x38,0x29,0x43,0xec] + fmsubs 2, 3, 4, 5 +# CHECK-BE: fmsubs. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x39] +# CHECK-LE: fmsubs. 2, 3, 4, 5 # encoding: [0x39,0x29,0x43,0xec] + fmsubs. 2, 3, 4, 5 +# CHECK-BE: fnmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3e] +# CHECK-LE: fnmadd 2, 3, 4, 5 # encoding: [0x3e,0x29,0x43,0xfc] + fnmadd 2, 3, 4, 5 +# CHECK-BE: fnmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3f] +# CHECK-LE: fnmadd. 2, 3, 4, 5 # encoding: [0x3f,0x29,0x43,0xfc] + fnmadd. 2, 3, 4, 5 +# CHECK-BE: fnmadds 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3e] +# CHECK-LE: fnmadds 2, 3, 4, 5 # encoding: [0x3e,0x29,0x43,0xec] + fnmadds 2, 3, 4, 5 +# CHECK-BE: fnmadds. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3f] +# CHECK-LE: fnmadds. 2, 3, 4, 5 # encoding: [0x3f,0x29,0x43,0xec] + fnmadds. 2, 3, 4, 5 +# CHECK-BE: fnmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3c] +# CHECK-LE: fnmsub 2, 3, 4, 5 # encoding: [0x3c,0x29,0x43,0xfc] + fnmsub 2, 3, 4, 5 +# CHECK-BE: fnmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3d] +# CHECK-LE: fnmsub. 2, 3, 4, 5 # encoding: [0x3d,0x29,0x43,0xfc] + fnmsub. 2, 3, 4, 5 +# CHECK-BE: fnmsubs 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3c] +# CHECK-LE: fnmsubs 2, 3, 4, 5 # encoding: [0x3c,0x29,0x43,0xec] + fnmsubs 2, 3, 4, 5 +# CHECK-BE: fnmsubs. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3d] +# CHECK-LE: fnmsubs. 2, 3, 4, 5 # encoding: [0x3d,0x29,0x43,0xec] + fnmsubs. 2, 3, 4, 5 # Floating-point rounding and conversion instructions -# CHECK: frsp 2, 3 # encoding: [0xfc,0x40,0x18,0x18] - frsp 2, 3 -# CHECK: frsp. 2, 3 # encoding: [0xfc,0x40,0x18,0x19] - frsp. 2, 3 - -# CHECK: fctid 2, 3 # encoding: [0xfc,0x40,0x1e,0x5c] - fctid 2, 3 -# CHECK: fctid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5d] - fctid. 2, 3 -# CHECK: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e] - fctidz 2, 3 -# CHECK: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f] - fctidz. 2, 3 -# FIXME: fctidu 2, 3 -# FIXME: fctidu. 2, 3 -# CHECK: fctiduz 2, 3 # encoding: [0xfc,0x40,0x1f,0x5e] - fctiduz 2, 3 -# CHECK: fctiduz. 2, 3 # encoding: [0xfc,0x40,0x1f,0x5f] - fctiduz. 2, 3 -# CHECK: fctiw 2, 3 # encoding: [0xfc,0x40,0x18,0x1c] - fctiw 2, 3 -# CHECK: fctiw. 2, 3 # encoding: [0xfc,0x40,0x18,0x1d] - fctiw. 2, 3 -# CHECK: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e] - fctiwz 2, 3 -# CHECK: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f] - fctiwz. 2, 3 -# FIXME: fctiwu 2, 3 -# FIXME: fctiwu. 2, 3 -# CHECK: fctiwuz 2, 3 # encoding: [0xfc,0x40,0x19,0x1e] - fctiwuz 2, 3 -# CHECK: fctiwuz. 2, 3 # encoding: [0xfc,0x40,0x19,0x1f] - fctiwuz. 2, 3 -# CHECK: fcfid 2, 3 # encoding: [0xfc,0x40,0x1e,0x9c] - fcfid 2, 3 -# CHECK: fcfid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x9d] - fcfid. 2, 3 -# CHECK: fcfidu 2, 3 # encoding: [0xfc,0x40,0x1f,0x9c] - fcfidu 2, 3 -# CHECK: fcfidu. 2, 3 # encoding: [0xfc,0x40,0x1f,0x9d] - fcfidu. 2, 3 -# CHECK: fcfids 2, 3 # encoding: [0xec,0x40,0x1e,0x9c] - fcfids 2, 3 -# CHECK: fcfids. 2, 3 # encoding: [0xec,0x40,0x1e,0x9d] - fcfids. 2, 3 -# CHECK: fcfidus 2, 3 # encoding: [0xec,0x40,0x1f,0x9c] - fcfidus 2, 3 -# CHECK: fcfidus. 2, 3 # encoding: [0xec,0x40,0x1f,0x9d] - fcfidus. 2, 3 -# CHECK: frin 2, 3 # encoding: [0xfc,0x40,0x1b,0x10] - frin 2, 3 -# CHECK: frin. 2, 3 # encoding: [0xfc,0x40,0x1b,0x11] - frin. 2, 3 -# CHECK: frip 2, 3 # encoding: [0xfc,0x40,0x1b,0x90] - frip 2, 3 -# CHECK: frip. 2, 3 # encoding: [0xfc,0x40,0x1b,0x91] - frip. 2, 3 -# CHECK: friz 2, 3 # encoding: [0xfc,0x40,0x1b,0x50] - friz 2, 3 -# CHECK: friz. 2, 3 # encoding: [0xfc,0x40,0x1b,0x51] - friz. 2, 3 -# CHECK: frim 2, 3 # encoding: [0xfc,0x40,0x1b,0xd0] - frim 2, 3 -# CHECK: frim. 2, 3 # encoding: [0xfc,0x40,0x1b,0xd1] - frim. 2, 3 +# CHECK-BE: frsp 2, 3 # encoding: [0xfc,0x40,0x18,0x18] +# CHECK-LE: frsp 2, 3 # encoding: [0x18,0x18,0x40,0xfc] + frsp 2, 3 +# CHECK-BE: frsp. 2, 3 # encoding: [0xfc,0x40,0x18,0x19] +# CHECK-LE: frsp. 2, 3 # encoding: [0x19,0x18,0x40,0xfc] + frsp. 2, 3 + +# CHECK-BE: fctid 2, 3 # encoding: [0xfc,0x40,0x1e,0x5c] +# CHECK-LE: fctid 2, 3 # encoding: [0x5c,0x1e,0x40,0xfc] + fctid 2, 3 +# CHECK-BE: fctid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5d] +# CHECK-LE: fctid. 2, 3 # encoding: [0x5d,0x1e,0x40,0xfc] + fctid. 2, 3 +# CHECK-BE: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e] +# CHECK-LE: fctidz 2, 3 # encoding: [0x5e,0x1e,0x40,0xfc] + fctidz 2, 3 +# CHECK-BE: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f] +# CHECK-LE: fctidz. 2, 3 # encoding: [0x5f,0x1e,0x40,0xfc] + fctidz. 2, 3 +# FIXME: fctidu 2, 3 +# FIXME: fctidu. 2, 3 +# CHECK-BE: fctiduz 2, 3 # encoding: [0xfc,0x40,0x1f,0x5e] +# CHECK-LE: fctiduz 2, 3 # encoding: [0x5e,0x1f,0x40,0xfc] + fctiduz 2, 3 +# CHECK-BE: fctiduz. 2, 3 # encoding: [0xfc,0x40,0x1f,0x5f] +# CHECK-LE: fctiduz. 2, 3 # encoding: [0x5f,0x1f,0x40,0xfc] + fctiduz. 2, 3 +# CHECK-BE: fctiw 2, 3 # encoding: [0xfc,0x40,0x18,0x1c] +# CHECK-LE: fctiw 2, 3 # encoding: [0x1c,0x18,0x40,0xfc] + fctiw 2, 3 +# CHECK-BE: fctiw. 2, 3 # encoding: [0xfc,0x40,0x18,0x1d] +# CHECK-LE: fctiw. 2, 3 # encoding: [0x1d,0x18,0x40,0xfc] + fctiw. 2, 3 +# CHECK-BE: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e] +# CHECK-LE: fctiwz 2, 3 # encoding: [0x1e,0x18,0x40,0xfc] + fctiwz 2, 3 +# CHECK-BE: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f] +# CHECK-LE: fctiwz. 2, 3 # encoding: [0x1f,0x18,0x40,0xfc] + fctiwz. 2, 3 +# FIXME: fctiwu 2, 3 +# FIXME: fctiwu. 2, 3 +# CHECK-BE: fctiwuz 2, 3 # encoding: [0xfc,0x40,0x19,0x1e] +# CHECK-LE: fctiwuz 2, 3 # encoding: [0x1e,0x19,0x40,0xfc] + fctiwuz 2, 3 +# CHECK-BE: fctiwuz. 2, 3 # encoding: [0xfc,0x40,0x19,0x1f] +# CHECK-LE: fctiwuz. 2, 3 # encoding: [0x1f,0x19,0x40,0xfc] + fctiwuz. 2, 3 +# CHECK-BE: fcfid 2, 3 # encoding: [0xfc,0x40,0x1e,0x9c] +# CHECK-LE: fcfid 2, 3 # encoding: [0x9c,0x1e,0x40,0xfc] + fcfid 2, 3 +# CHECK-BE: fcfid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x9d] +# CHECK-LE: fcfid. 2, 3 # encoding: [0x9d,0x1e,0x40,0xfc] + fcfid. 2, 3 +# CHECK-BE: fcfidu 2, 3 # encoding: [0xfc,0x40,0x1f,0x9c] +# CHECK-LE: fcfidu 2, 3 # encoding: [0x9c,0x1f,0x40,0xfc] + fcfidu 2, 3 +# CHECK-BE: fcfidu. 2, 3 # encoding: [0xfc,0x40,0x1f,0x9d] +# CHECK-LE: fcfidu. 2, 3 # encoding: [0x9d,0x1f,0x40,0xfc] + fcfidu. 2, 3 +# CHECK-BE: fcfids 2, 3 # encoding: [0xec,0x40,0x1e,0x9c] +# CHECK-LE: fcfids 2, 3 # encoding: [0x9c,0x1e,0x40,0xec] + fcfids 2, 3 +# CHECK-BE: fcfids. 2, 3 # encoding: [0xec,0x40,0x1e,0x9d] +# CHECK-LE: fcfids. 2, 3 # encoding: [0x9d,0x1e,0x40,0xec] + fcfids. 2, 3 +# CHECK-BE: fcfidus 2, 3 # encoding: [0xec,0x40,0x1f,0x9c] +# CHECK-LE: fcfidus 2, 3 # encoding: [0x9c,0x1f,0x40,0xec] + fcfidus 2, 3 +# CHECK-BE: fcfidus. 2, 3 # encoding: [0xec,0x40,0x1f,0x9d] +# CHECK-LE: fcfidus. 2, 3 # encoding: [0x9d,0x1f,0x40,0xec] + fcfidus. 2, 3 +# CHECK-BE: frin 2, 3 # encoding: [0xfc,0x40,0x1b,0x10] +# CHECK-LE: frin 2, 3 # encoding: [0x10,0x1b,0x40,0xfc] + frin 2, 3 +# CHECK-BE: frin. 2, 3 # encoding: [0xfc,0x40,0x1b,0x11] +# CHECK-LE: frin. 2, 3 # encoding: [0x11,0x1b,0x40,0xfc] + frin. 2, 3 +# CHECK-BE: frip 2, 3 # encoding: [0xfc,0x40,0x1b,0x90] +# CHECK-LE: frip 2, 3 # encoding: [0x90,0x1b,0x40,0xfc] + frip 2, 3 +# CHECK-BE: frip. 2, 3 # encoding: [0xfc,0x40,0x1b,0x91] +# CHECK-LE: frip. 2, 3 # encoding: [0x91,0x1b,0x40,0xfc] + frip. 2, 3 +# CHECK-BE: friz 2, 3 # encoding: [0xfc,0x40,0x1b,0x50] +# CHECK-LE: friz 2, 3 # encoding: [0x50,0x1b,0x40,0xfc] + friz 2, 3 +# CHECK-BE: friz. 2, 3 # encoding: [0xfc,0x40,0x1b,0x51] +# CHECK-LE: friz. 2, 3 # encoding: [0x51,0x1b,0x40,0xfc] + friz. 2, 3 +# CHECK-BE: frim 2, 3 # encoding: [0xfc,0x40,0x1b,0xd0] +# CHECK-LE: frim 2, 3 # encoding: [0xd0,0x1b,0x40,0xfc] + frim 2, 3 +# CHECK-BE: frim. 2, 3 # encoding: [0xfc,0x40,0x1b,0xd1] +# CHECK-LE: frim. 2, 3 # encoding: [0xd1,0x1b,0x40,0xfc] + frim. 2, 3 # Floating-point compare instructions -# CHECK: fcmpu 2, 3, 4 # encoding: [0xfd,0x03,0x20,0x00] - fcmpu 2, 3, 4 -# FIXME: fcmpo 2, 3, 4 +# CHECK-BE: fcmpu 2, 3, 4 # encoding: [0xfd,0x03,0x20,0x00] +# CHECK-LE: fcmpu 2, 3, 4 # encoding: [0x00,0x20,0x03,0xfd] + fcmpu 2, 3, 4 +# FIXME: fcmpo 2, 3, 4 # Floating-point select instruction -# CHECK: fsel 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x2e] - fsel 2, 3, 4, 5 -# CHECK: fsel. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x2f] - fsel. 2, 3, 4, 5 +# CHECK-BE: fsel 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x2e] +# CHECK-LE: fsel 2, 3, 4, 5 # encoding: [0x2e,0x29,0x43,0xfc] + fsel 2, 3, 4, 5 +# CHECK-BE: fsel. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x2f] +# CHECK-LE: fsel. 2, 3, 4, 5 # encoding: [0x2f,0x29,0x43,0xfc] + fsel. 2, 3, 4, 5 # Floating-point status and control register instructions -# CHECK: mffs 2 # encoding: [0xfc,0x40,0x04,0x8e] - mffs 2 -# FIXME: mffs. 2 - -# FIXME: mcrfs 2, 3 - -# FIXME: mtfsfi 2, 3, 1 -# FIXME: mtfsfi. 2, 3, 1 -# FIXME: mtfsf 2, 3, 1, 1 -# FIXME: mtfsf. 2, 3, 1, 1 - -# CHECK: mtfsb0 31 # encoding: [0xff,0xe0,0x00,0x8c] - mtfsb0 31 -# FIXME: mtfsb0. 31 -# CHECK: mtfsb1 31 # encoding: [0xff,0xe0,0x00,0x4c] - mtfsb1 31 -# FIXME: mtfsb1. 31 +# CHECK-BE: mffs 2 # encoding: [0xfc,0x40,0x04,0x8e] +# CHECK-LE: mffs 2 # encoding: [0x8e,0x04,0x40,0xfc] + mffs 2 +# FIXME: mffs. 2 + +# FIXME: mcrfs 2, 3 + +# FIXME: mtfsfi 2, 3, 1 +# FIXME: mtfsfi. 2, 3, 1 +# FIXME: mtfsf 2, 3, 1, 1 +# FIXME: mtfsf. 2, 3, 1, 1 + +# CHECK-BE: mtfsb0 31 # encoding: [0xff,0xe0,0x00,0x8c] +# CHECK-LE: mtfsb0 31 # encoding: [0x8c,0x00,0xe0,0xff] + mtfsb0 31 +# FIXME: mtfsb0. 31 +# CHECK-BE: mtfsb1 31 # encoding: [0xff,0xe0,0x00,0x4c] +# CHECK-LE: mtfsb1 31 # encoding: [0x4c,0x00,0xe0,0xff] + mtfsb1 31 +# FIXME: mtfsb1. 31 Index: llvm-suse/test/MC/PowerPC/ppc64-encoding-vmx.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-encoding-vmx.s +++ llvm-suse/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -1,384 +1,554 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Vector facility # Vector storage access instructions -# CHECK: lvebx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0e] - lvebx 2, 3, 4 -# CHECK: lvehx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4e] - lvehx 2, 3, 4 -# CHECK: lvewx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x8e] - lvewx 2, 3, 4 -# CHECK: lvx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xce] - lvx 2, 3, 4 -# CHECK: lvxl 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xce] - lvxl 2, 3, 4 -# CHECK: stvebx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x0e] - stvebx 2, 3, 4 -# CHECK: stvehx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x4e] - stvehx 2, 3, 4 -# CHECK: stvewx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x8e] - stvewx 2, 3, 4 -# CHECK: stvx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xce] - stvx 2, 3, 4 -# CHECK: stvxl 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xce] - stvxl 2, 3, 4 -# CHECK: lvsl 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0c] - lvsl 2, 3, 4 -# CHECK: lvsr 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4c] - lvsr 2, 3, 4 +# CHECK-BE: lvebx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0e] +# CHECK-LE: lvebx 2, 3, 4 # encoding: [0x0e,0x20,0x43,0x7c] + lvebx 2, 3, 4 +# CHECK-BE: lvehx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4e] +# CHECK-LE: lvehx 2, 3, 4 # encoding: [0x4e,0x20,0x43,0x7c] + lvehx 2, 3, 4 +# CHECK-BE: lvewx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x8e] +# CHECK-LE: lvewx 2, 3, 4 # encoding: [0x8e,0x20,0x43,0x7c] + lvewx 2, 3, 4 +# CHECK-BE: lvx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xce] +# CHECK-LE: lvx 2, 3, 4 # encoding: [0xce,0x20,0x43,0x7c] + lvx 2, 3, 4 +# CHECK-BE: lvxl 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xce] +# CHECK-LE: lvxl 2, 3, 4 # encoding: [0xce,0x22,0x43,0x7c] + lvxl 2, 3, 4 +# CHECK-BE: stvebx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x0e] +# CHECK-LE: stvebx 2, 3, 4 # encoding: [0x0e,0x21,0x43,0x7c] + stvebx 2, 3, 4 +# CHECK-BE: stvehx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x4e] +# CHECK-LE: stvehx 2, 3, 4 # encoding: [0x4e,0x21,0x43,0x7c] + stvehx 2, 3, 4 +# CHECK-BE: stvewx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x8e] +# CHECK-LE: stvewx 2, 3, 4 # encoding: [0x8e,0x21,0x43,0x7c] + stvewx 2, 3, 4 +# CHECK-BE: stvx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xce] +# CHECK-LE: stvx 2, 3, 4 # encoding: [0xce,0x21,0x43,0x7c] + stvx 2, 3, 4 +# CHECK-BE: stvxl 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xce] +# CHECK-LE: stvxl 2, 3, 4 # encoding: [0xce,0x23,0x43,0x7c] + stvxl 2, 3, 4 +# CHECK-BE: lvsl 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0c] +# CHECK-LE: lvsl 2, 3, 4 # encoding: [0x0c,0x20,0x43,0x7c] + lvsl 2, 3, 4 +# CHECK-BE: lvsr 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4c] +# CHECK-LE: lvsr 2, 3, 4 # encoding: [0x4c,0x20,0x43,0x7c] + lvsr 2, 3, 4 # Vector permute and formatting instructions -# CHECK: vpkpx 2, 3, 4 # encoding: [0x10,0x43,0x23,0x0e] - vpkpx 2, 3, 4 -# CHECK: vpkshss 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8e] - vpkshss 2, 3, 4 -# CHECK: vpkshus 2, 3, 4 # encoding: [0x10,0x43,0x21,0x0e] - vpkshus 2, 3, 4 -# CHECK: vpkswss 2, 3, 4 # encoding: [0x10,0x43,0x21,0xce] - vpkswss 2, 3, 4 -# CHECK: vpkswus 2, 3, 4 # encoding: [0x10,0x43,0x21,0x4e] - vpkswus 2, 3, 4 -# CHECK: vpkuhum 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0e] - vpkuhum 2, 3, 4 -# CHECK: vpkuhus 2, 3, 4 # encoding: [0x10,0x43,0x20,0x8e] - vpkuhus 2, 3, 4 -# CHECK: vpkuwum 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4e] - vpkuwum 2, 3, 4 -# CHECK: vpkuwus 2, 3, 4 # encoding: [0x10,0x43,0x20,0xce] - vpkuwus 2, 3, 4 - -# CHECK: vupkhpx 2, 3 # encoding: [0x10,0x40,0x1b,0x4e] - vupkhpx 2, 3 -# CHECK: vupkhsb 2, 3 # encoding: [0x10,0x40,0x1a,0x0e] - vupkhsb 2, 3 -# CHECK: vupkhsh 2, 3 # encoding: [0x10,0x40,0x1a,0x4e] - vupkhsh 2, 3 -# CHECK: vupklpx 2, 3 # encoding: [0x10,0x40,0x1b,0xce] - vupklpx 2, 3 -# CHECK: vupklsb 2, 3 # encoding: [0x10,0x40,0x1a,0x8e] - vupklsb 2, 3 -# CHECK: vupklsh 2, 3 # encoding: [0x10,0x40,0x1a,0xce] - vupklsh 2, 3 - -# CHECK: vmrghb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0c] - vmrghb 2, 3, 4 -# CHECK: vmrghh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4c] - vmrghh 2, 3, 4 -# CHECK: vmrghw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x8c] - vmrghw 2, 3, 4 -# CHECK: vmrglb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x0c] - vmrglb 2, 3, 4 -# CHECK: vmrglh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x4c] - vmrglh 2, 3, 4 -# CHECK: vmrglw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8c] - vmrglw 2, 3, 4 - -# CHECK: vspltb 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x0c] - vspltb 2, 3, 1 -# CHECK: vsplth 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x4c] - vsplth 2, 3, 1 -# CHECK: vspltw 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x8c] - vspltw 2, 3, 1 -# CHECK: vspltisb 2, 3 # encoding: [0x10,0x43,0x03,0x0c] - vspltisb 2, 3 -# CHECK: vspltish 2, 3 # encoding: [0x10,0x43,0x03,0x4c] - vspltish 2, 3 -# CHECK: vspltisw 2, 3 # encoding: [0x10,0x43,0x03,0x8c] - vspltisw 2, 3 - -# CHECK: vperm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6b] - vperm 2, 3, 4, 5 -# CHECK: vsel 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6a] - vsel 2, 3, 4, 5 - -# CHECK: vsl 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc4] - vsl 2, 3, 4 -# CHECK: vsldoi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6c] - vsldoi 2, 3, 4, 5 -# CHECK: vslo 2, 3, 4 # encoding: [0x10,0x43,0x24,0x0c] - vslo 2, 3, 4 -# CHECK: vsr 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc4] - vsr 2, 3, 4 -# CHECK: vsro 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4c] - vsro 2, 3, 4 +# CHECK-BE: vpkpx 2, 3, 4 # encoding: [0x10,0x43,0x23,0x0e] +# CHECK-LE: vpkpx 2, 3, 4 # encoding: [0x0e,0x23,0x43,0x10] + vpkpx 2, 3, 4 +# CHECK-BE: vpkshss 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8e] +# CHECK-LE: vpkshss 2, 3, 4 # encoding: [0x8e,0x21,0x43,0x10] + vpkshss 2, 3, 4 +# CHECK-BE: vpkshus 2, 3, 4 # encoding: [0x10,0x43,0x21,0x0e] +# CHECK-LE: vpkshus 2, 3, 4 # encoding: [0x0e,0x21,0x43,0x10] + vpkshus 2, 3, 4 +# CHECK-BE: vpkswss 2, 3, 4 # encoding: [0x10,0x43,0x21,0xce] +# CHECK-LE: vpkswss 2, 3, 4 # encoding: [0xce,0x21,0x43,0x10] + vpkswss 2, 3, 4 +# CHECK-BE: vpkswus 2, 3, 4 # encoding: [0x10,0x43,0x21,0x4e] +# CHECK-LE: vpkswus 2, 3, 4 # encoding: [0x4e,0x21,0x43,0x10] + vpkswus 2, 3, 4 +# CHECK-BE: vpkuhum 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0e] +# CHECK-LE: vpkuhum 2, 3, 4 # encoding: [0x0e,0x20,0x43,0x10] + vpkuhum 2, 3, 4 +# CHECK-BE: vpkuhus 2, 3, 4 # encoding: [0x10,0x43,0x20,0x8e] +# CHECK-LE: vpkuhus 2, 3, 4 # encoding: [0x8e,0x20,0x43,0x10] + vpkuhus 2, 3, 4 +# CHECK-BE: vpkuwum 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4e] +# CHECK-LE: vpkuwum 2, 3, 4 # encoding: [0x4e,0x20,0x43,0x10] + vpkuwum 2, 3, 4 +# CHECK-BE: vpkuwus 2, 3, 4 # encoding: [0x10,0x43,0x20,0xce] +# CHECK-LE: vpkuwus 2, 3, 4 # encoding: [0xce,0x20,0x43,0x10] + vpkuwus 2, 3, 4 + +# CHECK-BE: vupkhpx 2, 3 # encoding: [0x10,0x40,0x1b,0x4e] +# CHECK-LE: vupkhpx 2, 3 # encoding: [0x4e,0x1b,0x40,0x10] + vupkhpx 2, 3 +# CHECK-BE: vupkhsb 2, 3 # encoding: [0x10,0x40,0x1a,0x0e] +# CHECK-LE: vupkhsb 2, 3 # encoding: [0x0e,0x1a,0x40,0x10] + vupkhsb 2, 3 +# CHECK-BE: vupkhsh 2, 3 # encoding: [0x10,0x40,0x1a,0x4e] +# CHECK-LE: vupkhsh 2, 3 # encoding: [0x4e,0x1a,0x40,0x10] + vupkhsh 2, 3 +# CHECK-BE: vupklpx 2, 3 # encoding: [0x10,0x40,0x1b,0xce] +# CHECK-LE: vupklpx 2, 3 # encoding: [0xce,0x1b,0x40,0x10] + vupklpx 2, 3 +# CHECK-BE: vupklsb 2, 3 # encoding: [0x10,0x40,0x1a,0x8e] +# CHECK-LE: vupklsb 2, 3 # encoding: [0x8e,0x1a,0x40,0x10] + vupklsb 2, 3 +# CHECK-BE: vupklsh 2, 3 # encoding: [0x10,0x40,0x1a,0xce] +# CHECK-LE: vupklsh 2, 3 # encoding: [0xce,0x1a,0x40,0x10] + vupklsh 2, 3 + +# CHECK-BE: vmrghb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0c] +# CHECK-LE: vmrghb 2, 3, 4 # encoding: [0x0c,0x20,0x43,0x10] + vmrghb 2, 3, 4 +# CHECK-BE: vmrghh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4c] +# CHECK-LE: vmrghh 2, 3, 4 # encoding: [0x4c,0x20,0x43,0x10] + vmrghh 2, 3, 4 +# CHECK-BE: vmrghw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x8c] +# CHECK-LE: vmrghw 2, 3, 4 # encoding: [0x8c,0x20,0x43,0x10] + vmrghw 2, 3, 4 +# CHECK-BE: vmrglb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x0c] +# CHECK-LE: vmrglb 2, 3, 4 # encoding: [0x0c,0x21,0x43,0x10] + vmrglb 2, 3, 4 +# CHECK-BE: vmrglh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x4c] +# CHECK-LE: vmrglh 2, 3, 4 # encoding: [0x4c,0x21,0x43,0x10] + vmrglh 2, 3, 4 +# CHECK-BE: vmrglw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8c] +# CHECK-LE: vmrglw 2, 3, 4 # encoding: [0x8c,0x21,0x43,0x10] + vmrglw 2, 3, 4 + +# CHECK-BE: vspltb 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x0c] +# CHECK-LE: vspltb 2, 3, 1 # encoding: [0x0c,0x1a,0x41,0x10] + vspltb 2, 3, 1 +# CHECK-BE: vsplth 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x4c] +# CHECK-LE: vsplth 2, 3, 1 # encoding: [0x4c,0x1a,0x41,0x10] + vsplth 2, 3, 1 +# CHECK-BE: vspltw 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x8c] +# CHECK-LE: vspltw 2, 3, 1 # encoding: [0x8c,0x1a,0x41,0x10] + vspltw 2, 3, 1 +# CHECK-BE: vspltisb 2, 3 # encoding: [0x10,0x43,0x03,0x0c] +# CHECK-LE: vspltisb 2, 3 # encoding: [0x0c,0x03,0x43,0x10] + vspltisb 2, 3 +# CHECK-BE: vspltish 2, 3 # encoding: [0x10,0x43,0x03,0x4c] +# CHECK-LE: vspltish 2, 3 # encoding: [0x4c,0x03,0x43,0x10] + vspltish 2, 3 +# CHECK-BE: vspltisw 2, 3 # encoding: [0x10,0x43,0x03,0x8c] +# CHECK-LE: vspltisw 2, 3 # encoding: [0x8c,0x03,0x43,0x10] + vspltisw 2, 3 + +# CHECK-BE: vperm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6b] +# CHECK-LE: vperm 2, 3, 4, 5 # encoding: [0x6b,0x21,0x43,0x10] + vperm 2, 3, 4, 5 +# CHECK-BE: vsel 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6a] +# CHECK-LE: vsel 2, 3, 4, 5 # encoding: [0x6a,0x21,0x43,0x10] + vsel 2, 3, 4, 5 + +# CHECK-BE: vsl 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc4] +# CHECK-LE: vsl 2, 3, 4 # encoding: [0xc4,0x21,0x43,0x10] + vsl 2, 3, 4 +# CHECK-BE: vsldoi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6c] +# CHECK-LE: vsldoi 2, 3, 4, 5 # encoding: [0x6c,0x21,0x43,0x10] + vsldoi 2, 3, 4, 5 +# CHECK-BE: vslo 2, 3, 4 # encoding: [0x10,0x43,0x24,0x0c] +# CHECK-LE: vslo 2, 3, 4 # encoding: [0x0c,0x24,0x43,0x10] + vslo 2, 3, 4 +# CHECK-BE: vsr 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc4] +# CHECK-LE: vsr 2, 3, 4 # encoding: [0xc4,0x22,0x43,0x10] + vsr 2, 3, 4 +# CHECK-BE: vsro 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4c] +# CHECK-LE: vsro 2, 3, 4 # encoding: [0x4c,0x24,0x43,0x10] + vsro 2, 3, 4 # Vector integer arithmetic instructions -# CHECK: vaddcuw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x80] - vaddcuw 2, 3, 4 -# CHECK: vaddsbs 2, 3, 4 # encoding: [0x10,0x43,0x23,0x00] - vaddsbs 2, 3, 4 -# CHECK: vaddshs 2, 3, 4 # encoding: [0x10,0x43,0x23,0x40] - vaddshs 2, 3, 4 -# CHECK: vaddsws 2, 3, 4 # encoding: [0x10,0x43,0x23,0x80] - vaddsws 2, 3, 4 -# CHECK: vaddubm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x00] - vaddubm 2, 3, 4 -# CHECK: vadduhm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x40] - vadduhm 2, 3, 4 -# CHECK: vadduwm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x80] - vadduwm 2, 3, 4 -# CHECK: vaddubs 2, 3, 4 # encoding: [0x10,0x43,0x22,0x00] - vaddubs 2, 3, 4 -# CHECK: vadduhs 2, 3, 4 # encoding: [0x10,0x43,0x22,0x40] - vadduhs 2, 3, 4 -# CHECK: vadduws 2, 3, 4 # encoding: [0x10,0x43,0x22,0x80] - vadduws 2, 3, 4 - -# CHECK: vsubcuw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x80] - vsubcuw 2, 3, 4 -# CHECK: vsubsbs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x00] - vsubsbs 2, 3, 4 -# CHECK: vsubshs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x40] - vsubshs 2, 3, 4 -# CHECK: vsubsws 2, 3, 4 # encoding: [0x10,0x43,0x27,0x80] - vsubsws 2, 3, 4 -# CHECK: vsububm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x00] - vsububm 2, 3, 4 -# CHECK: vsubuhm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x40] - vsubuhm 2, 3, 4 -# CHECK: vsubuwm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x80] - vsubuwm 2, 3, 4 -# CHECK: vsububs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x00] - vsububs 2, 3, 4 -# CHECK: vsubuhs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x40] - vsubuhs 2, 3, 4 -# CHECK: vsubuws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x80] - vsubuws 2, 3, 4 - -# CHECK: vmulesb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x08] - vmulesb 2, 3, 4 -# CHECK: vmulesh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x48] - vmulesh 2, 3, 4 -# CHECK: vmuleub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x08] - vmuleub 2, 3, 4 -# CHECK: vmuleuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x48] - vmuleuh 2, 3, 4 -# CHECK: vmulosb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x08] - vmulosb 2, 3, 4 -# CHECK: vmulosh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x48] - vmulosh 2, 3, 4 -# CHECK: vmuloub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x08] - vmuloub 2, 3, 4 -# CHECK: vmulouh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x48] - vmulouh 2, 3, 4 - -# CHECK: vmhaddshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x60] - vmhaddshs 2, 3, 4, 5 -# CHECK: vmhraddshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x61] - vmhraddshs 2, 3, 4, 5 -# CHECK: vmladduhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x62] - vmladduhm 2, 3, 4, 5 -# CHECK: vmsumubm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x64] - vmsumubm 2, 3, 4, 5 -# CHECK: vmsummbm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x65] - vmsummbm 2, 3, 4, 5 -# CHECK: vmsumshm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x68] - vmsumshm 2, 3, 4, 5 -# CHECK: vmsumshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x69] - vmsumshs 2, 3, 4, 5 -# CHECK: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66] - vmsumuhm 2, 3, 4, 5 -# CHECK: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67] - vmsumuhs 2, 3, 4, 5 - -# CHECK: vsumsws 2, 3, 4 # encoding: [0x10,0x43,0x27,0x88] - vsumsws 2, 3, 4 -# CHECK: vsum2sws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x88] - vsum2sws 2, 3, 4 -# CHECK: vsum4sbs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x08] - vsum4sbs 2, 3, 4 -# CHECK: vsum4shs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x48] - vsum4shs 2, 3, 4 -# CHECK: vsum4ubs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x08] - vsum4ubs 2, 3, 4 - -# CHECK: vavgsb 2, 3, 4 # encoding: [0x10,0x43,0x25,0x02] - vavgsb 2, 3, 4 -# CHECK: vavgsh 2, 3, 4 # encoding: [0x10,0x43,0x25,0x42] - vavgsh 2, 3, 4 -# CHECK: vavgsw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x82] - vavgsw 2, 3, 4 -# CHECK: vavgub 2, 3, 4 # encoding: [0x10,0x43,0x24,0x02] - vavgub 2, 3, 4 -# CHECK: vavguh 2, 3, 4 # encoding: [0x10,0x43,0x24,0x42] - vavguh 2, 3, 4 -# CHECK: vavguw 2, 3, 4 # encoding: [0x10,0x43,0x24,0x82] - vavguw 2, 3, 4 - -# CHECK: vmaxsb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x02] - vmaxsb 2, 3, 4 -# CHECK: vmaxsh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x42] - vmaxsh 2, 3, 4 -# CHECK: vmaxsw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x82] - vmaxsw 2, 3, 4 -# CHECK: vmaxub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x02] - vmaxub 2, 3, 4 -# CHECK: vmaxuh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x42] - vmaxuh 2, 3, 4 -# CHECK: vmaxuw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x82] - vmaxuw 2, 3, 4 - -# CHECK: vminsb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x02] - vminsb 2, 3, 4 -# CHECK: vminsh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x42] - vminsh 2, 3, 4 -# CHECK: vminsw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x82] - vminsw 2, 3, 4 -# CHECK: vminub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x02] - vminub 2, 3, 4 -# CHECK: vminuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x42] - vminuh 2, 3, 4 -# CHECK: vminuw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x82] - vminuw 2, 3, 4 +# CHECK-BE: vaddcuw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x80] +# CHECK-LE: vaddcuw 2, 3, 4 # encoding: [0x80,0x21,0x43,0x10] + vaddcuw 2, 3, 4 +# CHECK-BE: vaddsbs 2, 3, 4 # encoding: [0x10,0x43,0x23,0x00] +# CHECK-LE: vaddsbs 2, 3, 4 # encoding: [0x00,0x23,0x43,0x10] + vaddsbs 2, 3, 4 +# CHECK-BE: vaddshs 2, 3, 4 # encoding: [0x10,0x43,0x23,0x40] +# CHECK-LE: vaddshs 2, 3, 4 # encoding: [0x40,0x23,0x43,0x10] + vaddshs 2, 3, 4 +# CHECK-BE: vaddsws 2, 3, 4 # encoding: [0x10,0x43,0x23,0x80] +# CHECK-LE: vaddsws 2, 3, 4 # encoding: [0x80,0x23,0x43,0x10] + vaddsws 2, 3, 4 +# CHECK-BE: vaddubm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x00] +# CHECK-LE: vaddubm 2, 3, 4 # encoding: [0x00,0x20,0x43,0x10] + vaddubm 2, 3, 4 +# CHECK-BE: vadduhm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x40] +# CHECK-LE: vadduhm 2, 3, 4 # encoding: [0x40,0x20,0x43,0x10] + vadduhm 2, 3, 4 +# CHECK-BE: vadduwm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x80] +# CHECK-LE: vadduwm 2, 3, 4 # encoding: [0x80,0x20,0x43,0x10] + vadduwm 2, 3, 4 +# CHECK-BE: vaddubs 2, 3, 4 # encoding: [0x10,0x43,0x22,0x00] +# CHECK-LE: vaddubs 2, 3, 4 # encoding: [0x00,0x22,0x43,0x10] + vaddubs 2, 3, 4 +# CHECK-BE: vadduhs 2, 3, 4 # encoding: [0x10,0x43,0x22,0x40] +# CHECK-LE: vadduhs 2, 3, 4 # encoding: [0x40,0x22,0x43,0x10] + vadduhs 2, 3, 4 +# CHECK-BE: vadduws 2, 3, 4 # encoding: [0x10,0x43,0x22,0x80] +# CHECK-LE: vadduws 2, 3, 4 # encoding: [0x80,0x22,0x43,0x10] + vadduws 2, 3, 4 + +# CHECK-BE: vsubcuw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x80] +# CHECK-LE: vsubcuw 2, 3, 4 # encoding: [0x80,0x25,0x43,0x10] + vsubcuw 2, 3, 4 +# CHECK-BE: vsubsbs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x00] +# CHECK-LE: vsubsbs 2, 3, 4 # encoding: [0x00,0x27,0x43,0x10] + vsubsbs 2, 3, 4 +# CHECK-BE: vsubshs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x40] +# CHECK-LE: vsubshs 2, 3, 4 # encoding: [0x40,0x27,0x43,0x10] + vsubshs 2, 3, 4 +# CHECK-BE: vsubsws 2, 3, 4 # encoding: [0x10,0x43,0x27,0x80] +# CHECK-LE: vsubsws 2, 3, 4 # encoding: [0x80,0x27,0x43,0x10] + vsubsws 2, 3, 4 +# CHECK-BE: vsububm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x00] +# CHECK-LE: vsububm 2, 3, 4 # encoding: [0x00,0x24,0x43,0x10] + vsububm 2, 3, 4 +# CHECK-BE: vsubuhm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x40] +# CHECK-LE: vsubuhm 2, 3, 4 # encoding: [0x40,0x24,0x43,0x10] + vsubuhm 2, 3, 4 +# CHECK-BE: vsubuwm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x80] +# CHECK-LE: vsubuwm 2, 3, 4 # encoding: [0x80,0x24,0x43,0x10] + vsubuwm 2, 3, 4 +# CHECK-BE: vsububs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x00] +# CHECK-LE: vsububs 2, 3, 4 # encoding: [0x00,0x26,0x43,0x10] + vsububs 2, 3, 4 +# CHECK-BE: vsubuhs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x40] +# CHECK-LE: vsubuhs 2, 3, 4 # encoding: [0x40,0x26,0x43,0x10] + vsubuhs 2, 3, 4 +# CHECK-BE: vsubuws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x80] +# CHECK-LE: vsubuws 2, 3, 4 # encoding: [0x80,0x26,0x43,0x10] + vsubuws 2, 3, 4 + +# CHECK-BE: vmulesb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x08] +# CHECK-LE: vmulesb 2, 3, 4 # encoding: [0x08,0x23,0x43,0x10] + vmulesb 2, 3, 4 +# CHECK-BE: vmulesh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x48] +# CHECK-LE: vmulesh 2, 3, 4 # encoding: [0x48,0x23,0x43,0x10] + vmulesh 2, 3, 4 +# CHECK-BE: vmuleub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x08] +# CHECK-LE: vmuleub 2, 3, 4 # encoding: [0x08,0x22,0x43,0x10] + vmuleub 2, 3, 4 +# CHECK-BE: vmuleuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x48] +# CHECK-LE: vmuleuh 2, 3, 4 # encoding: [0x48,0x22,0x43,0x10] + vmuleuh 2, 3, 4 +# CHECK-BE: vmulosb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x08] +# CHECK-LE: vmulosb 2, 3, 4 # encoding: [0x08,0x21,0x43,0x10] + vmulosb 2, 3, 4 +# CHECK-BE: vmulosh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x48] +# CHECK-LE: vmulosh 2, 3, 4 # encoding: [0x48,0x21,0x43,0x10] + vmulosh 2, 3, 4 +# CHECK-BE: vmuloub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x08] +# CHECK-LE: vmuloub 2, 3, 4 # encoding: [0x08,0x20,0x43,0x10] + vmuloub 2, 3, 4 +# CHECK-BE: vmulouh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x48] +# CHECK-LE: vmulouh 2, 3, 4 # encoding: [0x48,0x20,0x43,0x10] + vmulouh 2, 3, 4 + +# CHECK-BE: vmhaddshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x60] +# CHECK-LE: vmhaddshs 2, 3, 4, 5 # encoding: [0x60,0x21,0x43,0x10] + vmhaddshs 2, 3, 4, 5 +# CHECK-BE: vmhraddshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x61] +# CHECK-LE: vmhraddshs 2, 3, 4, 5 # encoding: [0x61,0x21,0x43,0x10] + vmhraddshs 2, 3, 4, 5 +# CHECK-BE: vmladduhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x62] +# CHECK-LE: vmladduhm 2, 3, 4, 5 # encoding: [0x62,0x21,0x43,0x10] + vmladduhm 2, 3, 4, 5 +# CHECK-BE: vmsumubm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x64] +# CHECK-LE: vmsumubm 2, 3, 4, 5 # encoding: [0x64,0x21,0x43,0x10] + vmsumubm 2, 3, 4, 5 +# CHECK-BE: vmsummbm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x65] +# CHECK-LE: vmsummbm 2, 3, 4, 5 # encoding: [0x65,0x21,0x43,0x10] + vmsummbm 2, 3, 4, 5 +# CHECK-BE: vmsumshm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x68] +# CHECK-LE: vmsumshm 2, 3, 4, 5 # encoding: [0x68,0x21,0x43,0x10] + vmsumshm 2, 3, 4, 5 +# CHECK-BE: vmsumshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x69] +# CHECK-LE: vmsumshs 2, 3, 4, 5 # encoding: [0x69,0x21,0x43,0x10] + vmsumshs 2, 3, 4, 5 +# CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66] +# CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10] + vmsumuhm 2, 3, 4, 5 +# CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67] +# CHECK-LE: vmsumuhs 2, 3, 4, 5 # encoding: [0x67,0x21,0x43,0x10] + vmsumuhs 2, 3, 4, 5 + +# CHECK-BE: vsumsws 2, 3, 4 # encoding: [0x10,0x43,0x27,0x88] +# CHECK-LE: vsumsws 2, 3, 4 # encoding: [0x88,0x27,0x43,0x10] + vsumsws 2, 3, 4 +# CHECK-BE: vsum2sws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x88] +# CHECK-LE: vsum2sws 2, 3, 4 # encoding: [0x88,0x26,0x43,0x10] + vsum2sws 2, 3, 4 +# CHECK-BE: vsum4sbs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x08] +# CHECK-LE: vsum4sbs 2, 3, 4 # encoding: [0x08,0x27,0x43,0x10] + vsum4sbs 2, 3, 4 +# CHECK-BE: vsum4shs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x48] +# CHECK-LE: vsum4shs 2, 3, 4 # encoding: [0x48,0x26,0x43,0x10] + vsum4shs 2, 3, 4 +# CHECK-BE: vsum4ubs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x08] +# CHECK-LE: vsum4ubs 2, 3, 4 # encoding: [0x08,0x26,0x43,0x10] + vsum4ubs 2, 3, 4 + +# CHECK-BE: vavgsb 2, 3, 4 # encoding: [0x10,0x43,0x25,0x02] +# CHECK-LE: vavgsb 2, 3, 4 # encoding: [0x02,0x25,0x43,0x10] + vavgsb 2, 3, 4 +# CHECK-BE: vavgsh 2, 3, 4 # encoding: [0x10,0x43,0x25,0x42] +# CHECK-LE: vavgsh 2, 3, 4 # encoding: [0x42,0x25,0x43,0x10] + vavgsh 2, 3, 4 +# CHECK-BE: vavgsw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x82] +# CHECK-LE: vavgsw 2, 3, 4 # encoding: [0x82,0x25,0x43,0x10] + vavgsw 2, 3, 4 +# CHECK-BE: vavgub 2, 3, 4 # encoding: [0x10,0x43,0x24,0x02] +# CHECK-LE: vavgub 2, 3, 4 # encoding: [0x02,0x24,0x43,0x10] + vavgub 2, 3, 4 +# CHECK-BE: vavguh 2, 3, 4 # encoding: [0x10,0x43,0x24,0x42] +# CHECK-LE: vavguh 2, 3, 4 # encoding: [0x42,0x24,0x43,0x10] + vavguh 2, 3, 4 +# CHECK-BE: vavguw 2, 3, 4 # encoding: [0x10,0x43,0x24,0x82] +# CHECK-LE: vavguw 2, 3, 4 # encoding: [0x82,0x24,0x43,0x10] + vavguw 2, 3, 4 + +# CHECK-BE: vmaxsb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x02] +# CHECK-LE: vmaxsb 2, 3, 4 # encoding: [0x02,0x21,0x43,0x10] + vmaxsb 2, 3, 4 +# CHECK-BE: vmaxsh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x42] +# CHECK-LE: vmaxsh 2, 3, 4 # encoding: [0x42,0x21,0x43,0x10] + vmaxsh 2, 3, 4 +# CHECK-BE: vmaxsw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x82] +# CHECK-LE: vmaxsw 2, 3, 4 # encoding: [0x82,0x21,0x43,0x10] + vmaxsw 2, 3, 4 +# CHECK-BE: vmaxub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x02] +# CHECK-LE: vmaxub 2, 3, 4 # encoding: [0x02,0x20,0x43,0x10] + vmaxub 2, 3, 4 +# CHECK-BE: vmaxuh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x42] +# CHECK-LE: vmaxuh 2, 3, 4 # encoding: [0x42,0x20,0x43,0x10] + vmaxuh 2, 3, 4 +# CHECK-BE: vmaxuw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x82] +# CHECK-LE: vmaxuw 2, 3, 4 # encoding: [0x82,0x20,0x43,0x10] + vmaxuw 2, 3, 4 + +# CHECK-BE: vminsb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x02] +# CHECK-LE: vminsb 2, 3, 4 # encoding: [0x02,0x23,0x43,0x10] + vminsb 2, 3, 4 +# CHECK-BE: vminsh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x42] +# CHECK-LE: vminsh 2, 3, 4 # encoding: [0x42,0x23,0x43,0x10] + vminsh 2, 3, 4 +# CHECK-BE: vminsw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x82] +# CHECK-LE: vminsw 2, 3, 4 # encoding: [0x82,0x23,0x43,0x10] + vminsw 2, 3, 4 +# CHECK-BE: vminub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x02] +# CHECK-LE: vminub 2, 3, 4 # encoding: [0x02,0x22,0x43,0x10] + vminub 2, 3, 4 +# CHECK-BE: vminuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x42] +# CHECK-LE: vminuh 2, 3, 4 # encoding: [0x42,0x22,0x43,0x10] + vminuh 2, 3, 4 +# CHECK-BE: vminuw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x82] +# CHECK-LE: vminuw 2, 3, 4 # encoding: [0x82,0x22,0x43,0x10] + vminuw 2, 3, 4 # Vector integer compare instructions -# CHECK: vcmpequb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x06] - vcmpequb 2, 3, 4 -# CHECK: vcmpequb. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x06] - vcmpequb. 2, 3, 4 -# CHECK: vcmpequh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x46] - vcmpequh 2, 3, 4 -# CHECK: vcmpequh. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x46] - vcmpequh. 2, 3, 4 -# CHECK: vcmpequw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x86] - vcmpequw 2, 3, 4 -# CHECK: vcmpequw. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x86] - vcmpequw. 2, 3, 4 -# CHECK: vcmpgtsb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x06] - vcmpgtsb 2, 3, 4 -# CHECK: vcmpgtsb. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x06] - vcmpgtsb. 2, 3, 4 -# CHECK: vcmpgtsh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x46] - vcmpgtsh 2, 3, 4 -# CHECK: vcmpgtsh. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x46] - vcmpgtsh. 2, 3, 4 -# CHECK: vcmpgtsw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x86] - vcmpgtsw 2, 3, 4 -# CHECK: vcmpgtsw. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x86] - vcmpgtsw. 2, 3, 4 -# CHECK: vcmpgtub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x06] - vcmpgtub 2, 3, 4 -# CHECK: vcmpgtub. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x06] - vcmpgtub. 2, 3, 4 -# CHECK: vcmpgtuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x46] - vcmpgtuh 2, 3, 4 -# CHECK: vcmpgtuh. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x46] - vcmpgtuh. 2, 3, 4 -# CHECK: vcmpgtuw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x86] - vcmpgtuw 2, 3, 4 -# CHECK: vcmpgtuw. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x86] - vcmpgtuw. 2, 3, 4 +# CHECK-BE: vcmpequb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x06] +# CHECK-LE: vcmpequb 2, 3, 4 # encoding: [0x06,0x20,0x43,0x10] + vcmpequb 2, 3, 4 +# CHECK-BE: vcmpequb. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x06] +# CHECK-LE: vcmpequb. 2, 3, 4 # encoding: [0x06,0x24,0x43,0x10] + vcmpequb. 2, 3, 4 +# CHECK-BE: vcmpequh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x46] +# CHECK-LE: vcmpequh 2, 3, 4 # encoding: [0x46,0x20,0x43,0x10] + vcmpequh 2, 3, 4 +# CHECK-BE: vcmpequh. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x46] +# CHECK-LE: vcmpequh. 2, 3, 4 # encoding: [0x46,0x24,0x43,0x10] + vcmpequh. 2, 3, 4 +# CHECK-BE: vcmpequw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x86] +# CHECK-LE: vcmpequw 2, 3, 4 # encoding: [0x86,0x20,0x43,0x10] + vcmpequw 2, 3, 4 +# CHECK-BE: vcmpequw. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x86] +# CHECK-LE: vcmpequw. 2, 3, 4 # encoding: [0x86,0x24,0x43,0x10] + vcmpequw. 2, 3, 4 +# CHECK-BE: vcmpgtsb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x06] +# CHECK-LE: vcmpgtsb 2, 3, 4 # encoding: [0x06,0x23,0x43,0x10] + vcmpgtsb 2, 3, 4 +# CHECK-BE: vcmpgtsb. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x06] +# CHECK-LE: vcmpgtsb. 2, 3, 4 # encoding: [0x06,0x27,0x43,0x10] + vcmpgtsb. 2, 3, 4 +# CHECK-BE: vcmpgtsh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x46] +# CHECK-LE: vcmpgtsh 2, 3, 4 # encoding: [0x46,0x23,0x43,0x10] + vcmpgtsh 2, 3, 4 +# CHECK-BE: vcmpgtsh. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x46] +# CHECK-LE: vcmpgtsh. 2, 3, 4 # encoding: [0x46,0x27,0x43,0x10] + vcmpgtsh. 2, 3, 4 +# CHECK-BE: vcmpgtsw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x86] +# CHECK-LE: vcmpgtsw 2, 3, 4 # encoding: [0x86,0x23,0x43,0x10] + vcmpgtsw 2, 3, 4 +# CHECK-BE: vcmpgtsw. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x86] +# CHECK-LE: vcmpgtsw. 2, 3, 4 # encoding: [0x86,0x27,0x43,0x10] + vcmpgtsw. 2, 3, 4 +# CHECK-BE: vcmpgtub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x06] +# CHECK-LE: vcmpgtub 2, 3, 4 # encoding: [0x06,0x22,0x43,0x10] + vcmpgtub 2, 3, 4 +# CHECK-BE: vcmpgtub. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x06] +# CHECK-LE: vcmpgtub. 2, 3, 4 # encoding: [0x06,0x26,0x43,0x10] + vcmpgtub. 2, 3, 4 +# CHECK-BE: vcmpgtuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x46] +# CHECK-LE: vcmpgtuh 2, 3, 4 # encoding: [0x46,0x22,0x43,0x10] + vcmpgtuh 2, 3, 4 +# CHECK-BE: vcmpgtuh. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x46] +# CHECK-LE: vcmpgtuh. 2, 3, 4 # encoding: [0x46,0x26,0x43,0x10] + vcmpgtuh. 2, 3, 4 +# CHECK-BE: vcmpgtuw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x86] +# CHECK-LE: vcmpgtuw 2, 3, 4 # encoding: [0x86,0x22,0x43,0x10] + vcmpgtuw 2, 3, 4 +# CHECK-BE: vcmpgtuw. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x86] +# CHECK-LE: vcmpgtuw. 2, 3, 4 # encoding: [0x86,0x26,0x43,0x10] + vcmpgtuw. 2, 3, 4 # Vector integer logical instructions -# CHECK: vand 2, 3, 4 # encoding: [0x10,0x43,0x24,0x04] - vand 2, 3, 4 -# CHECK: vandc 2, 3, 4 # encoding: [0x10,0x43,0x24,0x44] - vandc 2, 3, 4 -# CHECK: vnor 2, 3, 4 # encoding: [0x10,0x43,0x25,0x04] - vnor 2, 3, 4 -# CHECK: vor 2, 3, 4 # encoding: [0x10,0x43,0x24,0x84] - vor 2, 3, 4 -# CHECK: vxor 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc4] - vxor 2, 3, 4 +# CHECK-BE: vand 2, 3, 4 # encoding: [0x10,0x43,0x24,0x04] +# CHECK-LE: vand 2, 3, 4 # encoding: [0x04,0x24,0x43,0x10] + vand 2, 3, 4 +# CHECK-BE: vandc 2, 3, 4 # encoding: [0x10,0x43,0x24,0x44] +# CHECK-LE: vandc 2, 3, 4 # encoding: [0x44,0x24,0x43,0x10] + vandc 2, 3, 4 +# CHECK-BE: vnor 2, 3, 4 # encoding: [0x10,0x43,0x25,0x04] +# CHECK-LE: vnor 2, 3, 4 # encoding: [0x04,0x25,0x43,0x10] + vnor 2, 3, 4 +# CHECK-BE: vor 2, 3, 4 # encoding: [0x10,0x43,0x24,0x84] +# CHECK-LE: vor 2, 3, 4 # encoding: [0x84,0x24,0x43,0x10] + vor 2, 3, 4 +# CHECK-BE: vxor 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc4] +# CHECK-LE: vxor 2, 3, 4 # encoding: [0xc4,0x24,0x43,0x10] + vxor 2, 3, 4 # Vector integer rotate and shift instructions -# CHECK: vrlb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x04] - vrlb 2, 3, 4 -# CHECK: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44] - vrlh 2, 3, 4 -# CHECK: vrlw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x84] - vrlw 2, 3, 4 - -# CHECK: vslb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x04] - vslb 2, 3, 4 -# CHECK: vslh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x44] - vslh 2, 3, 4 -# CHECK: vslw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x84] - vslw 2, 3, 4 -# CHECK: vsrb 2, 3, 4 # encoding: [0x10,0x43,0x22,0x04] - vsrb 2, 3, 4 -# CHECK: vsrh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x44] - vsrh 2, 3, 4 -# CHECK: vsrw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x84] - vsrw 2, 3, 4 -# CHECK: vsrab 2, 3, 4 # encoding: [0x10,0x43,0x23,0x04] - vsrab 2, 3, 4 -# CHECK: vsrah 2, 3, 4 # encoding: [0x10,0x43,0x23,0x44] - vsrah 2, 3, 4 -# CHECK: vsraw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x84] - vsraw 2, 3, 4 +# CHECK-BE: vrlb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x04] +# CHECK-LE: vrlb 2, 3, 4 # encoding: [0x04,0x20,0x43,0x10] + vrlb 2, 3, 4 +# CHECK-BE: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44] +# CHECK-LE: vrlh 2, 3, 4 # encoding: [0x44,0x20,0x43,0x10] + vrlh 2, 3, 4 +# CHECK-BE: vrlw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x84] +# CHECK-LE: vrlw 2, 3, 4 # encoding: [0x84,0x20,0x43,0x10] + vrlw 2, 3, 4 + +# CHECK-BE: vslb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x04] +# CHECK-LE: vslb 2, 3, 4 # encoding: [0x04,0x21,0x43,0x10] + vslb 2, 3, 4 +# CHECK-BE: vslh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x44] +# CHECK-LE: vslh 2, 3, 4 # encoding: [0x44,0x21,0x43,0x10] + vslh 2, 3, 4 +# CHECK-BE: vslw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x84] +# CHECK-LE: vslw 2, 3, 4 # encoding: [0x84,0x21,0x43,0x10] + vslw 2, 3, 4 +# CHECK-BE: vsrb 2, 3, 4 # encoding: [0x10,0x43,0x22,0x04] +# CHECK-LE: vsrb 2, 3, 4 # encoding: [0x04,0x22,0x43,0x10] + vsrb 2, 3, 4 +# CHECK-BE: vsrh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x44] +# CHECK-LE: vsrh 2, 3, 4 # encoding: [0x44,0x22,0x43,0x10] + vsrh 2, 3, 4 +# CHECK-BE: vsrw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x84] +# CHECK-LE: vsrw 2, 3, 4 # encoding: [0x84,0x22,0x43,0x10] + vsrw 2, 3, 4 +# CHECK-BE: vsrab 2, 3, 4 # encoding: [0x10,0x43,0x23,0x04] +# CHECK-LE: vsrab 2, 3, 4 # encoding: [0x04,0x23,0x43,0x10] + vsrab 2, 3, 4 +# CHECK-BE: vsrah 2, 3, 4 # encoding: [0x10,0x43,0x23,0x44] +# CHECK-LE: vsrah 2, 3, 4 # encoding: [0x44,0x23,0x43,0x10] + vsrah 2, 3, 4 +# CHECK-BE: vsraw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x84] +# CHECK-LE: vsraw 2, 3, 4 # encoding: [0x84,0x23,0x43,0x10] + vsraw 2, 3, 4 # Vector floating-point instructions -# CHECK: vaddfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0a] - vaddfp 2, 3, 4 -# CHECK: vsubfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4a] - vsubfp 2, 3, 4 -# CHECK: vmaddfp 2, 3, 4, 5 # encoding: [0x10,0x43,0x29,0x2e] - vmaddfp 2, 3, 4, 5 -# CHECK: vnmsubfp 2, 3, 4, 5 # encoding: [0x10,0x43,0x29,0x2f] - vnmsubfp 2, 3, 4, 5 - -# CHECK: vmaxfp 2, 3, 4 # encoding: [0x10,0x43,0x24,0x0a] - vmaxfp 2, 3, 4 -# CHECK: vminfp 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4a] - vminfp 2, 3, 4 - -# CHECK: vctsxs 2, 3, 4 # encoding: [0x10,0x44,0x1b,0xca] - vctsxs 2, 3, 4 -# CHECK: vctuxs 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x8a] - vctuxs 2, 3, 4 -# CHECK: vcfsx 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x4a] - vcfsx 2, 3, 4 -# CHECK: vcfux 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x0a] - vcfux 2, 3, 4 -# CHECK: vrfim 2, 3 # encoding: [0x10,0x40,0x1a,0xca] - vrfim 2, 3 -# CHECK: vrfin 2, 3 # encoding: [0x10,0x40,0x1a,0x0a] - vrfin 2, 3 -# CHECK: vrfip 2, 3 # encoding: [0x10,0x40,0x1a,0x8a] - vrfip 2, 3 -# CHECK: vrfiz 2, 3 # encoding: [0x10,0x40,0x1a,0x4a] - vrfiz 2, 3 - -# CHECK: vcmpbfp 2, 3, 4 # encoding: [0x10,0x43,0x23,0xc6] - vcmpbfp 2, 3, 4 -# CHECK: vcmpbfp. 2, 3, 4 # encoding: [0x10,0x43,0x27,0xc6] - vcmpbfp. 2, 3, 4 -# CHECK: vcmpeqfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0xc6] - vcmpeqfp 2, 3, 4 -# CHECK: vcmpeqfp. 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc6] - vcmpeqfp. 2, 3, 4 -# CHECK: vcmpgefp 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc6] - vcmpgefp 2, 3, 4 -# CHECK: vcmpgefp. 2, 3, 4 # encoding: [0x10,0x43,0x25,0xc6] - vcmpgefp. 2, 3, 4 -# CHECK: vcmpgtfp 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc6] - vcmpgtfp 2, 3, 4 -# CHECK: vcmpgtfp. 2, 3, 4 # encoding: [0x10,0x43,0x26,0xc6] - vcmpgtfp. 2, 3, 4 - -# CHECK: vexptefp 2, 3 # encoding: [0x10,0x40,0x19,0x8a] - vexptefp 2, 3 -# CHECK: vlogefp 2, 3 # encoding: [0x10,0x40,0x19,0xca] - vlogefp 2, 3 -# CHECK: vrefp 2, 3 # encoding: [0x10,0x40,0x19,0x0a] - vrefp 2, 3 -# CHECK: vrsqrtefp 2, 3 # encoding: [0x10,0x40,0x19,0x4a] - vrsqrtefp 2, 3 +# CHECK-BE: vaddfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0a] +# CHECK-LE: vaddfp 2, 3, 4 # encoding: [0x0a,0x20,0x43,0x10] + vaddfp 2, 3, 4 +# CHECK-BE: vsubfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4a] +# CHECK-LE: vsubfp 2, 3, 4 # encoding: [0x4a,0x20,0x43,0x10] + vsubfp 2, 3, 4 +# CHECK-BE: vmaddfp 2, 3, 4, 5 # encoding: [0x10,0x43,0x29,0x2e] +# CHECK-LE: vmaddfp 2, 3, 4, 5 # encoding: [0x2e,0x29,0x43,0x10] + vmaddfp 2, 3, 4, 5 +# CHECK-BE: vnmsubfp 2, 3, 4, 5 # encoding: [0x10,0x43,0x29,0x2f] +# CHECK-LE: vnmsubfp 2, 3, 4, 5 # encoding: [0x2f,0x29,0x43,0x10] + vnmsubfp 2, 3, 4, 5 + +# CHECK-BE: vmaxfp 2, 3, 4 # encoding: [0x10,0x43,0x24,0x0a] +# CHECK-LE: vmaxfp 2, 3, 4 # encoding: [0x0a,0x24,0x43,0x10] + vmaxfp 2, 3, 4 +# CHECK-BE: vminfp 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4a] +# CHECK-LE: vminfp 2, 3, 4 # encoding: [0x4a,0x24,0x43,0x10] + vminfp 2, 3, 4 + +# CHECK-BE: vctsxs 2, 3, 4 # encoding: [0x10,0x44,0x1b,0xca] +# CHECK-LE: vctsxs 2, 3, 4 # encoding: [0xca,0x1b,0x44,0x10] + vctsxs 2, 3, 4 +# CHECK-BE: vctuxs 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x8a] +# CHECK-LE: vctuxs 2, 3, 4 # encoding: [0x8a,0x1b,0x44,0x10] + vctuxs 2, 3, 4 +# CHECK-BE: vcfsx 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x4a] +# CHECK-LE: vcfsx 2, 3, 4 # encoding: [0x4a,0x1b,0x44,0x10] + vcfsx 2, 3, 4 +# CHECK-BE: vcfux 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x0a] +# CHECK-LE: vcfux 2, 3, 4 # encoding: [0x0a,0x1b,0x44,0x10] + vcfux 2, 3, 4 +# CHECK-BE: vrfim 2, 3 # encoding: [0x10,0x40,0x1a,0xca] +# CHECK-LE: vrfim 2, 3 # encoding: [0xca,0x1a,0x40,0x10] + vrfim 2, 3 +# CHECK-BE: vrfin 2, 3 # encoding: [0x10,0x40,0x1a,0x0a] +# CHECK-LE: vrfin 2, 3 # encoding: [0x0a,0x1a,0x40,0x10] + vrfin 2, 3 +# CHECK-BE: vrfip 2, 3 # encoding: [0x10,0x40,0x1a,0x8a] +# CHECK-LE: vrfip 2, 3 # encoding: [0x8a,0x1a,0x40,0x10] + vrfip 2, 3 +# CHECK-BE: vrfiz 2, 3 # encoding: [0x10,0x40,0x1a,0x4a] +# CHECK-LE: vrfiz 2, 3 # encoding: [0x4a,0x1a,0x40,0x10] + vrfiz 2, 3 + +# CHECK-BE: vcmpbfp 2, 3, 4 # encoding: [0x10,0x43,0x23,0xc6] +# CHECK-LE: vcmpbfp 2, 3, 4 # encoding: [0xc6,0x23,0x43,0x10] + vcmpbfp 2, 3, 4 +# CHECK-BE: vcmpbfp. 2, 3, 4 # encoding: [0x10,0x43,0x27,0xc6] +# CHECK-LE: vcmpbfp. 2, 3, 4 # encoding: [0xc6,0x27,0x43,0x10] + vcmpbfp. 2, 3, 4 +# CHECK-BE: vcmpeqfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0xc6] +# CHECK-LE: vcmpeqfp 2, 3, 4 # encoding: [0xc6,0x20,0x43,0x10] + vcmpeqfp 2, 3, 4 +# CHECK-BE: vcmpeqfp. 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc6] +# CHECK-LE: vcmpeqfp. 2, 3, 4 # encoding: [0xc6,0x24,0x43,0x10] + vcmpeqfp. 2, 3, 4 +# CHECK-BE: vcmpgefp 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc6] +# CHECK-LE: vcmpgefp 2, 3, 4 # encoding: [0xc6,0x21,0x43,0x10] + vcmpgefp 2, 3, 4 +# CHECK-BE: vcmpgefp. 2, 3, 4 # encoding: [0x10,0x43,0x25,0xc6] +# CHECK-LE: vcmpgefp. 2, 3, 4 # encoding: [0xc6,0x25,0x43,0x10] + vcmpgefp. 2, 3, 4 +# CHECK-BE: vcmpgtfp 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc6] +# CHECK-LE: vcmpgtfp 2, 3, 4 # encoding: [0xc6,0x22,0x43,0x10] + vcmpgtfp 2, 3, 4 +# CHECK-BE: vcmpgtfp. 2, 3, 4 # encoding: [0x10,0x43,0x26,0xc6] +# CHECK-LE: vcmpgtfp. 2, 3, 4 # encoding: [0xc6,0x26,0x43,0x10] + vcmpgtfp. 2, 3, 4 + +# CHECK-BE: vexptefp 2, 3 # encoding: [0x10,0x40,0x19,0x8a] +# CHECK-LE: vexptefp 2, 3 # encoding: [0x8a,0x19,0x40,0x10] + vexptefp 2, 3 +# CHECK-BE: vlogefp 2, 3 # encoding: [0x10,0x40,0x19,0xca] +# CHECK-LE: vlogefp 2, 3 # encoding: [0xca,0x19,0x40,0x10] + vlogefp 2, 3 +# CHECK-BE: vrefp 2, 3 # encoding: [0x10,0x40,0x19,0x0a] +# CHECK-LE: vrefp 2, 3 # encoding: [0x0a,0x19,0x40,0x10] + vrefp 2, 3 +# CHECK-BE: vrsqrtefp 2, 3 # encoding: [0x10,0x40,0x19,0x4a] +# CHECK-LE: vrsqrtefp 2, 3 # encoding: [0x4a,0x19,0x40,0x10] + vrsqrtefp 2, 3 # Vector status and control register instructions -# CHECK: mtvscr 2 # encoding: [0x10,0x00,0x16,0x44] - mtvscr 2 -# CHECK: mfvscr 2 # encoding: [0x10,0x40,0x06,0x04] - mfvscr 2 +# CHECK-BE: mtvscr 2 # encoding: [0x10,0x00,0x16,0x44] +# CHECK-LE: mtvscr 2 # encoding: [0x44,0x16,0x00,0x10] + mtvscr 2 +# CHECK-BE: mfvscr 2 # encoding: [0x10,0x40,0x06,0x04] +# CHECK-LE: mfvscr 2 # encoding: [0x04,0x06,0x40,0x10] + mfvscr 2 Index: llvm-suse/test/MC/PowerPC/ppc64-encoding.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-encoding.s +++ llvm-suse/test/MC/PowerPC/ppc64-encoding.s @@ -1,551 +1,769 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Branch facility # Branch instructions -# CHECK: b target # encoding: [0b010010AA,A,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 - b target -# CHECK: ba target # encoding: [0b010010AA,A,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs - ba target -# CHECK: bl target # encoding: [0b010010AA,A,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 - bl target -# CHECK: bla target # encoding: [0b010010AA,A,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs - bla target - -# CHECK: bc 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bc 4, 10, target -# CHECK: bca 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bca 4, 10, target -# CHECK: bcl 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA01] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 - bcl 4, 10, target -# CHECK: bcla 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA11] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs - bcla 4, 10, target - -# CHECK: bclr 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x20] - bclr 4, 10, 3 -# CHECK: bclr 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x20] - bclr 4, 10 -# CHECK: bclrl 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x21] - bclrl 4, 10, 3 -# CHECK: bclrl 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x21] - bclrl 4, 10 -# CHECK: bcctr 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x20] - bcctr 4, 10, 3 -# CHECK: bcctr 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x20] - bcctr 4, 10 -# CHECK: bcctrl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x21] - bcctrl 4, 10, 3 -# CHECK: bcctrl 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x21] - bcctrl 4, 10 +# CHECK-BE: b target # encoding: [0b010010AA,A,A,0bAAAAAA00] +# CHECK-LE: b target # encoding: [0bAAAAAA00,A,A,0b010010AA] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 + b target +# CHECK-BE: ba target # encoding: [0b010010AA,A,A,0bAAAAAA10] +# CHECK-LE: ba target # encoding: [0bAAAAAA10,A,A,0b010010AA] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs + ba target +# CHECK-BE: bl target # encoding: [0b010010AA,A,A,0bAAAAAA01] +# CHECK-LE: bl target # encoding: [0bAAAAAA01,A,A,0b010010AA] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 + bl target +# CHECK-BE: bla target # encoding: [0b010010AA,A,A,0bAAAAAA11] +# CHECK-LE: bla target # encoding: [0bAAAAAA11,A,A,0b010010AA] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs + bla target + +# CHECK-BE: bc 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA00] +# CHECK-LE: bc 4, 10, target # encoding: [0bAAAAAA00,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bc 4, 10, target +# CHECK-BE: bca 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA10] +# CHECK-LE: bca 4, 10, target # encoding: [0bAAAAAA10,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bca 4, 10, target +# CHECK-BE: bcl 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA01] +# CHECK-LE: bcl 4, 10, target # encoding: [0bAAAAAA01,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bcl 4, 10, target +# CHECK-BE: bcla 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA11] +# CHECK-LE: bcla 4, 10, target # encoding: [0bAAAAAA11,A,0x8a,0x40] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bcla 4, 10, target + +# CHECK-BE: bclr 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x20] +# CHECK-LE: bclr 4, 10, 3 # encoding: [0x20,0x18,0x8a,0x4c] + bclr 4, 10, 3 +# CHECK-BE: bclr 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x20] +# CHECK-LE: bclr 4, 10, 0 # encoding: [0x20,0x00,0x8a,0x4c] + bclr 4, 10 +# CHECK-BE: bclrl 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x21] +# CHECK-LE: bclrl 4, 10, 3 # encoding: [0x21,0x18,0x8a,0x4c] + bclrl 4, 10, 3 +# CHECK-BE: bclrl 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x21] +# CHECK-LE: bclrl 4, 10, 0 # encoding: [0x21,0x00,0x8a,0x4c] + bclrl 4, 10 +# CHECK-BE: bcctr 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x20] +# CHECK-LE: bcctr 4, 10, 3 # encoding: [0x20,0x1c,0x8a,0x4c] + bcctr 4, 10, 3 +# CHECK-BE: bcctr 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x20] +# CHECK-LE: bcctr 4, 10, 0 # encoding: [0x20,0x04,0x8a,0x4c] + bcctr 4, 10 +# CHECK-BE: bcctrl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x21] +# CHECK-LE: bcctrl 4, 10, 3 # encoding: [0x21,0x1c,0x8a,0x4c] + bcctrl 4, 10, 3 +# CHECK-BE: bcctrl 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x21] +# CHECK-LE: bcctrl 4, 10, 0 # encoding: [0x21,0x04,0x8a,0x4c] + bcctrl 4, 10 # Condition register instructions -# CHECK: crand 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x02] - crand 2, 3, 4 -# CHECK: crnand 2, 3, 4 # encoding: [0x4c,0x43,0x21,0xc2] - crnand 2, 3, 4 -# CHECK: cror 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x82] - cror 2, 3, 4 -# CHECK: crxor 2, 3, 4 # encoding: [0x4c,0x43,0x21,0x82] - crxor 2, 3, 4 -# CHECK: crnor 2, 3, 4 # encoding: [0x4c,0x43,0x20,0x42] - crnor 2, 3, 4 -# CHECK: creqv 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x42] - creqv 2, 3, 4 -# CHECK: crandc 2, 3, 4 # encoding: [0x4c,0x43,0x21,0x02] - crandc 2, 3, 4 -# CHECK: crorc 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x42] - crorc 2, 3, 4 -# CHECK: mcrf 2, 3 # encoding: [0x4d,0x0c,0x00,0x00] - mcrf 2, 3 +# CHECK-BE: crand 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x02] +# CHECK-LE: crand 2, 3, 4 # encoding: [0x02,0x22,0x43,0x4c] + crand 2, 3, 4 +# CHECK-BE: crnand 2, 3, 4 # encoding: [0x4c,0x43,0x21,0xc2] +# CHECK-LE: crnand 2, 3, 4 # encoding: [0xc2,0x21,0x43,0x4c] + crnand 2, 3, 4 +# CHECK-BE: cror 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x82] +# CHECK-LE: cror 2, 3, 4 # encoding: [0x82,0x23,0x43,0x4c] + cror 2, 3, 4 +# CHECK-BE: crxor 2, 3, 4 # encoding: [0x4c,0x43,0x21,0x82] +# CHECK-LE: crxor 2, 3, 4 # encoding: [0x82,0x21,0x43,0x4c] + crxor 2, 3, 4 +# CHECK-BE: crnor 2, 3, 4 # encoding: [0x4c,0x43,0x20,0x42] +# CHECK-LE: crnor 2, 3, 4 # encoding: [0x42,0x20,0x43,0x4c] + crnor 2, 3, 4 +# CHECK-BE: creqv 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x42] +# CHECK-LE: creqv 2, 3, 4 # encoding: [0x42,0x22,0x43,0x4c] + creqv 2, 3, 4 +# CHECK-BE: crandc 2, 3, 4 # encoding: [0x4c,0x43,0x21,0x02] +# CHECK-LE: crandc 2, 3, 4 # encoding: [0x02,0x21,0x43,0x4c] + crandc 2, 3, 4 +# CHECK-BE: crorc 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x42] +# CHECK-LE: crorc 2, 3, 4 # encoding: [0x42,0x23,0x43,0x4c] + crorc 2, 3, 4 +# CHECK-BE: mcrf 2, 3 # encoding: [0x4d,0x0c,0x00,0x00] +# CHECK-LE: mcrf 2, 3 # encoding: [0x00,0x00,0x0c,0x4d] + mcrf 2, 3 # System call instruction -# CHECK: sc 1 # encoding: [0x44,0x00,0x00,0x22] - sc 1 -# CHECK: sc 0 # encoding: [0x44,0x00,0x00,0x02] - sc +# CHECK-BE: sc 1 # encoding: [0x44,0x00,0x00,0x22] +# CHECK-LE: sc 1 # encoding: [0x22,0x00,0x00,0x44] + sc 1 +# CHECK-BE: sc 0 # encoding: [0x44,0x00,0x00,0x02] +# CHECK-LE: sc 0 # encoding: [0x02,0x00,0x00,0x44] + sc # Fixed-point facility # Fixed-point load instructions -# CHECK: lbz 2, 128(4) # encoding: [0x88,0x44,0x00,0x80] - lbz 2, 128(4) -# CHECK: lbzx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xae] - lbzx 2, 3, 4 -# CHECK: lbzu 2, 128(4) # encoding: [0x8c,0x44,0x00,0x80] - lbzu 2, 128(4) -# CHECK: lbzux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xee] - lbzux 2, 3, 4 -# CHECK: lhz 2, 128(4) # encoding: [0xa0,0x44,0x00,0x80] - lhz 2, 128(4) -# CHECK: lhzx 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x2e] - lhzx 2, 3, 4 -# CHECK: lhzu 2, 128(4) # encoding: [0xa4,0x44,0x00,0x80] - lhzu 2, 128(4) -# CHECK: lhzux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x6e] - lhzux 2, 3, 4 -# CHECK: lha 2, 128(4) # encoding: [0xa8,0x44,0x00,0x80] - lha 2, 128(4) -# CHECK: lhax 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xae] - lhax 2, 3, 4 -# CHECK: lhau 2, 128(4) # encoding: [0xac,0x44,0x00,0x80] - lhau 2, 128(4) -# CHECK: lhaux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xee] - lhaux 2, 3, 4 -# CHECK: lwz 2, 128(4) # encoding: [0x80,0x44,0x00,0x80] - lwz 2, 128(4) -# CHECK: lwzx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x2e] - lwzx 2, 3, 4 -# CHECK: lwzu 2, 128(4) # encoding: [0x84,0x44,0x00,0x80] - lwzu 2, 128(4) -# CHECK: lwzux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6e] - lwzux 2, 3, 4 -# CHECK: lwa 2, 128(4) # encoding: [0xe8,0x44,0x00,0x82] - lwa 2, 128(4) -# CHECK: lwax 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xaa] - lwax 2, 3, 4 -# CHECK: lwaux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xea] - lwaux 2, 3, 4 -# CHECK: ld 2, 128(4) # encoding: [0xe8,0x44,0x00,0x80] - ld 2, 128(4) -# CHECK: ldx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x2a] - ldx 2, 3, 4 -# CHECK: ldu 2, 128(4) # encoding: [0xe8,0x44,0x00,0x81] - ldu 2, 128(4) -# CHECK: ldux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6a] - ldux 2, 3, 4 +# CHECK-BE: lbz 2, 128(4) # encoding: [0x88,0x44,0x00,0x80] +# CHECK-LE: lbz 2, 128(4) # encoding: [0x80,0x00,0x44,0x88] + lbz 2, 128(4) +# CHECK-BE: lbzx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xae] +# CHECK-LE: lbzx 2, 3, 4 # encoding: [0xae,0x20,0x43,0x7c] + lbzx 2, 3, 4 +# CHECK-BE: lbzu 2, 128(4) # encoding: [0x8c,0x44,0x00,0x80] +# CHECK-LE: lbzu 2, 128(4) # encoding: [0x80,0x00,0x44,0x8c] + lbzu 2, 128(4) +# CHECK-BE: lbzux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xee] +# CHECK-LE: lbzux 2, 3, 4 # encoding: [0xee,0x20,0x43,0x7c] + lbzux 2, 3, 4 +# CHECK-BE: lhz 2, 128(4) # encoding: [0xa0,0x44,0x00,0x80] +# CHECK-LE: lhz 2, 128(4) # encoding: [0x80,0x00,0x44,0xa0] + lhz 2, 128(4) +# CHECK-BE: lhzx 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x2e] +# CHECK-LE: lhzx 2, 3, 4 # encoding: [0x2e,0x22,0x43,0x7c] + lhzx 2, 3, 4 +# CHECK-BE: lhzu 2, 128(4) # encoding: [0xa4,0x44,0x00,0x80] +# CHECK-LE: lhzu 2, 128(4) # encoding: [0x80,0x00,0x44,0xa4] + lhzu 2, 128(4) +# CHECK-BE: lhzux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x6e] +# CHECK-LE: lhzux 2, 3, 4 # encoding: [0x6e,0x22,0x43,0x7c] + lhzux 2, 3, 4 +# CHECK-BE: lha 2, 128(4) # encoding: [0xa8,0x44,0x00,0x80] +# CHECK-LE: lha 2, 128(4) # encoding: [0x80,0x00,0x44,0xa8] + lha 2, 128(4) +# CHECK-BE: lhax 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xae] +# CHECK-LE: lhax 2, 3, 4 # encoding: [0xae,0x22,0x43,0x7c] + lhax 2, 3, 4 +# CHECK-BE: lhau 2, 128(4) # encoding: [0xac,0x44,0x00,0x80] +# CHECK-LE: lhau 2, 128(4) # encoding: [0x80,0x00,0x44,0xac] + lhau 2, 128(4) +# CHECK-BE: lhaux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xee] +# CHECK-LE: lhaux 2, 3, 4 # encoding: [0xee,0x22,0x43,0x7c] + lhaux 2, 3, 4 +# CHECK-BE: lwz 2, 128(4) # encoding: [0x80,0x44,0x00,0x80] +# CHECK-LE: lwz 2, 128(4) # encoding: [0x80,0x00,0x44,0x80] + lwz 2, 128(4) +# CHECK-BE: lwzx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x2e] +# CHECK-LE: lwzx 2, 3, 4 # encoding: [0x2e,0x20,0x43,0x7c] + lwzx 2, 3, 4 +# CHECK-BE: lwzu 2, 128(4) # encoding: [0x84,0x44,0x00,0x80] +# CHECK-LE: lwzu 2, 128(4) # encoding: [0x80,0x00,0x44,0x84] + lwzu 2, 128(4) +# CHECK-BE: lwzux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6e] +# CHECK-LE: lwzux 2, 3, 4 # encoding: [0x6e,0x20,0x43,0x7c] + lwzux 2, 3, 4 +# CHECK-BE: lwa 2, 128(4) # encoding: [0xe8,0x44,0x00,0x82] +# CHECK-LE: lwa 2, 128(4) # encoding: [0x82,0x00,0x44,0xe8] + lwa 2, 128(4) +# CHECK-BE: lwax 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xaa] +# CHECK-LE: lwax 2, 3, 4 # encoding: [0xaa,0x22,0x43,0x7c] + lwax 2, 3, 4 +# CHECK-BE: lwaux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xea] +# CHECK-LE: lwaux 2, 3, 4 # encoding: [0xea,0x22,0x43,0x7c] + lwaux 2, 3, 4 +# CHECK-BE: ld 2, 128(4) # encoding: [0xe8,0x44,0x00,0x80] +# CHECK-LE: ld 2, 128(4) # encoding: [0x80,0x00,0x44,0xe8] + ld 2, 128(4) +# CHECK-BE: ldx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x2a] +# CHECK-LE: ldx 2, 3, 4 # encoding: [0x2a,0x20,0x43,0x7c] + ldx 2, 3, 4 +# CHECK-BE: ldu 2, 128(4) # encoding: [0xe8,0x44,0x00,0x81] +# CHECK-LE: ldu 2, 128(4) # encoding: [0x81,0x00,0x44,0xe8] + ldu 2, 128(4) +# CHECK-BE: ldux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6a] +# CHECK-LE: ldux 2, 3, 4 # encoding: [0x6a,0x20,0x43,0x7c] + ldux 2, 3, 4 # Fixed-point store instructions -# CHECK: stb 2, 128(4) # encoding: [0x98,0x44,0x00,0x80] - stb 2, 128(4) -# CHECK: stbx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xae] - stbx 2, 3, 4 -# CHECK: stbu 2, 128(4) # encoding: [0x9c,0x44,0x00,0x80] - stbu 2, 128(4) -# CHECK: stbux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xee] - stbux 2, 3, 4 -# CHECK: sth 2, 128(4) # encoding: [0xb0,0x44,0x00,0x80] - sth 2, 128(4) -# CHECK: sthx 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x2e] - sthx 2, 3, 4 -# CHECK: sthu 2, 128(4) # encoding: [0xb4,0x44,0x00,0x80] - sthu 2, 128(4) -# CHECK: sthux 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x6e] - sthux 2, 3, 4 -# CHECK: stw 2, 128(4) # encoding: [0x90,0x44,0x00,0x80] - stw 2, 128(4) -# CHECK: stwx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2e] - stwx 2, 3, 4 -# CHECK: stwu 2, 128(4) # encoding: [0x94,0x44,0x00,0x80] - stwu 2, 128(4) -# CHECK: stwux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x6e] - stwux 2, 3, 4 -# CHECK: std 2, 128(4) # encoding: [0xf8,0x44,0x00,0x80] - std 2, 128(4) -# CHECK: stdx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2a] - stdx 2, 3, 4 -# CHECK: stdu 2, 128(4) # encoding: [0xf8,0x44,0x00,0x81] - stdu 2, 128(4) -# CHECK: stdux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x6a] - stdux 2, 3, 4 +# CHECK-BE: stb 2, 128(4) # encoding: [0x98,0x44,0x00,0x80] +# CHECK-LE: stb 2, 128(4) # encoding: [0x80,0x00,0x44,0x98] + stb 2, 128(4) +# CHECK-BE: stbx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xae] +# CHECK-LE: stbx 2, 3, 4 # encoding: [0xae,0x21,0x43,0x7c] + stbx 2, 3, 4 +# CHECK-BE: stbu 2, 128(4) # encoding: [0x9c,0x44,0x00,0x80] +# CHECK-LE: stbu 2, 128(4) # encoding: [0x80,0x00,0x44,0x9c] + stbu 2, 128(4) +# CHECK-BE: stbux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xee] +# CHECK-LE: stbux 2, 3, 4 # encoding: [0xee,0x21,0x43,0x7c] + stbux 2, 3, 4 +# CHECK-BE: sth 2, 128(4) # encoding: [0xb0,0x44,0x00,0x80] +# CHECK-LE: sth 2, 128(4) # encoding: [0x80,0x00,0x44,0xb0] + sth 2, 128(4) +# CHECK-BE: sthx 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x2e] +# CHECK-LE: sthx 2, 3, 4 # encoding: [0x2e,0x23,0x43,0x7c] + sthx 2, 3, 4 +# CHECK-BE: sthu 2, 128(4) # encoding: [0xb4,0x44,0x00,0x80] +# CHECK-LE: sthu 2, 128(4) # encoding: [0x80,0x00,0x44,0xb4] + sthu 2, 128(4) +# CHECK-BE: sthux 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x6e] +# CHECK-LE: sthux 2, 3, 4 # encoding: [0x6e,0x23,0x43,0x7c] + sthux 2, 3, 4 +# CHECK-BE: stw 2, 128(4) # encoding: [0x90,0x44,0x00,0x80] +# CHECK-LE: stw 2, 128(4) # encoding: [0x80,0x00,0x44,0x90] + stw 2, 128(4) +# CHECK-BE: stwx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2e] +# CHECK-LE: stwx 2, 3, 4 # encoding: [0x2e,0x21,0x43,0x7c] + stwx 2, 3, 4 +# CHECK-BE: stwu 2, 128(4) # encoding: [0x94,0x44,0x00,0x80] +# CHECK-LE: stwu 2, 128(4) # encoding: [0x80,0x00,0x44,0x94] + stwu 2, 128(4) +# CHECK-BE: stwux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x6e] +# CHECK-LE: stwux 2, 3, 4 # encoding: [0x6e,0x21,0x43,0x7c] + stwux 2, 3, 4 +# CHECK-BE: std 2, 128(4) # encoding: [0xf8,0x44,0x00,0x80] +# CHECK-LE: std 2, 128(4) # encoding: [0x80,0x00,0x44,0xf8] + std 2, 128(4) +# CHECK-BE: stdx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2a] +# CHECK-LE: stdx 2, 3, 4 # encoding: [0x2a,0x21,0x43,0x7c] + stdx 2, 3, 4 +# CHECK-BE: stdu 2, 128(4) # encoding: [0xf8,0x44,0x00,0x81] +# CHECK-LE: stdu 2, 128(4) # encoding: [0x81,0x00,0x44,0xf8] + stdu 2, 128(4) +# CHECK-BE: stdux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x6a] +# CHECK-LE: stdux 2, 3, 4 # encoding: [0x6a,0x21,0x43,0x7c] + stdux 2, 3, 4 # Fixed-point load and store with byte reversal instructions -# CHECK: lhbrx 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x2c] - lhbrx 2, 3, 4 -# CHECK: sthbrx 2, 3, 4 # encoding: [0x7c,0x43,0x27,0x2c] - sthbrx 2, 3, 4 -# CHECK: lwbrx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x2c] - lwbrx 2, 3, 4 -# CHECK: stwbrx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x2c] - stwbrx 2, 3, 4 -# CHECK: ldbrx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x28] - ldbrx 2, 3, 4 -# CHECK: stdbrx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x28] - stdbrx 2, 3, 4 +# CHECK-BE: lhbrx 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x2c] +# CHECK-LE: lhbrx 2, 3, 4 # encoding: [0x2c,0x26,0x43,0x7c] + lhbrx 2, 3, 4 +# CHECK-BE: sthbrx 2, 3, 4 # encoding: [0x7c,0x43,0x27,0x2c] +# CHECK-LE: sthbrx 2, 3, 4 # encoding: [0x2c,0x27,0x43,0x7c] + sthbrx 2, 3, 4 +# CHECK-BE: lwbrx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x2c] +# CHECK-LE: lwbrx 2, 3, 4 # encoding: [0x2c,0x24,0x43,0x7c] + lwbrx 2, 3, 4 +# CHECK-BE: stwbrx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x2c] +# CHECK-LE: stwbrx 2, 3, 4 # encoding: [0x2c,0x25,0x43,0x7c] + stwbrx 2, 3, 4 +# CHECK-BE: ldbrx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x28] +# CHECK-LE: ldbrx 2, 3, 4 # encoding: [0x28,0x24,0x43,0x7c] + ldbrx 2, 3, 4 +# CHECK-BE: stdbrx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x28] +# CHECK-LE: stdbrx 2, 3, 4 # encoding: [0x28,0x25,0x43,0x7c] + stdbrx 2, 3, 4 # Fixed-point load and store multiple instructions -# CHECK: lmw 2, 128(1) # encoding: [0xb8,0x41,0x00,0x80] - lmw 2, 128(1) -# CHECK: stmw 2, 128(1) # encoding: [0xbc,0x41,0x00,0x80] - stmw 2, 128(1) +# CHECK-BE: lmw 2, 128(1) # encoding: [0xb8,0x41,0x00,0x80] +# CHECK-LE: lmw 2, 128(1) # encoding: [0x80,0x00,0x41,0xb8] + lmw 2, 128(1) +# CHECK-BE: stmw 2, 128(1) # encoding: [0xbc,0x41,0x00,0x80] +# CHECK-LE: stmw 2, 128(1) # encoding: [0x80,0x00,0x41,0xbc] + stmw 2, 128(1) # FIXME: Fixed-point move assist instructions # Fixed-point arithmetic instructions -# CHECK: addi 2, 3, 128 # encoding: [0x38,0x43,0x00,0x80] - addi 2, 3, 128 -# CHECK: addis 2, 3, 128 # encoding: [0x3c,0x43,0x00,0x80] - addis 2, 3, 128 -# CHECK: add 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x14] - add 2, 3, 4 -# CHECK: add. 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x15] - add. 2, 3, 4 -# FIXME: addo 2, 3, 4 -# FIXME: addo. 2, 3, 4 -# CHECK: subf 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x50] - subf 2, 3, 4 -# CHECK: subf. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x51] - subf. 2, 3, 4 -# FIXME: subfo 2, 3, 4 -# FIXME: subfo. 2, 3, 4 -# CHECK: addic 2, 3, 128 # encoding: [0x30,0x43,0x00,0x80] - addic 2, 3, 128 -# CHECK: addic. 2, 3, 128 # encoding: [0x34,0x43,0x00,0x80] - addic. 2, 3, 128 -# CHECK: subfic 2, 3, 4 # encoding: [0x20,0x43,0x00,0x04] - subfic 2, 3, 4 - -# CHECK: addc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x14] - addc 2, 3, 4 -# CHECK: addc. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x15] - addc. 2, 3, 4 -# FIXME: addco 2, 3, 4 -# FIXME: addco. 2, 3, 4 -# CHECK: subfc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x10] - subfc 2, 3, 4 -# CHECK: subfc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x10] - subfc 2, 3, 4 -# FIXME: subfco 2, 3, 4 -# FIXME: subfco. 2, 3, 4 - -# CHECK: adde 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x14] - adde 2, 3, 4 -# CHECK: adde. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x15] - adde. 2, 3, 4 -# FIXME: addeo 2, 3, 4 -# FIXME: addeo. 2, 3, 4 -# CHECK: subfe 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x10] - subfe 2, 3, 4 -# CHECK: subfe. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x11] - subfe. 2, 3, 4 -# FIXME: subfeo 2, 3, 4 -# FIXME: subfeo. 2, 3, 4 - -# CHECK: addme 2, 3 # encoding: [0x7c,0x43,0x01,0xd4] - addme 2, 3 -# CHECK: addme. 2, 3 # encoding: [0x7c,0x43,0x01,0xd5] - addme. 2, 3 -# FIXME: addmeo 2, 3 -# FIXME: addmeo. 2, 3 -# CHECK: subfme 2, 3 # encoding: [0x7c,0x43,0x01,0xd0] - subfme 2, 3 -# CHECK: subfme. 2, 3 # encoding: [0x7c,0x43,0x01,0xd1] - subfme. 2, 3 -# FIXME: subfmeo 2, 3 -# FIXME: subfmeo. 2, 3 - -# CHECK: addze 2, 3 # encoding: [0x7c,0x43,0x01,0x94] - addze 2, 3 -# CHECK: addze. 2, 3 # encoding: [0x7c,0x43,0x01,0x95] - addze. 2, 3 -# FIXME: addzeo 2, 3 -# FIXME: addzeo. 2, 3 -# CHECK: subfze 2, 3 # encoding: [0x7c,0x43,0x01,0x90] - subfze 2, 3 -# CHECK: subfze. 2, 3 # encoding: [0x7c,0x43,0x01,0x91] - subfze. 2, 3 -# FIXME: subfzeo 2, 3 -# FIXME: subfzeo. 2, 3 - -# CHECK: neg 2, 3 # encoding: [0x7c,0x43,0x00,0xd0] - neg 2, 3 -# CHECK: neg. 2, 3 # encoding: [0x7c,0x43,0x00,0xd1] - neg. 2, 3 -# FIXME: nego 2, 3 -# FIXME: nego. 2, 3 - -# CHECK: mulli 2, 3, 128 # encoding: [0x1c,0x43,0x00,0x80] - mulli 2, 3, 128 -# CHECK: mulhw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x96] - mulhw 2, 3, 4 -# CHECK: mulhw. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x97] - mulhw. 2, 3, 4 -# CHECK: mullw 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd6] - mullw 2, 3, 4 -# CHECK: mullw. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd7] - mullw. 2, 3, 4 -# FIXME: mullwo 2, 3, 4 -# FIXME: mullwo. 2, 3, 4 -# CHECK: mulhwu 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x16] - mulhwu 2, 3, 4 -# CHECK: mulhwu. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x17] - mulhwu. 2, 3, 4 - -# CHECK: divw 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd6] - divw 2, 3, 4 -# CHECK: divw. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd7] - divw. 2, 3, 4 -# FIXME: divwo 2, 3, 4 -# FIXME: divwo. 2, 3, 4 -# CHECK: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96] - divwu 2, 3, 4 -# CHECK: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97] - divwu. 2, 3, 4 -# FIXME: divwuo 2, 3, 4 -# FIXME: divwuo. 2, 3, 4 -# FIXME: divwe 2, 3, 4 -# FIXME: divwe. 2, 3, 4 -# FIXME: divweo 2, 3, 4 -# FIXME: divweo. 2, 3, 4 -# FIXME: divweu 2, 3, 4 -# FIXME: divweu. 2, 3, 4 -# FIXME: divweuo 2, 3, 4 -# FIXME: divweuo. 2, 3, 4 - -# CHECK: mulld 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd2] - mulld 2, 3, 4 -# CHECK: mulld. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd3] - mulld. 2, 3, 4 -# FIXME: mulldo 2, 3, 4 -# FIXME: mulldo. 2, 3, 4 -# CHECK: mulhd 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x92] - mulhd 2, 3, 4 -# CHECK: mulhd. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x93] - mulhd. 2, 3, 4 -# CHECK: mulhdu 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x12] - mulhdu 2, 3, 4 -# CHECK: mulhdu. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x13] - mulhdu. 2, 3, 4 - -# CHECK: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2] - divd 2, 3, 4 -# CHECK: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3] - divd. 2, 3, 4 -# FIXME: divdo 2, 3, 4 -# FIXME: divdo. 2, 3, 4 -# CHECK: divdu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x92] - divdu 2, 3, 4 -# CHECK: divdu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x93] - divdu. 2, 3, 4 -# FIXME: divduo 2, 3, 4 -# FIXME: divduo. 2, 3, 4 -# FIXME: divde 2, 3, 4 -# FIXME: divde. 2, 3, 4 -# FIXME: divdeo 2, 3, 4 -# FIXME: divdeo. 2, 3, 4 -# FIXME: divdeu 2, 3, 4 -# FIXME: divdeu. 2, 3, 4 -# FIXME: divdeuo 2, 3, 4 -# FIXME: divdeuo. 2, 3, 4 +# CHECK-BE: addi 2, 3, 128 # encoding: [0x38,0x43,0x00,0x80] +# CHECK-LE: addi 2, 3, 128 # encoding: [0x80,0x00,0x43,0x38] + addi 2, 3, 128 +# CHECK-BE: addis 2, 3, 128 # encoding: [0x3c,0x43,0x00,0x80] +# CHECK-LE: addis 2, 3, 128 # encoding: [0x80,0x00,0x43,0x3c] + addis 2, 3, 128 +# CHECK-BE: add 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x14] +# CHECK-LE: add 2, 3, 4 # encoding: [0x14,0x22,0x43,0x7c] + add 2, 3, 4 +# CHECK-BE: add. 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x15] +# CHECK-LE: add. 2, 3, 4 # encoding: [0x15,0x22,0x43,0x7c] + add. 2, 3, 4 +# FIXME: addo 2, 3, 4 +# FIXME: addo. 2, 3, 4 +# CHECK-BE: subf 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x50] +# CHECK-LE: subf 2, 3, 4 # encoding: [0x50,0x20,0x43,0x7c] + subf 2, 3, 4 +# CHECK-BE: subf. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x51] +# CHECK-LE: subf. 2, 3, 4 # encoding: [0x51,0x20,0x43,0x7c] + subf. 2, 3, 4 +# FIXME: subfo 2, 3, 4 +# FIXME: subfo. 2, 3, 4 +# CHECK-BE: addic 2, 3, 128 # encoding: [0x30,0x43,0x00,0x80] +# CHECK-LE: addic 2, 3, 128 # encoding: [0x80,0x00,0x43,0x30] + addic 2, 3, 128 +# CHECK-BE: addic. 2, 3, 128 # encoding: [0x34,0x43,0x00,0x80] +# CHECK-LE: addic. 2, 3, 128 # encoding: [0x80,0x00,0x43,0x34] + addic. 2, 3, 128 +# CHECK-BE: subfic 2, 3, 4 # encoding: [0x20,0x43,0x00,0x04] +# CHECK-LE: subfic 2, 3, 4 # encoding: [0x04,0x00,0x43,0x20] + subfic 2, 3, 4 + +# CHECK-BE: addc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x14] +# CHECK-LE: addc 2, 3, 4 # encoding: [0x14,0x20,0x43,0x7c] + addc 2, 3, 4 +# CHECK-BE: addc. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x15] +# CHECK-LE: addc. 2, 3, 4 # encoding: [0x15,0x20,0x43,0x7c] + addc. 2, 3, 4 +# FIXME: addco 2, 3, 4 +# FIXME: addco. 2, 3, 4 +# CHECK-BE: subfc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x10] +# CHECK-LE: subfc 2, 3, 4 # encoding: [0x10,0x20,0x43,0x7c] + subfc 2, 3, 4 +# CHECK-BE: subfc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x10] +# CHECK-LE: subfc 2, 3, 4 # encoding: [0x10,0x20,0x43,0x7c] + subfc 2, 3, 4 +# FIXME: subfco 2, 3, 4 +# FIXME: subfco. 2, 3, 4 + +# CHECK-BE: adde 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x14] +# CHECK-LE: adde 2, 3, 4 # encoding: [0x14,0x21,0x43,0x7c] + adde 2, 3, 4 +# CHECK-BE: adde. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x15] +# CHECK-LE: adde. 2, 3, 4 # encoding: [0x15,0x21,0x43,0x7c] + adde. 2, 3, 4 +# FIXME: addeo 2, 3, 4 +# FIXME: addeo. 2, 3, 4 +# CHECK-BE: subfe 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x10] +# CHECK-LE: subfe 2, 3, 4 # encoding: [0x10,0x21,0x43,0x7c] + subfe 2, 3, 4 +# CHECK-BE: subfe. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x11] +# CHECK-LE: subfe. 2, 3, 4 # encoding: [0x11,0x21,0x43,0x7c] + subfe. 2, 3, 4 +# FIXME: subfeo 2, 3, 4 +# FIXME: subfeo. 2, 3, 4 + +# CHECK-BE: addme 2, 3 # encoding: [0x7c,0x43,0x01,0xd4] +# CHECK-LE: addme 2, 3 # encoding: [0xd4,0x01,0x43,0x7c] + addme 2, 3 +# CHECK-BE: addme. 2, 3 # encoding: [0x7c,0x43,0x01,0xd5] +# CHECK-LE: addme. 2, 3 # encoding: [0xd5,0x01,0x43,0x7c] + addme. 2, 3 +# FIXME: addmeo 2, 3 +# FIXME: addmeo. 2, 3 +# CHECK-BE: subfme 2, 3 # encoding: [0x7c,0x43,0x01,0xd0] +# CHECK-LE: subfme 2, 3 # encoding: [0xd0,0x01,0x43,0x7c] + subfme 2, 3 +# CHECK-BE: subfme. 2, 3 # encoding: [0x7c,0x43,0x01,0xd1] +# CHECK-LE: subfme. 2, 3 # encoding: [0xd1,0x01,0x43,0x7c] + subfme. 2, 3 +# FIXME: subfmeo 2, 3 +# FIXME: subfmeo. 2, 3 + +# CHECK-BE: addze 2, 3 # encoding: [0x7c,0x43,0x01,0x94] +# CHECK-LE: addze 2, 3 # encoding: [0x94,0x01,0x43,0x7c] + addze 2, 3 +# CHECK-BE: addze. 2, 3 # encoding: [0x7c,0x43,0x01,0x95] +# CHECK-LE: addze. 2, 3 # encoding: [0x95,0x01,0x43,0x7c] + addze. 2, 3 +# FIXME: addzeo 2, 3 +# FIXME: addzeo. 2, 3 +# CHECK-BE: subfze 2, 3 # encoding: [0x7c,0x43,0x01,0x90] +# CHECK-LE: subfze 2, 3 # encoding: [0x90,0x01,0x43,0x7c] + subfze 2, 3 +# CHECK-BE: subfze. 2, 3 # encoding: [0x7c,0x43,0x01,0x91] +# CHECK-LE: subfze. 2, 3 # encoding: [0x91,0x01,0x43,0x7c] + subfze. 2, 3 +# FIXME: subfzeo 2, 3 +# FIXME: subfzeo. 2, 3 + +# CHECK-BE: neg 2, 3 # encoding: [0x7c,0x43,0x00,0xd0] +# CHECK-LE: neg 2, 3 # encoding: [0xd0,0x00,0x43,0x7c] + neg 2, 3 +# CHECK-BE: neg. 2, 3 # encoding: [0x7c,0x43,0x00,0xd1] +# CHECK-LE: neg. 2, 3 # encoding: [0xd1,0x00,0x43,0x7c] + neg. 2, 3 +# FIXME: nego 2, 3 +# FIXME: nego. 2, 3 + +# CHECK-BE: mulli 2, 3, 128 # encoding: [0x1c,0x43,0x00,0x80] +# CHECK-LE: mulli 2, 3, 128 # encoding: [0x80,0x00,0x43,0x1c] + mulli 2, 3, 128 +# CHECK-BE: mulhw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x96] +# CHECK-LE: mulhw 2, 3, 4 # encoding: [0x96,0x20,0x43,0x7c] + mulhw 2, 3, 4 +# CHECK-BE: mulhw. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x97] +# CHECK-LE: mulhw. 2, 3, 4 # encoding: [0x97,0x20,0x43,0x7c] + mulhw. 2, 3, 4 +# CHECK-BE: mullw 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd6] +# CHECK-LE: mullw 2, 3, 4 # encoding: [0xd6,0x21,0x43,0x7c] + mullw 2, 3, 4 +# CHECK-BE: mullw. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd7] +# CHECK-LE: mullw. 2, 3, 4 # encoding: [0xd7,0x21,0x43,0x7c] + mullw. 2, 3, 4 +# FIXME: mullwo 2, 3, 4 +# FIXME: mullwo. 2, 3, 4 +# CHECK-BE: mulhwu 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x16] +# CHECK-LE: mulhwu 2, 3, 4 # encoding: [0x16,0x20,0x43,0x7c] + mulhwu 2, 3, 4 +# CHECK-BE: mulhwu. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x17] +# CHECK-LE: mulhwu. 2, 3, 4 # encoding: [0x17,0x20,0x43,0x7c] + mulhwu. 2, 3, 4 + +# CHECK-BE: divw 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd6] +# CHECK-LE: divw 2, 3, 4 # encoding: [0xd6,0x23,0x43,0x7c] + divw 2, 3, 4 +# CHECK-BE: divw. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd7] +# CHECK-LE: divw. 2, 3, 4 # encoding: [0xd7,0x23,0x43,0x7c] + divw. 2, 3, 4 +# FIXME: divwo 2, 3, 4 +# FIXME: divwo. 2, 3, 4 +# CHECK-BE: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96] +# CHECK-LE: divwu 2, 3, 4 # encoding: [0x96,0x23,0x43,0x7c] + divwu 2, 3, 4 +# CHECK-BE: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97] +# CHECK-LE: divwu. 2, 3, 4 # encoding: [0x97,0x23,0x43,0x7c] + divwu. 2, 3, 4 +# FIXME: divwuo 2, 3, 4 +# FIXME: divwuo. 2, 3, 4 +# FIXME: divwe 2, 3, 4 +# FIXME: divwe. 2, 3, 4 +# FIXME: divweo 2, 3, 4 +# FIXME: divweo. 2, 3, 4 +# FIXME: divweu 2, 3, 4 +# FIXME: divweu. 2, 3, 4 +# FIXME: divweuo 2, 3, 4 +# FIXME: divweuo. 2, 3, 4 + +# CHECK-BE: mulld 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd2] +# CHECK-LE: mulld 2, 3, 4 # encoding: [0xd2,0x21,0x43,0x7c] + mulld 2, 3, 4 +# CHECK-BE: mulld. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd3] +# CHECK-LE: mulld. 2, 3, 4 # encoding: [0xd3,0x21,0x43,0x7c] + mulld. 2, 3, 4 +# FIXME: mulldo 2, 3, 4 +# FIXME: mulldo. 2, 3, 4 +# CHECK-BE: mulhd 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x92] +# CHECK-LE: mulhd 2, 3, 4 # encoding: [0x92,0x20,0x43,0x7c] + mulhd 2, 3, 4 +# CHECK-BE: mulhd. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x93] +# CHECK-LE: mulhd. 2, 3, 4 # encoding: [0x93,0x20,0x43,0x7c] + mulhd. 2, 3, 4 +# CHECK-BE: mulhdu 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x12] +# CHECK-LE: mulhdu 2, 3, 4 # encoding: [0x12,0x20,0x43,0x7c] + mulhdu 2, 3, 4 +# CHECK-BE: mulhdu. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x13] +# CHECK-LE: mulhdu. 2, 3, 4 # encoding: [0x13,0x20,0x43,0x7c] + mulhdu. 2, 3, 4 + +# CHECK-BE: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2] +# CHECK-LE: divd 2, 3, 4 # encoding: [0xd2,0x23,0x43,0x7c] + divd 2, 3, 4 +# CHECK-BE: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3] +# CHECK-LE: divd. 2, 3, 4 # encoding: [0xd3,0x23,0x43,0x7c] + divd. 2, 3, 4 +# FIXME: divdo 2, 3, 4 +# FIXME: divdo. 2, 3, 4 +# CHECK-BE: divdu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x92] +# CHECK-LE: divdu 2, 3, 4 # encoding: [0x92,0x23,0x43,0x7c] + divdu 2, 3, 4 +# CHECK-BE: divdu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x93] +# CHECK-LE: divdu. 2, 3, 4 # encoding: [0x93,0x23,0x43,0x7c] + divdu. 2, 3, 4 +# FIXME: divduo 2, 3, 4 +# FIXME: divduo. 2, 3, 4 +# FIXME: divde 2, 3, 4 +# FIXME: divde. 2, 3, 4 +# FIXME: divdeo 2, 3, 4 +# FIXME: divdeo. 2, 3, 4 +# FIXME: divdeu 2, 3, 4 +# FIXME: divdeu. 2, 3, 4 +# FIXME: divdeuo 2, 3, 4 +# FIXME: divdeuo. 2, 3, 4 # Fixed-point compare instructions -# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] - cmpi 2, 1, 3, 128 -# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] - cmp 2, 1, 3, 4 -# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] - cmpli 2, 1, 3, 128 -# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] - cmpl 2, 1, 3, 4 - -# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] - cmpi 2, 0, 3, 128 -# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] - cmp 2, 0, 3, 4 -# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] - cmpli 2, 0, 3, 128 -# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] - cmpl 2, 0, 3, 4 +# CHECK-BE: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] +# CHECK-LE: cmpdi 2, 3, 128 # encoding: [0x80,0x00,0x23,0x2d] + cmpi 2, 1, 3, 128 +# CHECK-BE: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] +# CHECK-LE: cmpd 2, 3, 4 # encoding: [0x00,0x20,0x23,0x7d] + cmp 2, 1, 3, 4 +# CHECK-BE: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] +# CHECK-LE: cmpldi 2, 3, 128 # encoding: [0x80,0x00,0x23,0x29] + cmpli 2, 1, 3, 128 +# CHECK-BE: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] +# CHECK-LE: cmpld 2, 3, 4 # encoding: [0x40,0x20,0x23,0x7d] + cmpl 2, 1, 3, 4 + +# CHECK-BE: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] +# CHECK-LE: cmpwi 2, 3, 128 # encoding: [0x80,0x00,0x03,0x2d] + cmpi 2, 0, 3, 128 +# CHECK-BE: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] +# CHECK-LE: cmpw 2, 3, 4 # encoding: [0x00,0x20,0x03,0x7d] + cmp 2, 0, 3, 4 +# CHECK-BE: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] +# CHECK-LE: cmplwi 2, 3, 128 # encoding: [0x80,0x00,0x03,0x29] + cmpli 2, 0, 3, 128 +# CHECK-BE: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] +# CHECK-LE: cmplw 2, 3, 4 # encoding: [0x40,0x20,0x03,0x7d] + cmpl 2, 0, 3, 4 # Fixed-point trap instructions -# CHECK: twi 2, 3, 4 # encoding: [0x0c,0x43,0x00,0x04] - twi 2, 3, 4 -# CHECK: tw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x08] - tw 2, 3, 4 -# CHECK: tdi 2, 3, 4 # encoding: [0x08,0x43,0x00,0x04] - tdi 2, 3, 4 -# CHECK: td 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x88] - td 2, 3, 4 +# CHECK-BE: twi 2, 3, 4 # encoding: [0x0c,0x43,0x00,0x04] +# CHECK-LE: twi 2, 3, 4 # encoding: [0x04,0x00,0x43,0x0c] + twi 2, 3, 4 +# CHECK-BE: tw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x08] +# CHECK-LE: tw 2, 3, 4 # encoding: [0x08,0x20,0x43,0x7c] + tw 2, 3, 4 +# CHECK-BE: tdi 2, 3, 4 # encoding: [0x08,0x43,0x00,0x04] +# CHECK-LE: tdi 2, 3, 4 # encoding: [0x04,0x00,0x43,0x08] + tdi 2, 3, 4 +# CHECK-BE: td 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x88] +# CHECK-LE: td 2, 3, 4 # encoding: [0x88,0x20,0x43,0x7c] + td 2, 3, 4 # Fixed-point select -# CHECK: isel 2, 3, 4, 5 # encoding: [0x7c,0x43,0x21,0x5e] - isel 2, 3, 4, 5 +# CHECK-BE: isel 2, 3, 4, 5 # encoding: [0x7c,0x43,0x21,0x5e] +# CHECK-LE: isel 2, 3, 4, 5 # encoding: [0x5e,0x21,0x43,0x7c] + isel 2, 3, 4, 5 # Fixed-point logical instructions -# CHECK: andi. 2, 3, 128 # encoding: [0x70,0x62,0x00,0x80] - andi. 2, 3, 128 -# CHECK: andis. 2, 3, 128 # encoding: [0x74,0x62,0x00,0x80] - andis. 2, 3, 128 -# CHECK: ori 2, 3, 128 # encoding: [0x60,0x62,0x00,0x80] - ori 2, 3, 128 -# CHECK: oris 2, 3, 128 # encoding: [0x64,0x62,0x00,0x80] - oris 2, 3, 128 -# CHECK: xori 2, 3, 128 # encoding: [0x68,0x62,0x00,0x80] - xori 2, 3, 128 -# CHECK: xoris 2, 3, 128 # encoding: [0x6c,0x62,0x00,0x80] - xoris 2, 3, 128 -# CHECK: and 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x38] - and 2, 3, 4 -# CHECK: and. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x39] - and. 2, 3, 4 -# CHECK: xor 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x78] - xor 2, 3, 4 -# CHECK: xor. 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x79] - xor. 2, 3, 4 -# CHECK: nand 2, 3, 4 # encoding: [0x7c,0x62,0x23,0xb8] - nand 2, 3, 4 -# CHECK: nand. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0xb9] - nand. 2, 3, 4 -# CHECK: or 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x78] - or 2, 3, 4 -# CHECK: or. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x79] - or. 2, 3, 4 -# CHECK: nor 2, 3, 4 # encoding: [0x7c,0x62,0x20,0xf8] - nor 2, 3, 4 -# CHECK: nor. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0xf9] - nor. 2, 3, 4 -# CHECK: eqv 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x38] - eqv 2, 3, 4 -# CHECK: eqv. 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x39] - eqv. 2, 3, 4 -# CHECK: andc 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x78] - andc 2, 3, 4 -# CHECK: andc. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x79] - andc. 2, 3, 4 -# CHECK: orc 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x38] - orc 2, 3, 4 -# CHECK: orc. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x39] - orc. 2, 3, 4 - -# CHECK: extsb 2, 3 # encoding: [0x7c,0x62,0x07,0x74] - extsb 2, 3 -# CHECK: extsb. 2, 3 # encoding: [0x7c,0x62,0x07,0x75] - extsb. 2, 3 -# CHECK: extsh 2, 3 # encoding: [0x7c,0x62,0x07,0x34] - extsh 2, 3 -# CHECK: extsh. 2, 3 # encoding: [0x7c,0x62,0x07,0x35] - extsh. 2, 3 - -# CHECK: cntlzw 2, 3 # encoding: [0x7c,0x62,0x00,0x34] - cntlzw 2, 3 -# CHECK: cntlzw. 2, 3 # encoding: [0x7c,0x62,0x00,0x35] - cntlzw. 2, 3 -# FIXME: cmpb 2, 3, 4 -# FIXME: popcntb 2, 3 -# CHECK: popcntw 2, 3 # encoding: [0x7c,0x62,0x02,0xf4] - popcntw 2, 3 -# FIXME: prtyd 2, 3 -# FIXME: prtyw 2, 3 - -# CHECK: extsw 2, 3 # encoding: [0x7c,0x62,0x07,0xb4] - extsw 2, 3 -# CHECK: extsw. 2, 3 # encoding: [0x7c,0x62,0x07,0xb5] - extsw. 2, 3 - -# CHECK: cntlzd 2, 3 # encoding: [0x7c,0x62,0x00,0x74] - cntlzd 2, 3 -# CHECK: cntlzd. 2, 3 # encoding: [0x7c,0x62,0x00,0x75] - cntlzd. 2, 3 -# CHECK: popcntd 2, 3 # encoding: [0x7c,0x62,0x03,0xf4] - popcntd 2, 3 -# FIXME: bpermd 2, 3, 4 +# CHECK-BE: andi. 2, 3, 128 # encoding: [0x70,0x62,0x00,0x80] +# CHECK-LE: andi. 2, 3, 128 # encoding: [0x80,0x00,0x62,0x70] + andi. 2, 3, 128 +# CHECK-BE: andis. 2, 3, 128 # encoding: [0x74,0x62,0x00,0x80] +# CHECK-LE: andis. 2, 3, 128 # encoding: [0x80,0x00,0x62,0x74] + andis. 2, 3, 128 +# CHECK-BE: ori 2, 3, 128 # encoding: [0x60,0x62,0x00,0x80] +# CHECK-LE: ori 2, 3, 128 # encoding: [0x80,0x00,0x62,0x60] + ori 2, 3, 128 +# CHECK-BE: oris 2, 3, 128 # encoding: [0x64,0x62,0x00,0x80] +# CHECK-LE: oris 2, 3, 128 # encoding: [0x80,0x00,0x62,0x64] + oris 2, 3, 128 +# CHECK-BE: xori 2, 3, 128 # encoding: [0x68,0x62,0x00,0x80] +# CHECK-LE: xori 2, 3, 128 # encoding: [0x80,0x00,0x62,0x68] + xori 2, 3, 128 +# CHECK-BE: xoris 2, 3, 128 # encoding: [0x6c,0x62,0x00,0x80] +# CHECK-LE: xoris 2, 3, 128 # encoding: [0x80,0x00,0x62,0x6c] + xoris 2, 3, 128 +# CHECK-BE: and 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x38] +# CHECK-LE: and 2, 3, 4 # encoding: [0x38,0x20,0x62,0x7c] + and 2, 3, 4 +# CHECK-BE: and. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x39] +# CHECK-LE: and. 2, 3, 4 # encoding: [0x39,0x20,0x62,0x7c] + and. 2, 3, 4 +# CHECK-BE: xor 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x78] +# CHECK-LE: xor 2, 3, 4 # encoding: [0x78,0x22,0x62,0x7c] + xor 2, 3, 4 +# CHECK-BE: xor. 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x79] +# CHECK-LE: xor. 2, 3, 4 # encoding: [0x79,0x22,0x62,0x7c] + xor. 2, 3, 4 +# CHECK-BE: nand 2, 3, 4 # encoding: [0x7c,0x62,0x23,0xb8] +# CHECK-LE: nand 2, 3, 4 # encoding: [0xb8,0x23,0x62,0x7c] + nand 2, 3, 4 +# CHECK-BE: nand. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0xb9] +# CHECK-LE: nand. 2, 3, 4 # encoding: [0xb9,0x23,0x62,0x7c] + nand. 2, 3, 4 +# CHECK-BE: or 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x78] +# CHECK-LE: or 2, 3, 4 # encoding: [0x78,0x23,0x62,0x7c] + or 2, 3, 4 +# CHECK-BE: or. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x79] +# CHECK-LE: or. 2, 3, 4 # encoding: [0x79,0x23,0x62,0x7c] + or. 2, 3, 4 +# CHECK-BE: nor 2, 3, 4 # encoding: [0x7c,0x62,0x20,0xf8] +# CHECK-LE: nor 2, 3, 4 # encoding: [0xf8,0x20,0x62,0x7c] + nor 2, 3, 4 +# CHECK-BE: nor. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0xf9] +# CHECK-LE: nor. 2, 3, 4 # encoding: [0xf9,0x20,0x62,0x7c] + nor. 2, 3, 4 +# CHECK-BE: eqv 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x38] +# CHECK-LE: eqv 2, 3, 4 # encoding: [0x38,0x22,0x62,0x7c] + eqv 2, 3, 4 +# CHECK-BE: eqv. 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x39] +# CHECK-LE: eqv. 2, 3, 4 # encoding: [0x39,0x22,0x62,0x7c] + eqv. 2, 3, 4 +# CHECK-BE: andc 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x78] +# CHECK-LE: andc 2, 3, 4 # encoding: [0x78,0x20,0x62,0x7c] + andc 2, 3, 4 +# CHECK-BE: andc. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x79] +# CHECK-LE: andc. 2, 3, 4 # encoding: [0x79,0x20,0x62,0x7c] + andc. 2, 3, 4 +# CHECK-BE: orc 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x38] +# CHECK-LE: orc 2, 3, 4 # encoding: [0x38,0x23,0x62,0x7c] + orc 2, 3, 4 +# CHECK-BE: orc. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x39] +# CHECK-LE: orc. 2, 3, 4 # encoding: [0x39,0x23,0x62,0x7c] + orc. 2, 3, 4 + +# CHECK-BE: extsb 2, 3 # encoding: [0x7c,0x62,0x07,0x74] +# CHECK-LE: extsb 2, 3 # encoding: [0x74,0x07,0x62,0x7c] + extsb 2, 3 +# CHECK-BE: extsb. 2, 3 # encoding: [0x7c,0x62,0x07,0x75] +# CHECK-LE: extsb. 2, 3 # encoding: [0x75,0x07,0x62,0x7c] + extsb. 2, 3 +# CHECK-BE: extsh 2, 3 # encoding: [0x7c,0x62,0x07,0x34] +# CHECK-LE: extsh 2, 3 # encoding: [0x34,0x07,0x62,0x7c] + extsh 2, 3 +# CHECK-BE: extsh. 2, 3 # encoding: [0x7c,0x62,0x07,0x35] +# CHECK-LE: extsh. 2, 3 # encoding: [0x35,0x07,0x62,0x7c] + extsh. 2, 3 + +# CHECK-BE: cntlzw 2, 3 # encoding: [0x7c,0x62,0x00,0x34] +# CHECK-LE: cntlzw 2, 3 # encoding: [0x34,0x00,0x62,0x7c] + cntlzw 2, 3 +# CHECK-BE: cntlzw. 2, 3 # encoding: [0x7c,0x62,0x00,0x35] +# CHECK-LE: cntlzw. 2, 3 # encoding: [0x35,0x00,0x62,0x7c] + cntlzw. 2, 3 +# FIXME: cmpb 2, 3, 4 +# FIXME: popcntb 2, 3 +# CHECK-BE: popcntw 2, 3 # encoding: [0x7c,0x62,0x02,0xf4] +# CHECK-LE: popcntw 2, 3 # encoding: [0xf4,0x02,0x62,0x7c] + popcntw 2, 3 +# FIXME: prtyd 2, 3 +# FIXME: prtyw 2, 3 + +# CHECK-BE: extsw 2, 3 # encoding: [0x7c,0x62,0x07,0xb4] +# CHECK-LE: extsw 2, 3 # encoding: [0xb4,0x07,0x62,0x7c] + extsw 2, 3 +# CHECK-BE: extsw. 2, 3 # encoding: [0x7c,0x62,0x07,0xb5] +# CHECK-LE: extsw. 2, 3 # encoding: [0xb5,0x07,0x62,0x7c] + extsw. 2, 3 + +# CHECK-BE: cntlzd 2, 3 # encoding: [0x7c,0x62,0x00,0x74] +# CHECK-LE: cntlzd 2, 3 # encoding: [0x74,0x00,0x62,0x7c] + cntlzd 2, 3 +# CHECK-BE: cntlzd. 2, 3 # encoding: [0x7c,0x62,0x00,0x75] +# CHECK-LE: cntlzd. 2, 3 # encoding: [0x75,0x00,0x62,0x7c] + cntlzd. 2, 3 +# CHECK-BE: popcntd 2, 3 # encoding: [0x7c,0x62,0x03,0xf4] +# CHECK-LE: popcntd 2, 3 # encoding: [0xf4,0x03,0x62,0x7c] + popcntd 2, 3 +# FIXME: bpermd 2, 3, 4 # Fixed-point rotate and shift instructions -# CHECK: rlwinm 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4c] - rlwinm 2, 3, 4, 5, 6 -# CHECK: rlwinm. 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4d] - rlwinm. 2, 3, 4, 5, 6 -# CHECK: rlwnm 2, 3, 4, 5, 6 # encoding: [0x5c,0x62,0x21,0x4c] - rlwnm 2, 3, 4, 5, 6 -# CHECK: rlwnm. 2, 3, 4, 5, 6 # encoding: [0x5c,0x62,0x21,0x4d] - rlwnm. 2, 3, 4, 5, 6 -# CHECK: rlwimi 2, 3, 4, 5, 6 # encoding: [0x50,0x62,0x21,0x4c] - rlwimi 2, 3, 4, 5, 6 -# CHECK: rlwimi. 2, 3, 4, 5, 6 # encoding: [0x50,0x62,0x21,0x4d] - rlwimi. 2, 3, 4, 5, 6 -# CHECK: rldicl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x40] - rldicl 2, 3, 4, 5 -# CHECK: rldicl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x41] - rldicl. 2, 3, 4, 5 -# CHECK: rldicr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x44] - rldicr 2, 3, 4, 5 -# CHECK: rldicr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x45] - rldicr. 2, 3, 4, 5 -# CHECK: rldic 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x48] - rldic 2, 3, 4, 5 -# CHECK: rldic. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x49] - rldic. 2, 3, 4, 5 -# CHECK: rldcl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x50] - rldcl 2, 3, 4, 5 -# CHECK: rldcl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x51] - rldcl. 2, 3, 4, 5 -# CHECK: rldcr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x52] - rldcr 2, 3, 4, 5 -# CHECK: rldcr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x53] - rldcr. 2, 3, 4, 5 -# CHECK: rldimi 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4c] - rldimi 2, 3, 4, 5 -# CHECK: rldimi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4d] - rldimi. 2, 3, 4, 5 - -# CHECK: slw 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x30] - slw 2, 3, 4 -# CHECK: slw. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x31] - slw. 2, 3, 4 -# CHECK: srw 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x30] - srw 2, 3, 4 -# CHECK: srw. 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x31] - srw. 2, 3, 4 -# CHECK: srawi 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x70] - srawi 2, 3, 4 -# CHECK: srawi. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x71] - srawi. 2, 3, 4 -# CHECK: sraw 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x30] - sraw 2, 3, 4 -# CHECK: sraw. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x31] - sraw. 2, 3, 4 -# CHECK: sld 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x36] - sld 2, 3, 4 -# CHECK: sld. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x37] - sld. 2, 3, 4 -# CHECK: srd 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x36] - srd 2, 3, 4 -# CHECK: srd. 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x37] - srd. 2, 3, 4 -# CHECK: sradi 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x74] - sradi 2, 3, 4 -# CHECK: sradi. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x75] - sradi. 2, 3, 4 -# CHECK: srad 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x34] - srad 2, 3, 4 -# CHECK: srad. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x35] - srad. 2, 3, 4 +# CHECK-BE: rlwinm 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4c] +# CHECK-LE: rlwinm 2, 3, 4, 5, 6 # encoding: [0x4c,0x21,0x62,0x54] + rlwinm 2, 3, 4, 5, 6 +# CHECK-BE: rlwinm. 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4d] +# CHECK-LE: rlwinm. 2, 3, 4, 5, 6 # encoding: [0x4d,0x21,0x62,0x54] + rlwinm. 2, 3, 4, 5, 6 +# CHECK-BE: rlwnm 2, 3, 4, 5, 6 # encoding: [0x5c,0x62,0x21,0x4c] +# CHECK-LE: rlwnm 2, 3, 4, 5, 6 # encoding: [0x4c,0x21,0x62,0x5c] + rlwnm 2, 3, 4, 5, 6 +# CHECK-BE: rlwnm. 2, 3, 4, 5, 6 # encoding: [0x5c,0x62,0x21,0x4d] +# CHECK-LE: rlwnm. 2, 3, 4, 5, 6 # encoding: [0x4d,0x21,0x62,0x5c] + rlwnm. 2, 3, 4, 5, 6 +# CHECK-BE: rlwimi 2, 3, 4, 5, 6 # encoding: [0x50,0x62,0x21,0x4c] +# CHECK-LE: rlwimi 2, 3, 4, 5, 6 # encoding: [0x4c,0x21,0x62,0x50] + rlwimi 2, 3, 4, 5, 6 +# CHECK-BE: rlwimi. 2, 3, 4, 5, 6 # encoding: [0x50,0x62,0x21,0x4d] +# CHECK-LE: rlwimi. 2, 3, 4, 5, 6 # encoding: [0x4d,0x21,0x62,0x50] + rlwimi. 2, 3, 4, 5, 6 +# CHECK-BE: rldicl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x40] +# CHECK-LE: rldicl 2, 3, 4, 5 # encoding: [0x40,0x21,0x62,0x78] + rldicl 2, 3, 4, 5 +# CHECK-BE: rldicl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x41] +# CHECK-LE: rldicl. 2, 3, 4, 5 # encoding: [0x41,0x21,0x62,0x78] + rldicl. 2, 3, 4, 5 +# CHECK-BE: rldicr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x44] +# CHECK-LE: rldicr 2, 3, 4, 5 # encoding: [0x44,0x21,0x62,0x78] + rldicr 2, 3, 4, 5 +# CHECK-BE: rldicr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x45] +# CHECK-LE: rldicr. 2, 3, 4, 5 # encoding: [0x45,0x21,0x62,0x78] + rldicr. 2, 3, 4, 5 +# CHECK-BE: rldic 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x48] +# CHECK-LE: rldic 2, 3, 4, 5 # encoding: [0x48,0x21,0x62,0x78] + rldic 2, 3, 4, 5 +# CHECK-BE: rldic. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x49] +# CHECK-LE: rldic. 2, 3, 4, 5 # encoding: [0x49,0x21,0x62,0x78] + rldic. 2, 3, 4, 5 +# CHECK-BE: rldcl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x50] +# CHECK-LE: rldcl 2, 3, 4, 5 # encoding: [0x50,0x21,0x62,0x78] + rldcl 2, 3, 4, 5 +# CHECK-BE: rldcl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x51] +# CHECK-LE: rldcl. 2, 3, 4, 5 # encoding: [0x51,0x21,0x62,0x78] + rldcl. 2, 3, 4, 5 +# CHECK-BE: rldcr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x52] +# CHECK-LE: rldcr 2, 3, 4, 5 # encoding: [0x52,0x21,0x62,0x78] + rldcr 2, 3, 4, 5 +# CHECK-BE: rldcr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x53] +# CHECK-LE: rldcr. 2, 3, 4, 5 # encoding: [0x53,0x21,0x62,0x78] + rldcr. 2, 3, 4, 5 +# CHECK-BE: rldimi 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4c] +# CHECK-LE: rldimi 2, 3, 4, 5 # encoding: [0x4c,0x21,0x62,0x78] + rldimi 2, 3, 4, 5 +# CHECK-BE: rldimi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4d] +# CHECK-LE: rldimi. 2, 3, 4, 5 # encoding: [0x4d,0x21,0x62,0x78] + rldimi. 2, 3, 4, 5 + +# CHECK-BE: slw 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x30] +# CHECK-LE: slw 2, 3, 4 # encoding: [0x30,0x20,0x62,0x7c] + slw 2, 3, 4 +# CHECK-BE: slw. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x31] +# CHECK-LE: slw. 2, 3, 4 # encoding: [0x31,0x20,0x62,0x7c] + slw. 2, 3, 4 +# CHECK-BE: srw 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x30] +# CHECK-LE: srw 2, 3, 4 # encoding: [0x30,0x24,0x62,0x7c] + srw 2, 3, 4 +# CHECK-BE: srw. 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x31] +# CHECK-LE: srw. 2, 3, 4 # encoding: [0x31,0x24,0x62,0x7c] + srw. 2, 3, 4 +# CHECK-BE: srawi 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x70] +# CHECK-LE: srawi 2, 3, 4 # encoding: [0x70,0x26,0x62,0x7c] + srawi 2, 3, 4 +# CHECK-BE: srawi. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x71] +# CHECK-LE: srawi. 2, 3, 4 # encoding: [0x71,0x26,0x62,0x7c] + srawi. 2, 3, 4 +# CHECK-BE: sraw 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x30] +# CHECK-LE: sraw 2, 3, 4 # encoding: [0x30,0x26,0x62,0x7c] + sraw 2, 3, 4 +# CHECK-BE: sraw. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x31] +# CHECK-LE: sraw. 2, 3, 4 # encoding: [0x31,0x26,0x62,0x7c] + sraw. 2, 3, 4 +# CHECK-BE: sld 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x36] +# CHECK-LE: sld 2, 3, 4 # encoding: [0x36,0x20,0x62,0x7c] + sld 2, 3, 4 +# CHECK-BE: sld. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x37] +# CHECK-LE: sld. 2, 3, 4 # encoding: [0x37,0x20,0x62,0x7c] + sld. 2, 3, 4 +# CHECK-BE: srd 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x36] +# CHECK-LE: srd 2, 3, 4 # encoding: [0x36,0x24,0x62,0x7c] + srd 2, 3, 4 +# CHECK-BE: srd. 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x37] +# CHECK-LE: srd. 2, 3, 4 # encoding: [0x37,0x24,0x62,0x7c] + srd. 2, 3, 4 +# CHECK-BE: sradi 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x74] +# CHECK-LE: sradi 2, 3, 4 # encoding: [0x74,0x26,0x62,0x7c] + sradi 2, 3, 4 +# CHECK-BE: sradi. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x75] +# CHECK-LE: sradi. 2, 3, 4 # encoding: [0x75,0x26,0x62,0x7c] + sradi. 2, 3, 4 +# CHECK-BE: srad 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x34] +# CHECK-LE: srad 2, 3, 4 # encoding: [0x34,0x26,0x62,0x7c] + srad 2, 3, 4 +# CHECK-BE: srad. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x35] +# CHECK-LE: srad. 2, 3, 4 # encoding: [0x35,0x26,0x62,0x7c] + srad. 2, 3, 4 # FIXME: BCD assist instructions # Move to/from system register instructions -# CHECK: mtspr 600, 2 # encoding: [0x7c,0x58,0x93,0xa6] - mtspr 600, 2 -# CHECK: mfspr 2, 600 # encoding: [0x7c,0x58,0x92,0xa6] - mfspr 2, 600 -# CHECK: mtcrf 123, 2 # encoding: [0x7c,0x47,0xb1,0x20] - mtcrf 123, 2 -# CHECK: mfcr 2 # encoding: [0x7c,0x40,0x00,0x26] - mfcr 2 -# CHECK: mtocrf 16, 2 # encoding: [0x7c,0x51,0x01,0x20] - mtocrf 16, 2 -# CHECK: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26] - mfocrf 16, 8 +# CHECK-BE: mtspr 600, 2 # encoding: [0x7c,0x58,0x93,0xa6] +# CHECK-LE: mtspr 600, 2 # encoding: [0xa6,0x93,0x58,0x7c] + mtspr 600, 2 +# CHECK-BE: mfspr 2, 600 # encoding: [0x7c,0x58,0x92,0xa6] +# CHECK-LE: mfspr 2, 600 # encoding: [0xa6,0x92,0x58,0x7c] + mfspr 2, 600 +# CHECK-BE: mtcrf 123, 2 # encoding: [0x7c,0x47,0xb1,0x20] +# CHECK-LE: mtcrf 123, 2 # encoding: [0x20,0xb1,0x47,0x7c] + mtcrf 123, 2 +# CHECK-BE: mfcr 2 # encoding: [0x7c,0x40,0x00,0x26] +# CHECK-LE: mfcr 2 # encoding: [0x26,0x00,0x40,0x7c] + mfcr 2 +# CHECK-BE: mtocrf 16, 2 # encoding: [0x7c,0x51,0x01,0x20] +# CHECK-LE: mtocrf 16, 2 # encoding: [0x20,0x01,0x51,0x7c] + mtocrf 16, 2 +# CHECK-BE: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26] +# CHECK-LE: mfocrf 16, 8 # encoding: [0x26,0x80,0x10,0x7e] + mfocrf 16, 8 Index: llvm-suse/test/MC/PowerPC/ppc64-errors.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-errors.s +++ llvm-suse/test/MC/PowerPC/ppc64-errors.s @@ -1,6 +1,8 @@ # RUN: not llvm-mc -triple powerpc64-unknown-unknown < %s 2> %t # RUN: FileCheck < %t %s +# RUN: not llvm-mc -triple powerpc64le-unknown-unknown < %s 2> %t +# RUN: FileCheck < %t %s # Register operands Index: llvm-suse/test/MC/PowerPC/ppc64-fixup-apply.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-fixup-apply.s +++ llvm-suse/test/MC/PowerPC/ppc64-fixup-apply.s @@ -1,6 +1,8 @@ # RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ -# RUN: llvm-readobj -s -sd | FileCheck %s +# RUN: llvm-readobj -s -sd | FileCheck -check-prefix=CHECK -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -s -sd | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LE %s # This checks that fixups that can be resolved within the same # object file are applied correctly. @@ -72,10 +74,14 @@ addis 1, 1, target7@highesta # CHECK-NEXT: AddressAlignment: 4 # CHECK-NEXT: EntrySize: 0 # CHECK-NEXT: SectionData ( -# CHECK-NEXT: 0000: 38211234 3C211234 38215678 3C211234 -# CHECK-NEXT: 0010: 38214444 3C211111 38218001 3C211001 -# CHECK-NEXT: 0020: 38210008 3C210000 38214321 3C214321 -# CHECK-NEXT: 0030: 3821FFFF 3C211234 38210000 3C211235 +# CHECK-BE-NEXT: 0000: 38211234 3C211234 38215678 3C211234 +# CHECK-LE-NEXT: 0000: 34122138 3412213C 78562138 3412213C +# CHECK-BE-NEXT: 0010: 38214444 3C211111 38218001 3C211001 +# CHECK-LE-NEXT: 0010: 44442138 1111213C 01802138 0110213C +# CHECK-BE-NEXT: 0020: 38210008 3C210000 38214321 3C214321 +# CHECK-LE-NEXT: 0020: 08002138 0000213C 21432138 2143213C +# CHECK-BE-NEXT: 0030: 3821FFFF 3C211234 38210000 3C211235 +# CHECK-LE-NEXT: 0030: FFFF2138 3412213C 00002138 3512213C # CHECK-NEXT: ) # CHECK-NEXT: } @@ -94,7 +100,8 @@ addis 1, 1, target7@highesta # CHECK-NEXT: AddressAlignment: 4 # CHECK-NEXT: EntrySize: 0 # CHECK-NEXT: SectionData ( -# CHECK-NEXT: 0000: 12345678 9ABCDEF0 87654321 BEEF42 +# CHECK-BE-NEXT: 0000: 12345678 9ABCDEF0 87654321 BEEF42 +# CHECK-LE-NEXT: 0000: F0DEBC9A 78563412 21436587 EFBE42 # CHECK-NEXT: ) # CHECK-NEXT: } Index: llvm-suse/test/MC/PowerPC/ppc64-fixup-explicit.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-fixup-explicit.s +++ llvm-suse/test/MC/PowerPC/ppc64-fixup-explicit.s @@ -1,46 +1,70 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ -# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL +# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-BE-REL +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-LE-REL # GOT references must result in explicit relocations # even if the target symbol is local. target: -# CHECK: addi 4, 3, target@GOT # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16 target 0x0 - addi 4, 3, target@got - -# CHECK: ld 1, target@GOT(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_DS target 0x0 - ld 1, target@got(2) - -# CHECK: addis 3, 2, target@got@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HA target 0x0 - addis 3, 2, target@got@ha - -# CHECK: addi 4, 3, target@got@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 - addi 4, 3, target@got@l - -# CHECK: addis 3, 2, target@got@h # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HI target 0x0 - addis 3, 2, target@got@h - -# CHECK: lwz 1, target@got@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 - lwz 1, target@got@l(3) - -# CHECK: ld 1, target@got@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0 - ld 1, target@got@l(3) +# CHECK-BE: addi 4, 3, target@GOT # encoding: [0x38,0x83,A,A] +# CHECK-LE: addi 4, 3, target@GOT # encoding: [A,A,0x83,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@GOT, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16 target 0x0 + addi 4, 3, target@got + +# CHECK-BE: ld 1, target@GOT(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@GOT(2) # encoding: [0bAAAAAA00,A,0x22,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@GOT, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_DS target 0x0 + ld 1, target@got(2) + +# CHECK-BE: addis 3, 2, target@got@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_HA target 0x0 + addis 3, 2, target@got@ha + +# CHECK-BE: addi 4, 3, target@got@l # encoding: [0x38,0x83,A,A] +# CHECK-LE: addi 4, 3, target@got@l # encoding: [A,A,0x83,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_LO target 0x0 + addi 4, 3, target@got@l + +# CHECK-BE: addis 3, 2, target@got@h # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@h # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_HI target 0x0 + addis 3, 2, target@got@h + +# CHECK-BE: lwz 1, target@got@l(3) # encoding: [0x80,0x23,A,A] +# CHECK-LE: lwz 1, target@got@l(3) # encoding: [A,A,0x23,0x80] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_LO target 0x0 + lwz 1, target@got@l(3) + +# CHECK-BE: ld 1, target@got@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@got@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_LO_DS target 0x0 + ld 1, target@got@l(3) Index: llvm-suse/test/MC/PowerPC/ppc64-fixups.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-fixups.s +++ llvm-suse/test/MC/PowerPC/ppc64-fixups.s @@ -1,448 +1,708 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ -# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL - -# CHECK: b target # encoding: [0b010010AA,A,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 target 0x0 - b target - -# CHECK: ba target # encoding: [0b010010AA,A,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR24 target 0x0 - ba target - -# CHECK: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL14 target 0x0 - beq target - -# CHECK: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10] -# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR14 target 0x0 - beqa target - - -# CHECK: li 3, target@l # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 - li 3, target@l - -# CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 - addis 3, 3, target@ha - -# CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 - lis 3, target@ha - -# CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 - addi 4, 3, target@l - -# CHECK: li 3, target@ha # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 - li 3, target@ha - -# CHECK: lis 3, target@l # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 - lis 3, target@l - -# CHECK: li 3, target@h # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 - li 3, target@h - -# CHECK: lis 3, target@h # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 - lis 3, target@h - -# CHECK: li 3, target@higher # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@higher, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHER target 0x0 - li 3, target@higher - -# CHECK: lis 3, target@highest # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@highest, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHEST target 0x0 - lis 3, target@highest - -# CHECK: li 3, target@highera # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@highera, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHERA target 0x0 - li 3, target@highera - -# CHECK: lis 3, target@highesta # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@highesta, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHESTA target 0x0 - lis 3, target@highesta - -# CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 - lwz 1, target@l(3) - -# CHECK: lwz 1, target(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0 - lwz 1, target(3) - -# CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0 - ld 1, target@l(3) - -# CHECK: ld 1, target(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_DS target 0x0 - ld 1, target(3) +# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-BE-REL +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-LE-REL + +# CHECK-BE: b target # encoding: [0b010010AA,A,A,0bAAAAAA00] +# CHECK-LE: b target # encoding: [0bAAAAAA00,A,A,0b010010AA] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 target 0x0 + b target + +# CHECK-BE: ba target # encoding: [0b010010AA,A,A,0bAAAAAA10] +# CHECK-LE: ba target # encoding: [0bAAAAAA10,A,A,0b010010AA] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR24 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR24 target 0x0 + ba target + +# CHECK-BE: beq 0, target # encoding: [0x41,0x82,A,0bAAAAAA00] +# CHECK-LE: beq 0, target # encoding: [0bAAAAAA00,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL14 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL14 target 0x0 + beq target + +# CHECK-BE: beqa 0, target # encoding: [0x41,0x82,A,0bAAAAAA10] +# CHECK-LE: beqa 0, target # encoding: [0bAAAAAA10,A,0x82,0x41] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR14 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR14 target 0x0 + beqa target + + +# CHECK-BE: li 3, target@l # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target@l # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_LO target 0x0 + li 3, target@l + +# CHECK-BE: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A] +# CHECK-LE: addis 3, 3, target@ha # encoding: [A,A,0x63,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HA target 0x0 + addis 3, 3, target@ha + +# CHECK-BE: lis 3, target@ha # encoding: [0x3c,0x60,A,A] +# CHECK-LE: lis 3, target@ha # encoding: [A,A,0x60,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HA target 0x0 + lis 3, target@ha + +# CHECK-BE: addi 4, 3, target@l # encoding: [0x38,0x83,A,A] +# CHECK-LE: addi 4, 3, target@l # encoding: [A,A,0x83,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_LO target 0x0 + addi 4, 3, target@l + +# CHECK-BE: li 3, target@ha # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target@ha # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HA target 0x0 + li 3, target@ha + +# CHECK-BE: lis 3, target@l # encoding: [0x3c,0x60,A,A] +# CHECK-LE: lis 3, target@l # encoding: [A,A,0x60,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_LO target 0x0 + lis 3, target@l + +# CHECK-BE: li 3, target@h # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target@h # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HI target 0x0 + li 3, target@h + +# CHECK-BE: lis 3, target@h # encoding: [0x3c,0x60,A,A] +# CHECK-LE: lis 3, target@h # encoding: [A,A,0x60,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HI target 0x0 + lis 3, target@h + +# CHECK-BE: li 3, target@higher # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target@higher # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@higher, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@higher, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHER target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HIGHER target 0x0 + li 3, target@higher + +# CHECK-BE: lis 3, target@highest # encoding: [0x3c,0x60,A,A] +# CHECK-LE: lis 3, target@highest # encoding: [A,A,0x60,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@highest, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@highest, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHEST target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HIGHEST target 0x0 + lis 3, target@highest + +# CHECK-BE: li 3, target@highera # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target@highera # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@highera, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@highera, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHERA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HIGHERA target 0x0 + li 3, target@highera + +# CHECK-BE: lis 3, target@highesta # encoding: [0x3c,0x60,A,A] +# CHECK-LE: lis 3, target@highesta # encoding: [A,A,0x60,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@highesta, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@highesta, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHESTA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HIGHESTA target 0x0 + lis 3, target@highesta + +# CHECK-BE: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A] +# CHECK-LE: lwz 1, target@l(3) # encoding: [A,A,0x23,0x80] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_LO target 0x0 + lwz 1, target@l(3) + +# CHECK-BE: lwz 1, target(3) # encoding: [0x80,0x23,A,A] +# CHECK-LE: lwz 1, target(3) # encoding: [A,A,0x23,0x80] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16 target 0x0 + lwz 1, target(3) + +# CHECK-BE: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_LO_DS target 0x0 + ld 1, target@l(3) + +# CHECK-BE: ld 1, target(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_DS target 0x0 + ld 1, target(3) base: -# CHECK: lwz 1, target-base(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target-base, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16 target 0x2 - lwz 1, target-base(3) - -# CHECK: li 3, target-base@h # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target-base@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HI target 0x6 - li 3, target-base@h - -# CHECK: li 3, target-base@l # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target-base@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_LO target 0xA - li 3, target-base@l - -# CHECK: li 3, target-base@ha # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target-base@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE - li 3, target-base@ha - -# CHECK: ori 3, 3, target@l # encoding: [0x60,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 - ori 3, 3, target@l - -# CHECK: oris 3, 3, target@h # encoding: [0x64,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 - oris 3, 3, target@h - -# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 - ld 1, target@toc(2) - -# CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0 - addis 3, 2, target@toc@ha - -# CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 - addi 4, 3, target@toc@l - -# CHECK: addis 3, 2, target@toc@h # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HI target 0x0 - addis 3, 2, target@toc@h - -# CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 - lwz 1, target@toc@l(3) - -# CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0 - ld 1, target@toc@l(3) - -# CHECK: addi 4, 3, target@GOT # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16 target 0x0 - addi 4, 3, target@got - -# CHECK: ld 1, target@GOT(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_DS target 0x0 - ld 1, target@got(2) - -# CHECK: addis 3, 2, target@got@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HA target 0x0 - addis 3, 2, target@got@ha - -# CHECK: addi 4, 3, target@got@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 - addi 4, 3, target@got@l - -# CHECK: addis 3, 2, target@got@h # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HI target 0x0 - addis 3, 2, target@got@h - -# CHECK: lwz 1, target@got@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 - lwz 1, target@got@l(3) - -# CHECK: ld 1, target@got@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0 - ld 1, target@got@l(3) - - -# CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0 - addis 3, 2, target@tprel@ha - -# CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0 - addi 3, 3, target@tprel@l - -# CHECK: addi 3, 3, target@tprel # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16 target 0x0 - addi 3, 3, target@tprel - -# CHECK: addi 3, 3, target@tprel@h # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HI target 0x0 - addi 3, 3, target@tprel@h - -# CHECK: addi 3, 3, target@tprel@higher # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@higher, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHER target 0x0 - addi 3, 3, target@tprel@higher - -# CHECK: addis 3, 2, target@tprel@highest # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@highest, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHEST target 0x0 - addis 3, 2, target@tprel@highest - -# CHECK: addi 3, 3, target@tprel@highera # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@highera, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHERA target 0x0 - addi 3, 3, target@tprel@highera - -# CHECK: addis 3, 2, target@tprel@highesta # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@highesta, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHESTA target 0x0 - addis 3, 2, target@tprel@highesta - -# CHECK: ld 1, target@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO_DS target 0x0 - ld 1, target@tprel@l(3) - -# CHECK: ld 1, target@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_DS target 0x0 - ld 1, target@tprel(3) - -# CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0 - addis 3, 2, target@dtprel@ha - -# CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0 - addi 3, 3, target@dtprel@l - -# CHECK: addi 3, 3, target@dtprel # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16 target 0x0 - addi 3, 3, target@dtprel - -# CHECK: addi 3, 3, target@dtprel@h # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HI target 0x0 - addi 3, 3, target@dtprel@h - -# CHECK: addi 3, 3, target@dtprel@higher # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@higher, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHER target 0x0 - addi 3, 3, target@dtprel@higher - -# CHECK: addis 3, 2, target@dtprel@highest # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@highest, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHEST target 0x0 - addis 3, 2, target@dtprel@highest - -# CHECK: addi 3, 3, target@dtprel@highera # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@highera, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHERA target 0x0 - addi 3, 3, target@dtprel@highera - -# CHECK: addis 3, 2, target@dtprel@highesta # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@highesta, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHESTA target 0x0 - addis 3, 2, target@dtprel@highesta - -# CHECK: ld 1, target@dtprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO_DS target 0x0 - ld 1, target@dtprel@l(3) - -# CHECK: ld 1, target@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_DS target 0x0 - ld 1, target@dtprel(3) - - -# CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0 - addis 3, 2, target@got@tprel@ha - -# CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 - ld 1, target@got@tprel@l(3) - -# CHECK: addis 3, 2, target@got@tprel@h # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HI target 0x0 - addis 3, 2, target@got@tprel@h - -# CHECK: addis 3, 2, target@got@tprel@l # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 - addis 3, 2, target@got@tprel@l - -# CHECK: addis 3, 2, target@got@tprel # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0 - addis 3, 2, target@got@tprel - -# CHECK: ld 1, target@got@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0 - ld 1, target@got@tprel(3) - -# CHECK: addis 3, 2, target@got@dtprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HA target 0x0 - addis 3, 2, target@got@dtprel@ha - -# CHECK: ld 1, target@got@dtprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0 - ld 1, target@got@dtprel@l(3) - -# CHECK: addis 3, 2, target@got@dtprel@h # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HI target 0x0 - addis 3, 2, target@got@dtprel@h - -# CHECK: addis 3, 2, target@got@dtprel@l # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0 - addis 3, 2, target@got@dtprel@l - -# CHECK: addis 3, 2, target@got@dtprel # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0 - addis 3, 2, target@got@dtprel - -# CHECK: ld 1, target@got@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16ds -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0 - ld 1, target@got@dtprel(3) - -# CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0 - addis 3, 2, target@got@tlsgd@ha - -# CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0 - addi 3, 3, target@got@tlsgd@l - -# CHECK: addi 3, 3, target@got@tlsgd@h # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HI target 0x0 - addi 3, 3, target@got@tlsgd@h - -# CHECK: addi 3, 3, target@got@tlsgd # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16 target 0x0 - addi 3, 3, target@got@tlsgd - - -# CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0 - addis 3, 2, target@got@tlsld@ha - -# CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0 - addi 3, 3, target@got@tlsld@l - -# CHECK: addi 3, 3, target@got@tlsld@h # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@h, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HI target 0x0 - addi 3, 3, target@got@tlsld@h - -# CHECK: addi 3, 3, target@got@tlsld # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld, kind: fixup_ppc_half16 -# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16 target 0x0 - addi 3, 3, target@got@tlsld - -# CHECK: bl __tls_get_addr(target@tlsgd) # encoding: [0b010010BB,B,B,0bBBBBBB01] -# CHECK-NEXT: # fixup A - offset: 0, value: target@tlsgd, kind: fixup_ppc_nofixup -# CHECK-NEXT: # fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24 -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLSGD target 0x0 -# CHECK-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 - bl __tls_get_addr(target@tlsgd) - -# CHECK: bl __tls_get_addr(target@tlsld) # encoding: [0b010010BB,B,B,0bBBBBBB01] -# CHECK-NEXT: # fixup A - offset: 0, value: target@tlsld, kind: fixup_ppc_nofixup -# CHECK-NEXT: # fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24 -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLSLD target 0x0 -# CHECK-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 - bl __tls_get_addr(target@tlsld) - -# CHECK: add 3, 4, target@tls # encoding: [0x7c,0x64,0x6a,0x14] -# CHECK-NEXT: # fixup A - offset: 0, value: target@tls, kind: fixup_ppc_nofixup -# CHECK-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLS target 0x0 - add 3, 4, target@tls +# CHECK-BE: lwz 1, target-base(3) # encoding: [0x80,0x23,A,A] +# CHECK-LE: lwz 1, target-base(3) # encoding: [A,A,0x23,0x80] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target-base, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target-base, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16 target 0x2 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL16 target 0x0 + lwz 1, target-base(3) + +# CHECK-BE: li 3, target-base@h # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target-base@h # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target-base@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target-base@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HI target 0x6 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL16_HI target 0x4 + li 3, target-base@h + +# CHECK-BE: li 3, target-base@l # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target-base@l # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target-base@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target-base@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_LO target 0xA +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL16_LO target 0x8 + li 3, target-base@l + +# CHECK-BE: li 3, target-base@ha # encoding: [0x38,0x60,A,A] +# CHECK-LE: li 3, target-base@ha # encoding: [A,A,0x60,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target-base@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target-base@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL16_HA target 0xC + li 3, target-base@ha + +# CHECK-BE: ori 3, 3, target@l # encoding: [0x60,0x63,A,A] +# CHECK-LE: ori 3, 3, target@l # encoding: [A,A,0x63,0x60] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_LO target 0x0 + ori 3, 3, target@l + +# CHECK-BE: oris 3, 3, target@h # encoding: [0x64,0x63,A,A] +# CHECK-LE: oris 3, 3, target@h # encoding: [A,A,0x63,0x64] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR16_HI target 0x0 + oris 3, 3, target@h + +# CHECK-BE: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@toc(2) # encoding: [0bAAAAAA00,A,0x22,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@toc, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TOC16_DS target 0x0 + ld 1, target@toc(2) + +# CHECK-BE: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@toc@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@toc@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TOC16_HA target 0x0 + addis 3, 2, target@toc@ha + +# CHECK-BE: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A] +# CHECK-LE: addi 4, 3, target@toc@l # encoding: [A,A,0x83,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TOC16_LO target 0x0 + addi 4, 3, target@toc@l + +# CHECK-BE: addis 3, 2, target@toc@h # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@toc@h # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@toc@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@toc@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TOC16_HI target 0x0 + addis 3, 2, target@toc@h + +# CHECK-BE: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A] +# CHECK-LE: lwz 1, target@toc@l(3) # encoding: [A,A,0x23,0x80] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TOC16_LO target 0x0 + lwz 1, target@toc@l(3) + +# CHECK-BE: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@toc@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TOC16_LO_DS target 0x0 + ld 1, target@toc@l(3) + +# CHECK-BE: addi 4, 3, target@GOT # encoding: [0x38,0x83,A,A] +# CHECK-LE: addi 4, 3, target@GOT # encoding: [A,A,0x83,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@GOT, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16 target 0x0 + addi 4, 3, target@got + +# CHECK-BE: ld 1, target@GOT(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@GOT(2) # encoding: [0bAAAAAA00,A,0x22,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@GOT, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_DS target 0x0 + ld 1, target@got(2) + +# CHECK-BE: addis 3, 2, target@got@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_HA target 0x0 + addis 3, 2, target@got@ha + +# CHECK-BE: addi 4, 3, target@got@l # encoding: [0x38,0x83,A,A] +# CHECK-LE: addi 4, 3, target@got@l # encoding: [A,A,0x83,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_LO target 0x0 + addi 4, 3, target@got@l + +# CHECK-BE: addis 3, 2, target@got@h # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@h # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_HI target 0x0 + addis 3, 2, target@got@h + +# CHECK-BE: lwz 1, target@got@l(3) # encoding: [0x80,0x23,A,A] +# CHECK-LE: lwz 1, target@got@l(3) # encoding: [A,A,0x23,0x80] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_LO target 0x0 + lwz 1, target@got@l(3) + +# CHECK-BE: ld 1, target@got@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@got@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT16_LO_DS target 0x0 + ld 1, target@got@l(3) + + +# CHECK-BE: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@tprel@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_HA target 0x0 + addis 3, 2, target@tprel@ha + +# CHECK-BE: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@tprel@l # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_LO target 0x0 + addi 3, 3, target@tprel@l + +# CHECK-BE: addi 3, 3, target@tprel # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@tprel # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16 target 0x0 + addi 3, 3, target@tprel + +# CHECK-BE: addi 3, 3, target@tprel@h # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@tprel@h # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_HI target 0x0 + addi 3, 3, target@tprel@h + +# CHECK-BE: addi 3, 3, target@tprel@higher # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@tprel@higher # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@higher, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@higher, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHER target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_HIGHER target 0x0 + addi 3, 3, target@tprel@higher + +# CHECK-BE: addis 3, 2, target@tprel@highest # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@tprel@highest # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@highest, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@highest, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHEST target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_HIGHEST target 0x0 + addis 3, 2, target@tprel@highest + +# CHECK-BE: addi 3, 3, target@tprel@highera # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@tprel@highera # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@highera, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@highera, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHERA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_HIGHERA target 0x0 + addi 3, 3, target@tprel@highera + +# CHECK-BE: addis 3, 2, target@tprel@highesta # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@tprel@highesta # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@highesta, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@highesta, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHESTA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_HIGHESTA target 0x0 + addis 3, 2, target@tprel@highesta + +# CHECK-BE: ld 1, target@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@tprel@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_LO_DS target 0x0 + ld 1, target@tprel@l(3) + +# CHECK-BE: ld 1, target@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@tprel(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_DS target 0x0 + ld 1, target@tprel(3) + +# CHECK-BE: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@dtprel@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_HA target 0x0 + addis 3, 2, target@dtprel@ha + +# CHECK-BE: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@dtprel@l # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_LO target 0x0 + addi 3, 3, target@dtprel@l + +# CHECK-BE: addi 3, 3, target@dtprel # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@dtprel # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16 target 0x0 + addi 3, 3, target@dtprel + +# CHECK-BE: addi 3, 3, target@dtprel@h # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@dtprel@h # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_HI target 0x0 + addi 3, 3, target@dtprel@h + +# CHECK-BE: addi 3, 3, target@dtprel@higher # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@dtprel@higher # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@higher, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@higher, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHER target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_HIGHER target 0x0 + addi 3, 3, target@dtprel@higher + +# CHECK-BE: addis 3, 2, target@dtprel@highest # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@dtprel@highest # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@highest, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@highest, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHEST target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_HIGHEST target 0x0 + addis 3, 2, target@dtprel@highest + +# CHECK-BE: addi 3, 3, target@dtprel@highera # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@dtprel@highera # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@highera, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@highera, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHERA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_HIGHERA target 0x0 + addi 3, 3, target@dtprel@highera + +# CHECK-BE: addis 3, 2, target@dtprel@highesta # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@dtprel@highesta # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@highesta, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@highesta, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHESTA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_HIGHESTA target 0x0 + addis 3, 2, target@dtprel@highesta + +# CHECK-BE: ld 1, target@dtprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@dtprel@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_LO_DS target 0x0 + ld 1, target@dtprel@l(3) + +# CHECK-BE: ld 1, target@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@dtprel(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_DS target 0x0 + ld 1, target@dtprel(3) + + +# CHECK-BE: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@tprel@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tprel@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TPREL16_HA target 0x0 + addis 3, 2, target@got@tprel@ha + +# CHECK-BE: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@got@tprel@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 + ld 1, target@got@tprel@l(3) + +# CHECK-BE: addis 3, 2, target@got@tprel@h # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@tprel@h # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tprel@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tprel@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TPREL16_HI target 0x0 + addis 3, 2, target@got@tprel@h + +# CHECK-BE: addis 3, 2, target@got@tprel@l # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@tprel@l # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 + addis 3, 2, target@got@tprel@l + +# CHECK-BE: addis 3, 2, target@got@tprel # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@tprel # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tprel, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TPREL16_DS target 0x0 + addis 3, 2, target@got@tprel + +# CHECK-BE: ld 1, target@got@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@got@tprel(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tprel, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TPREL16_DS target 0x0 + ld 1, target@got@tprel(3) + +# CHECK-BE: addis 3, 2, target@got@dtprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@dtprel@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@dtprel@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@dtprel@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_DTPREL16_HA target 0x0 + addis 3, 2, target@got@dtprel@ha + +# CHECK-BE: ld 1, target@got@dtprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@got@dtprel@l(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@dtprel@l, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0 + ld 1, target@got@dtprel@l(3) + +# CHECK-BE: addis 3, 2, target@got@dtprel@h # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@dtprel@h # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@dtprel@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@dtprel@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_DTPREL16_HI target 0x0 + addis 3, 2, target@got@dtprel@h + +# CHECK-BE: addis 3, 2, target@got@dtprel@l # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@dtprel@l # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@dtprel@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0 + addis 3, 2, target@got@dtprel@l + +# CHECK-BE: addis 3, 2, target@got@dtprel # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@dtprel # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@dtprel, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_DTPREL16_DS target 0x0 + addis 3, 2, target@got@dtprel + +# CHECK-BE: ld 1, target@got@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@got@dtprel(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@dtprel, kind: fixup_ppc_half16ds +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_DTPREL16_DS target 0x0 + ld 1, target@got@dtprel(3) + +# CHECK-BE: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@tlsgd@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSGD16_HA target 0x0 + addis 3, 2, target@got@tlsgd@ha + +# CHECK-BE: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@got@tlsgd@l # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSGD16_LO target 0x0 + addi 3, 3, target@got@tlsgd@l + +# CHECK-BE: addi 3, 3, target@got@tlsgd@h # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@got@tlsgd@h # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSGD16_HI target 0x0 + addi 3, 3, target@got@tlsgd@h + +# CHECK-BE: addi 3, 3, target@got@tlsgd # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@got@tlsgd # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsgd, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsgd, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSGD16 target 0x0 + addi 3, 3, target@got@tlsgd + + +# CHECK-BE: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A] +# CHECK-LE: addis 3, 2, target@got@tlsld@ha # encoding: [A,A,0x62,0x3c] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsld@ha, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSLD16_HA target 0x0 + addis 3, 2, target@got@tlsld@ha + +# CHECK-BE: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@got@tlsld@l # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsld@l, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSLD16_LO target 0x0 + addi 3, 3, target@got@tlsld@l + +# CHECK-BE: addi 3, 3, target@got@tlsld@h # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@got@tlsld@h # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsld@h, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsld@h, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HI target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSLD16_HI target 0x0 + addi 3, 3, target@got@tlsld@h + +# CHECK-BE: addi 3, 3, target@got@tlsld # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@got@tlsld # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@got@tlsld, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@got@tlsld, kind: fixup_ppc_half16 +# CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_GOT_TLSLD16 target 0x0 + addi 3, 3, target@got@tlsld + +# CHECK-BE: bl __tls_get_addr(target@tlsgd) # encoding: [0b010010BB,B,B,0bBBBBBB01] +# CHECK-LE: bl __tls_get_addr(target@tlsgd) # encoding: [0bBBBBBB01,B,B,0b010010BB] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target@tlsgd, kind: fixup_ppc_nofixup +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tlsgd, kind: fixup_ppc_nofixup +# CHECK-BE-NEXT: # fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24 +# CHECK-LE-NEXT: # fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24 +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLSGD target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLSGD target 0x0 +# CHECK-BE-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 +# CHECK-LE-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 + bl __tls_get_addr(target@tlsgd) + +# CHECK-BE: bl __tls_get_addr(target@tlsld) # encoding: [0b010010BB,B,B,0bBBBBBB01] +# CHECK-LE: bl __tls_get_addr(target@tlsld) # encoding: [0bBBBBBB01,B,B,0b010010BB] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target@tlsld, kind: fixup_ppc_nofixup +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tlsld, kind: fixup_ppc_nofixup +# CHECK-BE-NEXT: # fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24 +# CHECK-LE-NEXT: # fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24 +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLSLD target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLSLD target 0x0 +# CHECK-BE-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 +# CHECK-LE-REL-NEXT: 0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0 + bl __tls_get_addr(target@tlsld) + +# CHECK-BE: add 3, 4, target@tls # encoding: [0x7c,0x64,0x6a,0x14] +# CHECK-LE: add 3, 4, target@tls # encoding: [0x14,0x6a,0x64,0x7c] +# CHECK-BE-NEXT: # fixup A - offset: 0, value: target@tls, kind: fixup_ppc_nofixup +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tls, kind: fixup_ppc_nofixup +# CHECK-BE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLS target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TLS target 0x0 + add 3, 4, target@tls # Data relocs # llvm-mc does not show any "encoding" string for data, so we just check the relocs -# CHECK-REL: .rela.data +# CHECK-BE-REL: .rela.data +# CHECK-LE-REL: .rela.data .data -# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TOC - 0x0 +# CHECK-BE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TOC - 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TOC - 0x0 .quad .TOC.@tocbase -# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPMOD64 target 0x0 +# CHECK-BE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPMOD64 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPMOD64 target 0x0 .quad target@dtpmod -# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TPREL64 target 0x0 +# CHECK-BE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TPREL64 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TPREL64 target 0x0 .quad target@tprel -# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPREL64 target 0x0 +# CHECK-BE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPREL64 target 0x0 +# CHECK-LE-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPREL64 target 0x0 .quad target@dtprel # Constant fixup ori 1, 2, 131071@l -# CHECK: ori 1, 2, 131071@l # encoding: [0x60,0x41,A,A] -# CHECK-NEXT: # fixup A - offset: 2, value: 131071@l, kind: fixup_ppc_half16 +# CHECK-BE: ori 1, 2, 131071@l # encoding: [0x60,0x41,A,A] +# CHECK-LE: ori 1, 2, 131071@l # encoding: [A,A,0x41,0x60] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: 131071@l, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: 131071@l, kind: fixup_ppc_half16 Index: llvm-suse/test/MC/PowerPC/ppc64-initial-cfa.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-initial-cfa.s +++ llvm-suse/test/MC/PowerPC/ppc64-initial-cfa.s @@ -1,7 +1,11 @@ # RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=static %s | \ -# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=STATIC +# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=STATIC -check-prefix=STATIC-BE # RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=pic %s | \ -# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC +# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC -check-prefix=PIC-BE +# RUN: llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj -relocation-model=static %s | \ +# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=STATIC -check-prefix=STATIC-LE +# RUN: llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj -relocation-model=pic %s | \ +# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC -check-prefix=PIC-LE .cfi_startproc nop @@ -23,9 +27,12 @@ # STATIC-NEXT: Relocations [ # STATIC-NEXT: ] # STATIC-NEXT: SectionData ( -# STATIC-NEXT: 0000: 00000010 00000000 017A5200 04784101 -# STATIC-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 -# STATIC-NEXT: 0020: 00000004 00000000 +# STATIC-BE-NEXT: 0000: 00000010 00000000 017A5200 04784101 +# STATIC-LE-NEXT: 0000: 10000000 00000000 017A5200 04784101 +# STATIC-BE-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 +# STATIC-LE-NEXT: 0010: 1B0C0100 10000000 18000000 00000000 +# STATIC-BE-NEXT: 0020: 00000004 00000000 +# STATIC-LE-NEXT: 0020: 04000000 00000000 # STATIC-NEXT: ) # STATIC-NEXT: } @@ -61,9 +68,12 @@ # PIC-NEXT: Relocations [ # PIC-NEXT: ] # PIC-NEXT: SectionData ( -# PIC-NEXT: 0000: 00000010 00000000 017A5200 04784101 -# PIC-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 -# PIC-NEXT: 0020: 00000004 00000000 +# PIC-BE-NEXT: 0000: 00000010 00000000 017A5200 04784101 +# PIC-LE-NEXT: 0000: 10000000 00000000 017A5200 04784101 +# PIC-BE-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 +# PIC-LE-NEXT: 0010: 1B0C0100 10000000 18000000 00000000 +# PIC-BE-NEXT: 0020: 00000004 00000000 +# PIC-LE-NEXT: 0020: 04000000 00000000 # PIC-NEXT: ) # PIC-NEXT: } Index: llvm-suse/test/MC/PowerPC/ppc64-localentry-error1.s =================================================================== --- /dev/null +++ llvm-suse/test/MC/PowerPC/ppc64-localentry-error1.s @@ -0,0 +1,11 @@ + +# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t +# RUN: FileCheck < %t %s +# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t +# RUN: FileCheck < %t %s + +sym: + .localentry sym, 123 + +# CHECK: LLVM ERROR: .localentry expression cannot be encoded. + Index: llvm-suse/test/MC/PowerPC/ppc64-localentry-error2.s =================================================================== --- /dev/null +++ llvm-suse/test/MC/PowerPC/ppc64-localentry-error2.s @@ -0,0 +1,12 @@ + +# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t +# RUN: FileCheck < %t %s +# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t +# RUN: FileCheck < %t %s + + .globl remote_sym +sym: + .localentry sym, remote_sym + +# CHECK: LLVM ERROR: .localentry expression must be absolute. + Index: llvm-suse/test/MC/PowerPC/ppc64-localentry.s =================================================================== --- /dev/null +++ llvm-suse/test/MC/PowerPC/ppc64-localentry.s @@ -0,0 +1,70 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -h -r -symbols | FileCheck %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj %s | \ +# RUN: llvm-readobj -h -r -symbols | FileCheck %s + + .type callee1, @function +callee1: + nop + nop + .localentry callee1, .-callee1 + nop + nop + .size callee1, .-callee1 + + .type callee2, @function +callee2: + nop + nop + .size callee2, .-callee2 + + .type caller, @function +caller: + bl callee1 + nop + bl callee2 + nop + .size caller, .-caller + + .section .text.other +caller_other: + bl callee1 + nop + bl callee2 + nop + .size caller_other, .-caller_other + +# Verify that use of .localentry implies ABI version 2 +# CHECK: ElfHeader { +# CHECK: Flags [ (0x2) + +# Verify that fixups to local function symbols are performed only +# if the target symbol does not use .localentry +# CHECK: Relocations [ +# CHECK: Section ({{[0-9]*}}) .rela.text { +# CHECK-NEXT: R_PPC64_REL24 callee1 +# CHECK-NEXT: } +# CHECK-NOT: R_PPC64_REL24 callee2 +# CHECK: Section ({{[0-9]*}}) .rela.text.other { +# CHECK-NEXT: R_PPC64_REL24 callee1 +# CHECK-NEXT: R_PPC64_REL24 .text +# CHECK-NEXT: } + +# Verify that .localentry is encoded in the Other field. +# CHECK: Symbols [ +# CHECK: Name: callee1 +# CHECK-NEXT: Value: +# CHECK-NEXT: Size: 16 +# CHECK-NEXT: Binding: Local +# CHECK-NEXT: Type: Function +# CHECK-NEXT: Other: 96 +# CHECK-NEXT: Section: .text +# CHECK: Name: callee2 +# CHECK-NEXT: Value: +# CHECK-NEXT: Size: 8 +# CHECK-NEXT: Binding: Local +# CHECK-NEXT: Type: Function +# CHECK-NEXT: Other: 0 +# CHECK-NEXT: Section: .text + Index: llvm-suse/test/MC/PowerPC/ppc64-operands.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-operands.s +++ llvm-suse/test/MC/PowerPC/ppc64-operands.s @@ -1,115 +1,149 @@ -# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s # Register operands -# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14] - add 1, 2, 3 - -# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14] - add %r1, %r2, %r3 - -# CHECK: add 0, 0, 0 # encoding: [0x7c,0x00,0x02,0x14] - add 0, 0, 0 - -# CHECK: add 31, 31, 31 # encoding: [0x7f,0xff,0xfa,0x14] - add 31, 31, 31 - -# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00] - addi 1, 0, 0 - -# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00] - addi 1, %r0, 0 +# CHECK-BE: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14] +# CHECK-LE: add 1, 2, 3 # encoding: [0x14,0x1a,0x22,0x7c] + add 1, 2, 3 + +# CHECK-BE: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14] +# CHECK-LE: add 1, 2, 3 # encoding: [0x14,0x1a,0x22,0x7c] + add %r1, %r2, %r3 + +# CHECK-BE: add 0, 0, 0 # encoding: [0x7c,0x00,0x02,0x14] +# CHECK-LE: add 0, 0, 0 # encoding: [0x14,0x02,0x00,0x7c] + add 0, 0, 0 + +# CHECK-BE: add 31, 31, 31 # encoding: [0x7f,0xff,0xfa,0x14] +# CHECK-LE: add 31, 31, 31 # encoding: [0x14,0xfa,0xff,0x7f] + add 31, 31, 31 + +# CHECK-BE: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00] +# CHECK-LE: addi 1, 0, 0 # encoding: [0x00,0x00,0x20,0x38] + addi 1, 0, 0 + +# CHECK-BE: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00] +# CHECK-LE: addi 1, 0, 0 # encoding: [0x00,0x00,0x20,0x38] + addi 1, %r0, 0 # Signed 16-bit immediate operands -# CHECK: addi 1, 2, 0 # encoding: [0x38,0x22,0x00,0x00] - addi 1, 2, 0 - -# CHECK: addi 1, 0, -32768 # encoding: [0x38,0x20,0x80,0x00] - addi 1, 0, -32768 - -# CHECK: addi 1, 0, 32767 # encoding: [0x38,0x20,0x7f,0xff] - addi 1, 0, 32767 +# CHECK-BE: addi 1, 2, 0 # encoding: [0x38,0x22,0x00,0x00] +# CHECK-LE: addi 1, 2, 0 # encoding: [0x00,0x00,0x22,0x38] + addi 1, 2, 0 + +# CHECK-BE: addi 1, 0, -32768 # encoding: [0x38,0x20,0x80,0x00] +# CHECK-LE: addi 1, 0, -32768 # encoding: [0x00,0x80,0x20,0x38] + addi 1, 0, -32768 + +# CHECK-BE: addi 1, 0, 32767 # encoding: [0x38,0x20,0x7f,0xff] +# CHECK-LE: addi 1, 0, 32767 # encoding: [0xff,0x7f,0x20,0x38] + addi 1, 0, 32767 # Unsigned 16-bit immediate operands -# CHECK: ori 1, 2, 0 # encoding: [0x60,0x41,0x00,0x00] - ori 1, 2, 0 - -# CHECK: ori 1, 2, 65535 # encoding: [0x60,0x41,0xff,0xff] - ori 1, 2, 65535 +# CHECK-BE: ori 1, 2, 0 # encoding: [0x60,0x41,0x00,0x00] +# CHECK-LE: ori 1, 2, 0 # encoding: [0x00,0x00,0x41,0x60] + ori 1, 2, 0 + +# CHECK-BE: ori 1, 2, 65535 # encoding: [0x60,0x41,0xff,0xff] +# CHECK-LE: ori 1, 2, 65535 # encoding: [0xff,0xff,0x41,0x60] + ori 1, 2, 65535 # Signed 16-bit immediate operands (extended range for addis) -# CHECK: addis 1, 0, 0 # encoding: [0x3c,0x20,0x00,0x00] - addis 1, 0, -65536 - -# CHECK: addis 1, 0, -1 # encoding: [0x3c,0x20,0xff,0xff] - addis 1, 0, 65535 +# CHECK-BE: addis 1, 0, 0 # encoding: [0x3c,0x20,0x00,0x00] +# CHECK-LE: addis 1, 0, 0 # encoding: [0x00,0x00,0x20,0x3c] + addis 1, 0, -65536 + +# CHECK-BE: addis 1, 0, -1 # encoding: [0x3c,0x20,0xff,0xff] +# CHECK-LE: addis 1, 0, -1 # encoding: [0xff,0xff,0x20,0x3c] + addis 1, 0, 65535 # D-Form memory operands -# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] - lwz 1, 0(0) - -# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] - lwz 1, 0(%r0) - -# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00] - lwz 1, 0(31) - -# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00] - lwz 1, 0(%r31) - -# CHECK: lwz 1, -32768(2) # encoding: [0x80,0x22,0x80,0x00] - lwz 1, -32768(2) - -# CHECK: lwz 1, 32767(2) # encoding: [0x80,0x22,0x7f,0xff] - lwz 1, 32767(2) - - -# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00] - ld 1, 0(0) - -# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00] - ld 1, 0(%r0) - -# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00] - ld 1, 0(31) - -# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00] - ld 1, 0(%r31) - -# CHECK: ld 1, -32768(2) # encoding: [0xe8,0x22,0x80,0x00] - ld 1, -32768(2) - -# CHECK: ld 1, 32764(2) # encoding: [0xe8,0x22,0x7f,0xfc] - ld 1, 32764(2) - -# CHECK: ld 1, 4(2) # encoding: [0xe8,0x22,0x00,0x04] - ld 1, 4(2) - -# CHECK: ld 1, -4(2) # encoding: [0xe8,0x22,0xff,0xfc] - ld 1, -4(2) +# CHECK-BE: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] +# CHECK-LE: lwz 1, 0(0) # encoding: [0x00,0x00,0x20,0x80] + lwz 1, 0(0) + +# CHECK-BE: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] +# CHECK-LE: lwz 1, 0(0) # encoding: [0x00,0x00,0x20,0x80] + lwz 1, 0(%r0) + +# CHECK-BE: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00] +# CHECK-LE: lwz 1, 0(31) # encoding: [0x00,0x00,0x3f,0x80] + lwz 1, 0(31) + +# CHECK-BE: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00] +# CHECK-LE: lwz 1, 0(31) # encoding: [0x00,0x00,0x3f,0x80] + lwz 1, 0(%r31) + +# CHECK-BE: lwz 1, -32768(2) # encoding: [0x80,0x22,0x80,0x00] +# CHECK-LE: lwz 1, -32768(2) # encoding: [0x00,0x80,0x22,0x80] + lwz 1, -32768(2) + +# CHECK-BE: lwz 1, 32767(2) # encoding: [0x80,0x22,0x7f,0xff] +# CHECK-LE: lwz 1, 32767(2) # encoding: [0xff,0x7f,0x22,0x80] + lwz 1, 32767(2) + + +# CHECK-BE: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00] +# CHECK-LE: ld 1, 0(0) # encoding: [0x00,0x00,0x20,0xe8] + ld 1, 0(0) + +# CHECK-BE: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00] +# CHECK-LE: ld 1, 0(0) # encoding: [0x00,0x00,0x20,0xe8] + ld 1, 0(%r0) + +# CHECK-BE: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00] +# CHECK-LE: ld 1, 0(31) # encoding: [0x00,0x00,0x3f,0xe8] + ld 1, 0(31) + +# CHECK-BE: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00] +# CHECK-LE: ld 1, 0(31) # encoding: [0x00,0x00,0x3f,0xe8] + ld 1, 0(%r31) + +# CHECK-BE: ld 1, -32768(2) # encoding: [0xe8,0x22,0x80,0x00] +# CHECK-LE: ld 1, -32768(2) # encoding: [0x00,0x80,0x22,0xe8] + ld 1, -32768(2) + +# CHECK-BE: ld 1, 32764(2) # encoding: [0xe8,0x22,0x7f,0xfc] +# CHECK-LE: ld 1, 32764(2) # encoding: [0xfc,0x7f,0x22,0xe8] + ld 1, 32764(2) + +# CHECK-BE: ld 1, 4(2) # encoding: [0xe8,0x22,0x00,0x04] +# CHECK-LE: ld 1, 4(2) # encoding: [0x04,0x00,0x22,0xe8] + ld 1, 4(2) + +# CHECK-BE: ld 1, -4(2) # encoding: [0xe8,0x22,0xff,0xfc] +# CHECK-LE: ld 1, -4(2) # encoding: [0xfc,0xff,0x22,0xe8] + ld 1, -4(2) # Immediate branch operands -# CHECK: b .+1024 # encoding: [0x48,0x00,0x04,0x00] - b 1024 - -# CHECK: ba 1024 # encoding: [0x48,0x00,0x04,0x02] - ba 1024 - -# CHECK: beq 0, .+1024 # encoding: [0x41,0x82,0x04,0x00] - beq 1024 - -# CHECK: beqa 0, 1024 # encoding: [0x41,0x82,0x04,0x02] - beqa 1024 - -# CHECK: # encoding: [0x42,0x9f,A,0bAAAAAA01] - bcl 20, 31, $+4 - -# CHECK: # encoding: [0x42,0x00,A,0bAAAAAA00] - bdnz $-8 +# CHECK-BE: b .+1024 # encoding: [0x48,0x00,0x04,0x00] +# CHECK-LE: b .+1024 # encoding: [0x00,0x04,0x00,0x48] + b 1024 + +# CHECK-BE: ba 1024 # encoding: [0x48,0x00,0x04,0x02] +# CHECK-LE: ba 1024 # encoding: [0x02,0x04,0x00,0x48] + ba 1024 + +# CHECK-BE: beq 0, .+1024 # encoding: [0x41,0x82,0x04,0x00] +# CHECK-LE: beq 0, .+1024 # encoding: [0x00,0x04,0x82,0x41] + beq 1024 + +# CHECK-BE: beqa 0, 1024 # encoding: [0x41,0x82,0x04,0x02] +# CHECK-LE: beqa 0, 1024 # encoding: [0x02,0x04,0x82,0x41] + beqa 1024 + +# CHECK-BE: # encoding: [0x42,0x9f,A,0bAAAAAA01] +# CHECK-LE: # encoding: [0bAAAAAA01,A,0x9f,0x42] + bcl 20, 31, $+4 + +# CHECK-BE: # encoding: [0x42,0x00,A,0bAAAAAA00] +# CHECK-LE: # encoding: [0bAAAAAA00,A,0x00,0x42] + bdnz $-8 Index: llvm-suse/test/MC/PowerPC/ppc64-regs.s =================================================================== --- llvm-suse.orig/test/MC/PowerPC/ppc64-regs.s +++ llvm-suse/test/MC/PowerPC/ppc64-regs.s @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple powerpc64le-unknown-unknown --show-encoding %s | FileCheck %s #CHECK: .cfi_startproc #CHECK: .cfi_offset r0, 0 Index: llvm-suse/test/tools/llvm-cov/llvm-cov.test =================================================================== --- llvm-suse.orig/test/tools/llvm-cov/llvm-cov.test +++ llvm-suse/test/tools/llvm-cov/llvm-cov.test @@ -7,4 +7,4 @@ RUN: | diff -aub test.cpp.gcov - RUN: not llvm-cov -gcno=test_read_fail.gcno -gcda=test.gcda -XFAIL: powerpc64, s390x +XFAIL: powerpc64-, s390x
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