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File backport-llvm-r233690 of Package llvm
------------------------------------------------------------------------ r233690 | uweigand | 2015-03-31 14:58:17 +0200 (Tue, 31 Mar 2015) | 13 lines [SystemZ] Support RISBGN instruction on zEC12 So far, we do not yet support any instruction specific to zEC12. Most of the facilities added with zEC12 are indeed not very useful to compiler code generation, but there is one exception: the miscellaneous-extensions facility provides the RISBGN instruction, which is a variant of RISBG that does not set the condition code. Add support for this facility, MC support for RISBGN, and CodeGen support for prefering RISBGN over RISBG on zEC12, unless we can actually make use of the condition code set by RISBG. ------------------------------------------------------------------------ Index: test/CodeGen/SystemZ/risbg-03.ll =================================================================== --- /dev/null +++ test/CodeGen/SystemZ/risbg-03.ll @@ -0,0 +1,30 @@ +; Test use of RISBG vs RISBGN on zEC12. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s + +; On zEC12, we generally prefer RISBGN. +define i64 @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: risbgn %r2, %r3, 60, 62, 0 +; CHECK: br %r14 + %anda = and i64 %a, -15 + %andb = and i64 %b, 14 + %or = or i64 %anda, %andb + ret i64 %or +} + +; But we may fall back to RISBG if we can use the condition code. +define i64 @f2(i64 %a, i64 %b, i32* %c) { +; CHECK-LABEL: f2: +; CHECK: risbg %r2, %r3, 60, 62, 0 +; CHECK-NEXT: ipm +; CHECK: br %r14 + %anda = and i64 %a, -15 + %andb = and i64 %b, 14 + %or = or i64 %anda, %andb + %cmp = icmp sgt i64 %or, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* %c, align 4 + ret i64 %or +} + Index: test/MC/Disassembler/SystemZ/insns.txt =================================================================== --- test/MC/Disassembler/SystemZ/insns.txt.orig +++ test/MC/Disassembler/SystemZ/insns.txt @@ -6367,6 +6367,27 @@ # CHECK: risbg %r4, %r5, 6, 7, 8 0xec 0x45 0x06 0x07 0x08 0x55 +# CHECK: risbgn %r0, %r0, 0, 0, 0 +0xec 0x00 0x00 0x00 0x00 0x59 + +# CHECK: risbgn %r0, %r0, 0, 0, 63 +0xec 0x00 0x00 0x00 0x3f 0x59 + +# CHECK: risbgn %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x59 + +# CHECK: risbgn %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x59 + +# CHECK: risbgn %r0, %r15, 0, 0, 0 +0xec 0x0f 0x00 0x00 0x00 0x59 + +# CHECK: risbgn %r15, %r0, 0, 0, 0 +0xec 0xf0 0x00 0x00 0x00 0x59 + +# CHECK: risbgn %r4, %r5, 6, 7, 8 +0xec 0x45 0x06 0x07 0x08 0x59 + # CHECK: risbhg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x5d Index: test/MC/SystemZ/insn-bad-zEC12.s =================================================================== --- /dev/null +++ test/MC/SystemZ/insn-bad-zEC12.s @@ -0,0 +1,24 @@ +# For zEC12 only. +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,0,-1 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,0,64 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,-1,0 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,0,256,0 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,-1,0,0 +#CHECK: error: invalid operand +#CHECK: risbgn %r0,%r0,256,0,0 + + risbgn %r0,%r0,0,0,-1 + risbgn %r0,%r0,0,0,64 + risbgn %r0,%r0,0,-1,0 + risbgn %r0,%r0,0,256,0 + risbgn %r0,%r0,-1,0,0 + risbgn %r0,%r0,256,0,0 + Index: test/MC/SystemZ/insn-good-zEC12.s =================================================================== --- /dev/null +++ test/MC/SystemZ/insn-good-zEC12.s @@ -0,0 +1,19 @@ +# For zEC12 and above. +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s + +#CHECK: risbgn %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x59] +#CHECK: risbgn %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59] +#CHECK: risbgn %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x59] +#CHECK: risbgn %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x59] +#CHECK: risbgn %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x59] +#CHECK: risbgn %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x59] +#CHECK: risbgn %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x59] + + risbgn %r0,%r0,0,0,0 + risbgn %r0,%r0,0,0,63 + risbgn %r0,%r0,0,255,0 + risbgn %r0,%r0,255,0,0 + risbgn %r0,%r15,0,0,0 + risbgn %r15,%r0,0,0,0 + risbgn %r4,%r5,6,7,8 + Index: test/MC/SystemZ/insn-bad-z196.s =================================================================== --- test/MC/SystemZ/insn-bad-z196.s.orig +++ test/MC/SystemZ/insn-bad-z196.s @@ -546,6 +546,11 @@ locr %r0,%r0,-1 locr %r0,%r0,16 +#CHECK: error: {{(instruction requires: miscellaneous-extensions)?}} +#CHECK: risbgn %r1, %r2, 0, 0, 0 + + risbgn %r1, %r2, 0, 0, 0 + #CHECK: error: invalid operand #CHECK: risbhg %r0,%r0,0,0,-1 #CHECK: error: invalid operand Index: lib/Target/SystemZ/SystemZISelDAGToDAG.cpp =================================================================== --- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp.orig +++ lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -902,6 +902,9 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZer } unsigned Opcode = SystemZ::RISBG; + // Prefer RISBGN if available, since it does not clobber CC. + if (Subtarget.hasMiscellaneousExtensions()) + Opcode = SystemZ::RISBGN; EVT OpcodeVT = MVT::i64; if (VT == MVT::i32 && Subtarget.hasHighWord()) { Opcode = SystemZ::RISBMux; @@ -949,9 +952,13 @@ SDNode *SystemZDAGToDAGISel::tryRxSBG(SD // See whether we can avoid an AND in the first operand by converting // ROSBG to RISBG. - if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) + if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) { Opcode = SystemZ::RISBG; - + // Prefer RISBGN if available, since it does not clobber CC. + if (Subtarget.hasMiscellaneousExtensions()) + Opcode = SystemZ::RISBGN; + } + EVT VT = N->getValueType(0); SDValue Ops[5] = { convertTo(SDLoc(N), MVT::i64, Op0), Index: lib/Target/SystemZ/SystemZProcessors.td =================================================================== --- lib/Target/SystemZ/SystemZProcessors.td.orig +++ lib/Target/SystemZ/SystemZProcessors.td @@ -55,6 +55,11 @@ def FeatureInterlockedAccess1 : SystemZF >; def FeatureNoInterlockedAccess1 : SystemZMissingFeature<"InterlockedAccess1">; +def FeatureMiscellaneousExtensions : SystemZFeature< + "miscellaneous-extensions", "MiscellaneousExtensions", + "Assume that the miscellaneous-extensions facility is installed" +>; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, @@ -64,4 +69,5 @@ def : Processor<"z196", NoItineraries, def : Processor<"zEC12", NoItineraries, [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord, FeatureFPExtension, FeaturePopulationCount, - FeatureFastSerialization, FeatureInterlockedAccess1]>; + FeatureFastSerialization, FeatureInterlockedAccess1, + FeatureMiscellaneousExtensions]>; Index: lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- lib/Target/SystemZ/SystemZSubtarget.h.orig +++ lib/Target/SystemZ/SystemZSubtarget.h @@ -35,6 +35,7 @@ protected: bool HasPopulationCount; bool HasFastSerialization; bool HasInterlockedAccess1; + bool HasMiscellaneousExtensions; private: Triple TargetTriple; @@ -70,6 +71,11 @@ public: // Return true if the target has interlocked-access facility 1. bool hasInterlockedAccess1() const { return HasInterlockedAccess1; } + // Return true if the target has the miscellaneous-extensions facility. + bool hasMiscellaneousExtensions() const { + return HasMiscellaneousExtensions; + } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM, Index: lib/Target/SystemZ/SystemZInstrInfo.td =================================================================== --- lib/Target/SystemZ/SystemZInstrInfo.td.orig +++ lib/Target/SystemZ/SystemZInstrInfo.td @@ -1061,6 +1061,10 @@ let Defs = [CC] in { def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; } +// On zEC12 we have a variant of RISBG that does not set CC. +let Predicates = [FeatureMiscellaneousExtensions] in + def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; + // Forms of RISBG that only affect one word of the destination register. // They do not set CC. let Predicates = [FeatureHighWord] in { Index: lib/Target/SystemZ/SystemZSubtarget.cpp =================================================================== --- lib/Target/SystemZ/SystemZSubtarget.cpp.orig +++ lib/Target/SystemZ/SystemZSubtarget.cpp @@ -27,7 +27,7 @@ SystemZSubtarget::SystemZSubtarget(const : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasPopulationCount(false), HasFastSerialization(false), - HasInterlockedAccess1(false), + HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), TargetTriple(TT) { std::string CPUName = CPU; if (CPUName.empty()) Index: lib/Target/SystemZ/SystemZInstrInfo.cpp =================================================================== --- lib/Target/SystemZ/SystemZInstrInfo.cpp.orig +++ lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -723,9 +723,12 @@ SystemZInstrInfo::convertToThreeAddress( unsigned Start, End; if (isRxSBGMask(Imm, And.RegSize, Start, End)) { unsigned NewOpcode; - if (And.RegSize == 64) + if (And.RegSize == 64) { NewOpcode = SystemZ::RISBG; - else { + // Prefer RISBGN if available, since it does not clobber CC. + if (TM.getSubtargetImpl()->hasMiscellaneousExtensions()) + NewOpcode = SystemZ::RISBGN; + } else { NewOpcode = SystemZ::RISBMux; Start &= 31; End &= 31; @@ -1147,17 +1150,22 @@ unsigned SystemZInstrInfo::getOpcodeForO unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const { switch (Opcode) { - case SystemZ::L: return SystemZ::LT; - case SystemZ::LY: return SystemZ::LT; - case SystemZ::LG: return SystemZ::LTG; - case SystemZ::LGF: return SystemZ::LTGF; - case SystemZ::LR: return SystemZ::LTR; - case SystemZ::LGFR: return SystemZ::LTGFR; - case SystemZ::LGR: return SystemZ::LTGR; - case SystemZ::LER: return SystemZ::LTEBR; - case SystemZ::LDR: return SystemZ::LTDBR; - case SystemZ::LXR: return SystemZ::LTXBR; - default: return 0; + case SystemZ::L: return SystemZ::LT; + case SystemZ::LY: return SystemZ::LT; + case SystemZ::LG: return SystemZ::LTG; + case SystemZ::LGF: return SystemZ::LTGF; + case SystemZ::LR: return SystemZ::LTR; + case SystemZ::LGFR: return SystemZ::LTGFR; + case SystemZ::LGR: return SystemZ::LTGR; + case SystemZ::LER: return SystemZ::LTEBR; + case SystemZ::LDR: return SystemZ::LTDBR; + case SystemZ::LXR: return SystemZ::LTXBR; + // On zEC12 we prefer to use RISBGN. But if there is a chance to + // actually use the condition code, we may turn it back into RISGB. + // Note that RISBG is not really a "load-and-test" instruction, + // but sets the same condition code values, so is OK to use here. + case SystemZ::RISBGN: return SystemZ::RISBG; + default: return 0; } } Index: test/CodeGen/SystemZ/and-04.ll =================================================================== --- test/CodeGen/SystemZ/and-04.ll.orig +++ test/CodeGen/SystemZ/and-04.ll @@ -1,6 +1,6 @@ ; Test 64-bit ANDs in which the second operand is constant. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s ; Use RISBG for a single bit. define i64 @f1(i64 %a) { Index: test/CodeGen/SystemZ/insert-06.ll =================================================================== --- test/CodeGen/SystemZ/insert-06.ll.orig +++ test/CodeGen/SystemZ/insert-06.ll @@ -1,6 +1,6 @@ ; Test insertions of i32s into the low half of an i64. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s ; Insertion of an i32 can be done using LR. define i64 @f1(i64 %a, i32 %b) { Index: test/CodeGen/SystemZ/risbg-02.ll =================================================================== --- test/CodeGen/SystemZ/risbg-02.ll.orig +++ test/CodeGen/SystemZ/risbg-02.ll @@ -1,6 +1,6 @@ ; Test sequences that can use RISBG with a normal first operand. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s ; Test a case with two ANDs. define i32 @f1(i32 %a, i32 %b) { Index: test/CodeGen/SystemZ/shift-10.ll =================================================================== --- test/CodeGen/SystemZ/shift-10.ll.orig +++ test/CodeGen/SystemZ/shift-10.ll @@ -1,6 +1,6 @@ ; Test compound shifts. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mcpu=z10 -mtriple=s390x-linux-gnu | FileCheck %s ; Test a shift right followed by a sign extension. This can use two shifts. define i64 @f1(i32 %a) {
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