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SUSE:SLE-12:Update
xen.1589
561bbc8b-VT-d-don-t-suppress-invalidation-addre...
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File 561bbc8b-VT-d-don-t-suppress-invalidation-address-write-when-0.patch of Package xen.1589
# Commit 710942e57fb42ff8f344ca82f6b678f67e38ae63 # Date 2015-10-12 15:58:35 +0200 # Author Jan Beulich <jbeulich@suse.com> # Committer Jan Beulich <jbeulich@suse.com> VT-d: don't suppress invalidation address write when it is zero GFN zero is a valid address, and hence may need invalidation done for it just like for any other GFN. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Yang Zhang <yang.z.zhang@intel.com> --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -415,7 +415,7 @@ static int flush_iotlb_reg(void *_iommu, { struct iommu *iommu = (struct iommu *) _iommu; int tlb_offset = ecap_iotlb_offset(iommu->ecap); - u64 val = 0, val_iva = 0; + u64 val = 0; unsigned long flags; /* @@ -436,7 +436,6 @@ static int flush_iotlb_reg(void *_iommu, switch ( type ) { case DMA_TLB_GLOBAL_FLUSH: - /* global flush doesn't need set IVA_REG */ val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; break; case DMA_TLB_DSI_FLUSH: @@ -444,8 +443,6 @@ static int flush_iotlb_reg(void *_iommu, break; case DMA_TLB_PSI_FLUSH: val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); - /* Note: always flush non-leaf currently */ - val_iva = size_order | addr; break; default: BUG(); @@ -458,8 +455,11 @@ static int flush_iotlb_reg(void *_iommu, spin_lock_irqsave(&iommu->register_lock, flags); /* Note: Only uses first TLB reg currently */ - if ( val_iva ) - dmar_writeq(iommu->reg, tlb_offset, val_iva); + if ( type == DMA_TLB_PSI_FLUSH ) + { + /* Note: always flush non-leaf currently. */ + dmar_writeq(iommu->reg, tlb_offset, size_order | addr); + } dmar_writeq(iommu->reg, tlb_offset + 8, val); /* Make sure hardware complete it */
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