File 5a856a2b-x86-use-32bit-xors-for-clearing-GPRs.p... of Package xen.8005

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File 5a856a2b-x86-use-32bit-xors-for-clearing-GPRs.patch of Package xen.8005

# Commit eb1d3a3f04b85d596862a4c9dcf796e67ab4dc09
# Date 2018-02-15 11:08:27 +0000
# Author Andrew Cooper <andrew.cooper3@citrix.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/entry: Use 32bit xors rater than 64bit xors for clearing GPRs

Intel's Silvermont/Knights Landing architecture treats them as full ALU
operations, rather than zeroing idoms.

No functional change, and no change in code volume (only changing the bit
selection in the REX prefix).

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/include/asm-x86/x86_64/asm_defns.h
+++ b/xen/include/asm-x86/x86_64/asm_defns.h
@@ -38,10 +38,10 @@
         movq  %r10,UREGS_r10(%rsp)
         movq  %r11,UREGS_r11(%rsp)
 .endif
-        xor   %r8, %r8
-        xor   %r9, %r9
-        xor   %r10, %r10
-        xor   %r11, %r11
+        xor   %r8d, %r8d
+        xor   %r9d, %r9d
+        xor   %r10d, %r10d
+        xor   %r11d, %r11d
         movq  %rbx,UREGS_rbx(%rsp)
         xor   %ebx, %ebx
         movq  %rbp,UREGS_rbp(%rsp)
@@ -58,10 +58,10 @@
         movq  %r14,UREGS_r14(%rsp)
         movq  %r15,UREGS_r15(%rsp)
 .endif
-        xor   %r12, %r12
-        xor   %r13, %r13
-        xor   %r14, %r14
-        xor   %r15, %r15
+        xor   %r12d, %r12d
+        xor   %r13d, %r13d
+        xor   %r14d, %r14d
+        xor   %r15d, %r15d
 .endm
 
 /*

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File 5a856a2b-x86-use-32bit-xors-for-clearing-GPRs.patch of Package xen.8005

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