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SUSE:SLE-12:Update
xen
5a5e3a4e-5-x86-definitions-for-Indirect-Branch-...
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File 5a5e3a4e-5-x86-definitions-for-Indirect-Branch-Controls.patch of Package xen
# Commit 0d703a701cc4bc47773986b2796eebd28b1439b5 # Date 2018-01-16 17:45:50 +0000 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/feature: Definitions for Indirect Branch Controls Contemporary processors are gaining Indirect Branch Controls via microcode updates. Intel are introducing one bit to indicate IBRS and IBPB support, and a second bit for STIBP. AMD are introducing IBPB only, so enumerate it with a separate bit. Furthermore, depending on compiler and microcode availability, we may want to run Xen with IBRS set, or clear. To use these facilities, we synthesise separate IBRS and IBPB bits for internal use. A lot of infrastructure is required before these features are safe to offer to guests. This is part of XSA-254. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Acked-by: Wei Liu <wei.liu2@citrix.com> --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -138,4 +138,11 @@ #define X86_FEATURE_INVPCID 10 /* Invalidate Process Context ID */ #define X86_FEATURE_RTM 11 /* Restricted Transactional Memory */ +/* AMD-defined CPU features, CPUID level 0x80000008, ebx */ +#define X86_FEATURE_IBPB 12 /* IBPB support only (no IBRS, used by AMD) */ + +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx) */ +#define X86_FEATURE_IBRSB 26 /* IBRS and IBPB support (used by Intel) */ +#define X86_FEATURE_STIBP 27 /* STIBP */ + #endif /* __LIBXC_CPUFEATURE_H */ --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -372,9 +372,11 @@ static void xc_cpuid_hvm_policy( bitmaskof(X86_FEATURE_INVPCID) | bitmaskof(X86_FEATURE_RTM) | bitmaskof(X86_FEATURE_FSGSBASE)); + regs[3] &= (bitmaskof(X86_FEATURE_IBRSB) | + bitmaskof(X86_FEATURE_STIBP)); } else - regs[1] = 0; - regs[0] = regs[2] = regs[3] = 0; + regs[1] = regs[3] = 0; + regs[0] = regs[2] = 0; break; case 0x0000000d: @@ -403,7 +405,8 @@ static void xc_cpuid_hvm_policy( case 0x80000008: regs[0] &= 0x0000ffffu; - regs[1] = regs[3] = 0; + regs[3] &= bitmaskof(X86_FEATURE_IBPB); + regs[1] = 0; break; case 0x00000002: /* Intel cache info (dumped by AMD policy) */ @@ -496,6 +499,7 @@ static void xc_cpuid_pv_policy( case 0x00000007: if ( input[1] == 0 ) + { regs[1] &= (bitmaskof(X86_FEATURE_BMI1) | bitmaskof(X86_FEATURE_HLE) | bitmaskof(X86_FEATURE_AVX2) | @@ -503,9 +507,12 @@ static void xc_cpuid_pv_policy( bitmaskof(X86_FEATURE_ERMS) | bitmaskof(X86_FEATURE_RTM) | bitmaskof(X86_FEATURE_FSGSBASE)); + regs[3] &= (bitmaskof(X86_FEATURE_IBRSB) | + bitmaskof(X86_FEATURE_STIBP)); + } else - regs[1] = 0; - regs[0] = regs[2] = regs[3] = 0; + regs[1] = regs[3] = 0; + regs[0] = regs[2] = 0; break; case 0x0000000d: --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -153,6 +153,8 @@ int libxl_cpuid_parse_config(libxl_cpuid {"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1}, {"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1}, {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1}, + {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1}, + {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1}, {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1}, {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1}, @@ -182,6 +184,7 @@ int libxl_cpuid_parse_config(libxl_cpuid {"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1}, {"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1}, {"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6}, + {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1}, {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4}, {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8}, {"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1}, --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -198,7 +198,7 @@ static void __init early_cpu_detect(void static void __cpuinit generic_identify(struct cpuinfo_x86 *c) { - u32 tfms, xlvl, capability, excap, eax, ebx; + u32 tfms, xlvl, capability, excap, eax, ebx, edx, dummy; /* Get vendor name */ cpuid(0x00000000, &c->cpuid_level, @@ -234,9 +234,10 @@ static void __cpuinit generic_identify(s if ( xlvl >= 0x80000004 ) get_model_name(c); /* Default name */ if ( xlvl >= 0x80000008 ) { - eax = cpuid_eax(0x80000008); + cpuid(0x80000008, &eax, &ebx, &dummy, &dummy); paddr_bits = eax & 0xff; hap_paddr_bits = ((eax >> 16) & 0xff) ?: paddr_bits; + c->x86_capability[X86_FEATURE_IBPB / 32] = ebx; } } @@ -245,9 +246,9 @@ static void __cpuinit generic_identify(s /* Intel-defined flags: level 0x00000007 */ if ( c->cpuid_level >= 0x00000007 ) { - u32 dummy; - cpuid_count(0x00000007, 0, &dummy, &ebx, &dummy, &dummy); + cpuid_count(0x00000007, 0, &dummy, &ebx, &dummy, &edx); c->x86_capability[X86_FEATURE_FSGSBASE / 32] = ebx; + c->x86_capability[X86_FEATURE_IBRSB / 32] = edx; } #ifdef CONFIG_X86_HT --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -31,8 +31,25 @@ enum ind_thunk { static void __init print_details(enum ind_thunk thunk) { + unsigned int _7d0 = 0, e8b = 0, tmp; + + /* Collect diagnostics about available mitigations. */ + if ( boot_cpu_data.cpuid_level >= 7 ) + cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0); + if ( cpuid_eax(0x80000000) >= 0x80000008 ) + cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); + printk(XENLOG_DEBUG "Speculative mitigation facilities:\n"); + /* Hardware features which pertain to speculative mitigations. */ + if ( (_7d0 & (cpufeat_mask(X86_FEATURE_IBRSB) | + cpufeat_mask(X86_FEATURE_STIBP))) || + (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ) + printk(XENLOG_DEBUG " Hardware features:%s%s%s\n", + (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "", + (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "", + (e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : ""); + /* Compiled-in support which pertains to BTI mitigations. */ #ifdef CONFIG_INDIRECT_THUNK printk(XENLOG_DEBUG " Compiled-in support: INDIRECT_THUNK\n"); --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -9,7 +9,7 @@ #include <xen/bitops.h> -#define NCAPINTS 8 /* N 32-bit words worth of info */ +#define NCAPINTS 10 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -154,6 +154,13 @@ #define X86_FEATURE_NO_FPU_SEL (7*32+13) /* FPU CS/DS stored as zero */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ +/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ +#define X86_FEATURE_IBPB (8*32+12) /* IBPB support only (no IBRS, used by AMD) */ + +/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ +#define X86_FEATURE_IBRSB (9*32+26) /* IBRS and IBPB support (used by Intel) */ +#define X86_FEATURE_STIBP (9*32+27) /* STIBP */ + #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) #define cpufeat_mask(idx) (1u << ((idx) & 31)) --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -31,6 +31,14 @@ #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSE (1<<_EFER_FFXSE) +/* Speculation Controls. */ +#define MSR_SPEC_CTRL 0x00000048 +#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) +#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) + +#define MSR_PRED_CMD 0x00000049 +#define PRED_CMD_IBPB (_AC(1, ULL) << 0) + /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_A_PERFCTR0 0x000004c1
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