File xsa333.patch of Package xen.16552

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File xsa333.patch of Package xen.16552

From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly

This MSR doesn't exist on AMD hardware, and switching away from the safe
functions in the common MSR path was an erroneous change.

Partially revert the change.

This is XSA-333.

Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

--- sle15sp1.orig/xen/arch/x86/pv/emul-priv-op.c	2020-09-07 17:39:38.000000000 +0200
+++ sle15sp1/xen/arch/x86/pv/emul-priv-op.c	2020-09-07 17:53:54.688168500 +0200
@@ -892,7 +892,8 @@ static int read_msr(unsigned int reg, ui
         return X86EMUL_OKAY;
 
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(reg, *val);
+        if ( rdmsr_safe(reg, *val) )
+            break;
         *val = guest_misc_enable(*val);
         return X86EMUL_OKAY;
 
@@ -1030,7 +1031,8 @@ static int write_msr(unsigned int reg, u
         break;
 
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(reg, temp);
+        if ( rdmsr_safe(reg, temp) )
+            break;
         if ( val != guest_misc_enable(temp) )
             goto invalid;
         return X86EMUL_OKAY;

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File xsa333.patch of Package xen.16552

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