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File 5e4ec20e-x86-virtualise-MSR_PLATFORM_ID-properly.patch of Package xen (Revision 3a513a1c247a1fd4ac85ccdcb610d485)

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# Commit 691265f96097d4fe3e46ff4267451d49b30143e6
# Date 2020-02-20 17:29:50 +0000
# Author Andrew Cooper <andrew.cooper3@citrix.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/msr: Virtualise MSR_PLATFORM_ID properly

This is an Intel-only, read-only MSR related to microcode loading.  Expose it
in similar circumstances as the PATCHLEVEL MSR.

This should have been alongside c/s 013896cb8b2 "x86/msr: Fix handling of
MSR_AMD_PATCHLEVEL/MSR_IA32_UCODE_REV"

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -136,6 +136,13 @@ int guest_rdmsr(const struct vcpu *v, ui
         /* Not offered to guests. */
         goto gp_fault;
 
+    case MSR_IA32_PLATFORM_ID:
+        if ( cp->x86_vendor != X86_VENDOR_INTEL ||
+             boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+            goto gp_fault;
+        rdmsrl(MSR_IA32_PLATFORM_ID, *val);
+        break;
+
     case MSR_AMD_PATCHLEVEL:
         BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
         /*
@@ -256,6 +263,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t
     {
         uint64_t rsvd;
 
+    case MSR_IA32_PLATFORM_ID:
     case MSR_INTEL_CORE_THREAD_COUNT:
     case MSR_INTEL_PLATFORM_INFO:
     case MSR_ARCH_CAPABILITIES:

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File 5e4ec20e-x86-virtualise-MSR_PLATFORM_ID-properly.patch of Package xen (Revision 3a513a1c247a1fd4ac85ccdcb610d485)

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