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SUSE:SLE-15-SP1:Update
xen
60d496d6-VT-d-clear_fault_bits-should-clear-all...
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File 60d496d6-VT-d-clear_fault_bits-should-clear-all.patch of Package xen
# Commit 80589800ae62fce43fd3921e8fbd362465fe5ba3 # Date 2021-06-24 16:29:42 +0200 # Author Jan Beulich <jbeulich@suse.com> # Committer Jan Beulich <jbeulich@suse.com> VT-d: clear_fault_bits() should clear all fault bits If there is any way for one fault to be left set in the recording registers, there's no reason there couldn't also be multiple ones. If PPF set set (being the OR or all F fields), simply loop over the entire range of fault recording registers, clearing F everywhere. Since PPF is a r/o bit, also remove it from DMA_FSTS_FAULTS (arguably the constant's name is ambiguous as well). Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2167,13 +2167,23 @@ static int __hwdom_init setup_hwdom_devi void clear_fault_bits(struct iommu *iommu) { - u64 val; unsigned long flags; spin_lock_irqsave(&iommu->register_lock, flags); - val = dmar_readq(iommu->reg, cap_fault_reg_offset(iommu->cap) + 8); - dmar_writeq(iommu->reg, cap_fault_reg_offset(iommu->cap) + 8, val); + + if ( dmar_readl(iommu->reg, DMAR_FSTS_REG) & DMA_FSTS_PPF ) + { + unsigned int reg = cap_fault_reg_offset(iommu->cap); + unsigned int end = reg + cap_num_fault_regs(iommu->cap); + + do { + dmar_writel(iommu->reg, reg + 12, DMA_FRCD_F); + reg += PRIMARY_FAULT_REG_LEN; + } while ( reg < end ); + } + dmar_writel(iommu->reg, DMAR_FSTS_REG, DMA_FSTS_FAULTS); + spin_unlock_irqrestore(&iommu->register_lock, flags); } --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -174,7 +174,8 @@ #define DMA_FSTS_IQE ((u64)1 << 4) #define DMA_FSTS_ICE ((u64)1 << 5) #define DMA_FSTS_ITE ((u64)1 << 6) -#define DMA_FSTS_FAULTS DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_AFO | DMA_FSTS_APF | DMA_FSTS_IQE | DMA_FSTS_ICE | DMA_FSTS_ITE +#define DMA_FSTS_FAULTS (DMA_FSTS_PFO | DMA_FSTS_AFO | DMA_FSTS_APF | \ + DMA_FSTS_IQE | DMA_FSTS_ICE | DMA_FSTS_ITE) #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) /* FRCD_REG, 32 bits access */
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