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SUSE:SLE-15-SP3:Update
xen
xsa455.patch
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File xsa455.patch of Package xen
From: Andrew Cooper <andrew.cooper3@citrix.com> Subject: x86/spec-ctrl: Fix BTC/SRSO mitigations We were looking for SCF_entry_ibpb in the wrong variable in the top-of-stack block, and xen_spec_ctrl won't have had bit 5 set because Xen doesn't understand SPEC_CTRL_RRSBA_DIS_U yet. This is XSA-455 / CVE-2024-31142. Fixes: 53a570b28569 ("x86/spec-ctrl: Support IBPB-on-entry") Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/hvm/svm/entry.S +++ b/xen/arch/x86/hvm/svm/entry.S @@ -105,7 +105,7 @@ __UNLIKELY_END(nsvm_hap) /* SPEC_CTRL_ENTRY_FROM_SVM Req: %rsp=regs/cpuinfo, %rdx=0 Clob: acd */ .macro svm_vmexit_cond_ibpb - testb $SCF_entry_ibpb, CPUINFO_xen_spec_ctrl(%rsp) + testb $SCF_entry_ibpb, CPUINFO_spec_ctrl_flags(%rsp) jz .L_skip_ibpb mov $MSR_PRED_CMD, %ecx --- a/xen/include/asm-x86/spec_ctrl_asm.h +++ b/xen/include/asm-x86/spec_ctrl_asm.h @@ -102,7 +102,7 @@ jz .L\@_skip testb $3, UREGS_cs(%rsp) .else - testb $SCF_entry_ibpb, CPUINFO_xen_spec_ctrl(%rsp) + testb $SCF_entry_ibpb, CPUINFO_spec_ctrl_flags(%rsp) .endif jz .L\@_skip
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