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SUSE:SLE-15-SP5:GA
xen.17121
5dca846c-x86-fix-clear_IO_APIC_pin-raw-writes.p...
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File 5dca846c-x86-fix-clear_IO_APIC_pin-raw-writes.patch of Package xen.17121
# Commit dedcb1087dfeae0bbd9eea465a57f25b13e40585 # Date 2019-11-12 11:07:40 +0100 # Author Roger Pau Monné <roger.pau@citrix.com> # Committer Jan Beulich <jbeulich@suse.com> x86/ioapic: fix clear_IO_APIC_pin write of raw entries clear_IO_APIC_pin can be called after the iommu has been enabled, and using raw reads and writes to modify IO-APIC entries that have been setup to use interrupt remapping can lead to issues as some of the fields have different meaning when the IO-APIC entry is setup to point to an interrupt remapping table entry. The following ASSERT in AMD IOMMU code triggers afterwards as a result of the raw changes to IO-APIC entries performed by clear_IO_APIC_pin. (XEN) [ 10.082154] ENABLING IO-APIC IRQs (XEN) [ 10.087789] -> Using new ACK method (XEN) [ 10.093738] Assertion 'get_rte_index(rte) == offset' failed at iommu_intr.c:328 Fix this by making sure that modifications to entries are performed in non raw mode when fields are affected which may either have changed meaning with interrupt remapping, or which may need mirroring into IRTEs. Reported-by: Sergey Dyasli <sergey.dyasli@citrix.com> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -517,8 +517,9 @@ static void clear_IO_APIC_pin(unsigned i if (entry.irr) { /* Make sure the trigger mode is set to level. */ if (!entry.trigger) { + entry = __ioapic_read_entry(apic, pin, false); entry.trigger = 1; - __ioapic_write_entry(apic, pin, TRUE, entry); + __ioapic_write_entry(apic, pin, false, entry); } __io_apic_eoi(apic, entry.vector, pin); } @@ -528,7 +529,7 @@ static void clear_IO_APIC_pin(unsigned i */ memset(&entry, 0, sizeof(entry)); entry.mask = 1; - __ioapic_write_entry(apic, pin, TRUE, entry); + __ioapic_write_entry(apic, pin, false, entry); entry = __ioapic_read_entry(apic, pin, TRUE); if (entry.irr)
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