File rasdaemon-mce-amd-smca-Optimizing-decoding-of-M... of Package rasdaemon.35133

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File rasdaemon-mce-amd-smca-Optimizing-decoding-of-MCA_CTL_SMU-bits.patch of Package rasdaemon.35133

From 73d8177ce0d2fcb7693cacee4778d0845ebd3788 Mon Sep 17 00:00:00 2001
From: sathya priya kumar <SathyaPriya.K@amd.com>
Date: Thu, 13 Jun 2024 05:29:09 +0000
Subject: [PATCH] rasdaemon: mce-amd-smca: Optimizing decoding of MCA_CTL_SMU
 bits

Optimize smca_smu2_mce_desc in better way from the commit ced615c.

Update existing array with extended error descriptions instead
of creating new array, simplifying the code.

Signed-off-by: Sathya Priya Kumar <sathyapriya.k@amd.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 mce-amd-smca.c    | 29 +++--------------------------
 ras-mce-handler.h |  1 -
 2 files changed, 3 insertions(+), 27 deletions(-)

diff --git a/mce-amd-smca.c b/mce-amd-smca.c
index a55e013..c97f4cb 100644
--- a/mce-amd-smca.c
+++ b/mce-amd-smca.c
@@ -421,7 +421,7 @@ static const char * const smca_smu_mce_desc[] = {
 	"An ECC or parity error in an SMU RAM instance",
 };
 
-static const char * smca_smu2_mce_desc[64] = {
+static const char * const smca_smu2_mce_desc[] = {
 	"High SRAM ECC or parity error",
 	"Low SRAM ECC or parity error",
 	"Data Cache Bank A ECC or parity error",
@@ -434,14 +434,13 @@ static const char * smca_smu2_mce_desc[64] = {
 	"Instruction Tag Cache Bank B ECC or parity error",
 	"System Hub Read Buffer ECC or parity error",
 	"PHY RAS ECC Error",
-};
-
-static const char * smca_smu2_ext_mce_desc[] = {
+	[12 ... 57] = "Reserved",
 	"A correctable error from a GFX Sub-IP",
 	"A fatal error from a GFX Sub-IP",
 	"Reserved",
 	"Reserved",
 	"A poison error from a GFX Sub-IP",
+	"Reserved",
 };
 
 static const char * const smca_mp5_mce_desc[] = {
@@ -850,28 +849,7 @@ static struct smca_bank_name smca_names[] = {
 	[SMCA_GMI_PHY]			= { "Global Memory Interconnect PHY Unit" },
 };
 
-void smca_smu2_ext_err_desc(void)
-{
-	int i, j;
-	int smu2_bits = 62;
-
-	/*
-	 * MCA_CTL_SMU error stings are defined for b'58:59 and b'62
-	 * in MI300A AMD systems. See AMD PPR MCA::SMU::MCA_CTL_SMU
-	 *
-	 * b'0:11 can be decoded from existing array smca_smu2_mce_desc.
-	 * b'12:57 are Reserved and b'58:62 are appended to the
-	 * smca_smu2_mce_desc.
-	 */
-	for (i = 12, j = 0; i < smu2_bits || j < 5; i++, j++) {
-		for ( ; i < 58; i++)
-			smca_smu2_mce_desc[i] = "Reserved";
-
-		smca_smu2_mce_desc[i] = smca_smu2_ext_mce_desc[j];
-	}
-}
-
 void amd_decode_errcode(struct mce_event *e)
 {
 
 	decode_amd_errcode(e);
@@ -961,7 +939,6 @@ void decode_smca_error(struct mce_event *e, struct mce_priv *m)
 	mcatype_hwid = HWID_MCATYPE(ipid_high & MCI_IPID_HWID,
 				    (ipid_high & MCI_IPID_MCATYPE) >> 16);
 
-	smca_smu2_ext_err_desc();
 	fixup_hwid(m, &mcatype_hwid);
 
 	for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
diff --git a/ras-mce-handler.h b/ras-mce-handler.h
index b8ae389..694bd41 100644
--- a/ras-mce-handler.h
+++ b/ras-mce-handler.h
@@ -127,7 +127,6 @@ int set_intel_imc_log(enum cputype cputype, unsigned ncpus);
 /* Undertake AMD SMCA Error Decoding */
 void decode_smca_error(struct mce_event *e, struct mce_priv *m);
 void amd_decode_errcode(struct mce_event *e);
-void smca_smu2_ext_err_desc(void);
 
 /* Per-CPU-type decoders for Intel CPUs */
 void p4_decode_model(struct mce_event *e);
-- 
2.45.2

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File rasdaemon-mce-amd-smca-Optimizing-decoding-of-MCA_CTL_SMU-bits.patch of Package rasdaemon.35133

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