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SUSE:SLE-15-SP7:GA
qemu-linux-user.8001
0065-target-i386-clear-C-bit-when-walkin.patch
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File 0065-target-i386-clear-C-bit-when-walkin.patch of Package qemu-linux-user.8001
From 960c74cfec5dd8bbafb366923927bb7d1b8a8cb0 Mon Sep 17 00:00:00 2001 From: Brijesh Singh <brijesh.singh@amd.com> Date: Wed, 28 Feb 2018 14:28:00 -0700 Subject: [PATCH] target/i386: clear C-bit when walking SEV guest page table In SEV-enabled guest the pte entry will have C-bit set, we need to clear the C-bit when walking the page table. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> [BR: FATE#322124] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target/i386/helper.c | 31 +++++++++++--------- target/i386/monitor.c | 68 ++++++++++++++++++++++++++++--------------- 2 files changed, 62 insertions(+), 37 deletions(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index 5dc9e8839b..11ee48e297 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" +#include "sev_i386.h" #include "kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" @@ -732,6 +733,9 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int32_t a20_mask; uint32_t page_offset; int page_size; + uint64_t me_mask; + + me_mask = sev_get_me_mask(); a20_mask = x86_get_a20_mask(env); if (!(env->cr[0] & CR0_PG_MASK)) { @@ -755,25 +759,25 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } if (la57) { - pml5e_addr = ((env->cr[3] & ~0xfff) + + pml5e_addr = ((env->cr[3] & ~0xfff & me_mask) + (((addr >> 48) & 0x1ff) << 3)) & a20_mask; - pml5e = ldq_phys_debug(cs, pml5e_addr); + pml5e = ldq_phys_debug(cs, pml5e_addr) & me_mask; if (!(pml5e & PG_PRESENT_MASK)) { return -1; } } else { - pml5e = env->cr[3]; + pml5e = env->cr[3] & me_mask; } pml4e_addr = ((pml5e & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff) << 3)) & a20_mask; - pml4e = ldq_phys_debug(cs, pml4e_addr); + pml4e = ldq_phys_debug(cs, pml4e_addr) & me_mask; if (!(pml4e & PG_PRESENT_MASK)) { return -1; } pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; - pdpe = x86_ldq_phys(cs, pdpe_addr); + pdpe = ldq_phys_debug(cs, pdpe_addr) & me_mask; if (!(pdpe & PG_PRESENT_MASK)) { return -1; } @@ -786,16 +790,16 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } else #endif { - pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & - a20_mask; - pdpe = ldq_phys_debug(cs, pdpe_addr); + pdpe_addr = ((env->cr[3] & ~0x1f & me_mask) + ((addr >> 27) & 0x18)) + & a20_mask; + pdpe = ldq_phys_debug(cs, pdpe_addr) & me_mask; if (!(pdpe & PG_PRESENT_MASK)) return -1; } pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; - pde = ldq_phys_debug(cs, pde_addr); + pde = ldq_phys_debug(cs, pde_addr) & me_mask; if (!(pde & PG_PRESENT_MASK)) { return -1; } @@ -808,7 +812,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) & a20_mask; page_size = 4096; - pte = ldq_phys_debug(cs, pte_addr); + pte = ldq_phys_debug(cs, pte_addr) & me_mask; } if (!(pte & PG_PRESENT_MASK)) { return -1; @@ -817,8 +821,9 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) uint32_t pde; /* page directory entry */ - pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask; - pde = ldl_phys_debug(cs, pde_addr); + pde_addr = ((env->cr[3] & ~0xfff & me_mask) + ((addr >> 20) & 0xffc)) + & a20_mask; + pde = ldl_phys_debug(cs, pde_addr) & me_mask; if (!(pde & PG_PRESENT_MASK)) return -1; if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { @@ -827,7 +832,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } else { /* page directory entry */ pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask; - pte = ldl_phys_debug(cs, pte_addr); + pte = ldl_phys_debug(cs, pte_addr) & me_mask; if (!(pte & PG_PRESENT_MASK)) { return -1; } diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 3999dadf88..9f2487793d 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -96,16 +96,20 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env) unsigned int l1, l2, l3; uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask = sev_get_me_mask(); pdp_addr = env->cr[3] & ~0x1f; + pdp_addr &= me_mask; for (l1 = 0; l1 < 4; l1++) { cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { /* 2M pages with PAE, CR4.PSE is ignored */ @@ -116,7 +120,7 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pt_addr + l3 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l1 << 30) + (l2 << 21) + (l3 << 12), @@ -138,10 +142,13 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; + uint64_t me_mask; + + me_mask = sev_get_me_mask(); for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); + pml4e = le64_to_cpu(pml4e & me_mask); if (!(pml4e & PG_PRESENT_MASK)) { continue; } @@ -149,7 +156,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); if (!(pdpe & PG_PRESENT_MASK)) { continue; } @@ -164,7 +171,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); if (!(pde & PG_PRESENT_MASK)) { continue; } @@ -179,7 +186,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, pt_addr = pde & 0x3fffffffff000ULL; for (l4 = 0; l4 < 512; l4++) { cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); if (pte & PG_PRESENT_MASK) { print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12), @@ -196,11 +203,14 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env) uint64_t l0; uint64_t pml5e; uint64_t pml5_addr; + uint64_t me_mask; - pml5_addr = env->cr[3] & 0x3fffffffff000ULL; + me_mask = sev_get_me_mask(); + + pml5_addr = env->cr[3] & 0x3fffffffff000ULL & me_mask; for (l0 = 0; l0 < 512; l0++) { cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); - pml5e = le64_to_cpu(pml5e); + pml5e = le64_to_cpu(pml5e & me_mask); if (pml5e & PG_PRESENT_MASK) { tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); } @@ -228,7 +238,8 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) if (env->cr[4] & CR4_LA57_MASK) { tlb_info_la57(mon, env); } else { - tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL); + tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL & + sev_get_me_mask()); } } else #endif @@ -312,19 +323,22 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env) uint64_t pdpe, pde, pte; uint64_t pdp_addr, pd_addr, pt_addr; hwaddr start, end; + uint64_t me_mask; - pdp_addr = env->cr[3] & ~0x1f; + me_mask = sev_get_me_mask(); + + pdp_addr = env->cr[3] & ~0x1f & me_mask; last_prot = 0; start = -1; for (l1 = 0; l1 < 4; l1++) { cpu_physical_memory_read_debug(pdp_addr + l1 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); end = l1 << 30; if (pdpe & PG_PRESENT_MASK) { pd_addr = pdpe & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pd_addr + l2 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); end = (l1 << 30) + (l2 << 21); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -336,7 +350,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pt_addr + l3 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); end = (l1 << 30) + (l2 << 21) + (l3 << 12); if (pte & PG_PRESENT_MASK) { prot = pte & pde & (PG_USER_MASK | PG_RW_MASK | @@ -369,19 +383,22 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) uint64_t l1, l2, l3, l4; uint64_t pml4e, pdpe, pde, pte; uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask = sev_get_me_mask(); - pml4_addr = env->cr[3] & 0x3fffffffff000ULL; + pml4_addr = env->cr[3] & 0x3fffffffff000ULL & me_mask; last_prot = 0; start = -1; for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); + pml4e = le64_to_cpu(pml4e & me_mask); end = l1 << 39; if (pml4e & PG_PRESENT_MASK) { pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); end = (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { if (pdpe & PG_PSE_MASK) { @@ -394,7 +411,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); end = (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { if (pde & PG_PSE_MASK) { @@ -408,7 +425,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env) cpu_physical_memory_read_debug(pt_addr + l4 * 8, &pte, 8); - pte = le64_to_cpu(pte); + pte = le64_to_cpu(pte & me_mask); end = (l1 << 39) + (l2 << 30) + (l3 << 21) + (l4 << 12); if (pte & PG_PRESENT_MASK) { @@ -447,13 +464,16 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) uint64_t l0, l1, l2, l3, l4; uint64_t pml5e, pml4e, pdpe, pde, pte; uint64_t pml5_addr, pml4_addr, pdp_addr, pd_addr, pt_addr, start, end; + uint64_t me_mask; + + me_mask = sev_get_me_mask(); - pml5_addr = env->cr[3] & 0x3fffffffff000ULL; + pml5_addr = env->cr[3] & 0x3fffffffff000ULL & me_mask; last_prot = 0; start = -1; for (l0 = 0; l0 < 512; l0++) { cpu_physical_memory_read_debug(pml5_addr + l0 * 8, &pml5e, 8); - pml5e = le64_to_cpu(pml5e); + pml5e = le64_to_cpu(pml5e & me_mask); end = l0 << 48; if (!(pml5e & PG_PRESENT_MASK)) { prot = 0; @@ -464,7 +484,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pml4_addr = pml5e & 0x3fffffffff000ULL; for (l1 = 0; l1 < 512; l1++) { cpu_physical_memory_read_debug(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); + pml4e = le64_to_cpu(pml4e & me_mask); end = (l0 << 48) + (l1 << 39); if (!(pml4e & PG_PRESENT_MASK)) { prot = 0; @@ -475,7 +495,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pdp_addr = pml4e & 0x3fffffffff000ULL; for (l2 = 0; l2 < 512; l2++) { cpu_physical_memory_read_debug(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); + pdpe = le64_to_cpu(pdpe & me_mask); end = (l0 << 48) + (l1 << 39) + (l2 << 30); if (pdpe & PG_PRESENT_MASK) { prot = 0; @@ -494,7 +514,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env) pd_addr = pdpe & 0x3fffffffff000ULL; for (l3 = 0; l3 < 512; l3++) { cpu_physical_memory_read_debug(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); + pde = le64_to_cpu(pde & me_mask); end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21); if (pde & PG_PRESENT_MASK) { prot = 0;
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