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xen.32200
xsa434-2.patch
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File xsa434-2.patch of Package xen.32200
From f287b47734a0ff67c5087dbab7366c8e6120ecaa Mon Sep 17 00:00:00 2001 From: Andrew Cooper <andrew.cooper3@citrix.com> Date: Wed, 14 Jun 2023 09:13:28 +0100 Subject: x86/spec-ctrl: Enumerations for Speculative Return Stack Overflow AMD have specified new CPUID bits relating to SRSO. * SRSO_NO indicates that hardware is no longer vulnerable to SRSO. * IBPB_BRTYPE indicates that IBPB flushes branch type information too. * SBPB indicates support for a relaxed form of IBPB that does not flush branch type information. Current CPUs (Zen4 and older) are not expected to enumerate these bits. Native software is expected to synthesise them for guests using model and microcode revision checks. Two are just status bits, and SBPB is trivial to support for guests by tweaking the reserved bit calculation in guest_wrmsr() and feature dependencies. Expose all by default to guests, so they start showing up when Xen synthesises them. While adding feature dependenies for IBPB, fix up an overlooked issue from XSA-422. It's inappropriate to advertise that IBPB flushes RET predictions if IBPB is unavailable itself. This is part of XSA-434 / CVE-2023-20569 Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Roger Pau Monné <roger.pau@citrix.com> --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -181,6 +181,9 @@ static const char *str_7a1[32] = static const char *str_e21a[32] = { [ 2] = "lfence+", + + /* 26 */ [27] = "sbpb", + [28] = "ibpb-brtype", [29] = "srso-no", }; static const char *str_7b1[32] = --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -322,7 +322,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t if ( !cp->feat.ibrsb && !cp->extd.ibpb ) goto gp_fault; /* MSR available? */ - if ( val & ~PRED_CMD_IBPB ) + rsvd = ~(PRED_CMD_IBPB | + (cp->extd.sbpb ? PRED_CMD_SBPB : 0)); + + if ( val & rsvd ) goto gp_fault; /* Rsvd bit set? */ if ( v == curr ) --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -402,7 +402,7 @@ custom_param("pv-l1tf", parse_pv_l1tf); static void __init print_details(enum ind_thunk thunk) { - unsigned int _7d0 = 0, _7d2 = 0, e8b = 0, max = 0, tmp; + unsigned int _7d0 = 0, _7d2 = 0, e8b = 0, e21a = 0, max = 0, tmp; uint64_t caps = 0; /* Collect diagnostics about available mitigations. */ @@ -412,6 +412,8 @@ static void __init print_details(enum in cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2); if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 ) cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); + if ( boot_cpu_data.extended_cpuid_level >= 0x80000021 ) + cpuid(0x80000021, &e21a, &tmp, &tmp, &tmp); if ( cpu_has_arch_caps ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); @@ -421,7 +423,7 @@ static void __init print_details(enum in * Hardware read-only information, stating immunity to certain issues, or * suggestions of which mitigation to use. */ - printk(" Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + printk(" Hardware hints:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", (caps & ARCH_CAPS_RDCL_NO) ? " RDCL_NO" : "", (caps & ARCH_CAPS_EIBRS) ? " EIBRS" : "", (caps & ARCH_CAPS_RSBA) ? " RSBA" : "", @@ -441,10 +443,12 @@ static void __init print_details(enum in (e8b & cpufeat_mask(X86_FEATURE_IBRS_FAST)) ? " IBRS_FAST" : "", (e8b & cpufeat_mask(X86_FEATURE_IBRS_SAME_MODE)) ? " IBRS_SAME_MODE" : "", (e8b & cpufeat_mask(X86_FEATURE_BTC_NO)) ? " BTC_NO" : "", - (e8b & cpufeat_mask(X86_FEATURE_IBPB_RET)) ? " IBPB_RET" : ""); + (e8b & cpufeat_mask(X86_FEATURE_IBPB_RET)) ? " IBPB_RET" : "", + (e21a & cpufeat_mask(X86_FEATURE_IBPB_BRTYPE)) ? " IBPB_BRTYPE" : "", + (e21a & cpufeat_mask(X86_FEATURE_SRSO_NO)) ? " SRSO_NO" : ""); /* Hardware features which need driving to mitigate issues. */ - printk(" Hardware features:%s%s%s%s%s%s%s%s%s%s%s\n", + printk(" Hardware features:%s%s%s%s%s%s%s%s%s%s%s%s\n", (e8b & cpufeat_mask(X86_FEATURE_IBPB)) || (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBPB" : "", (e8b & cpufeat_mask(X86_FEATURE_IBRS)) || @@ -460,7 +464,8 @@ static void __init print_details(enum in (_7d0 & cpufeat_mask(X86_FEATURE_SRBDS_CTRL)) ? " SRBDS_CTRL" : "", (e8b & cpufeat_mask(X86_FEATURE_VIRT_SSBD)) ? " VIRT_SSBD" : "", (caps & ARCH_CAPS_TSX_CTRL) ? " TSX_CTRL" : "", - (caps & ARCH_CAPS_FB_CLEAR_CTRL) ? " FB_CLEAR_CTRL" : ""); + (caps & ARCH_CAPS_FB_CLEAR_CTRL) ? " FB_CLEAR_CTRL" : "", + (e21a & cpufeat_mask(X86_FEATURE_SBPB)) ? " SBPB" : ""); /* Compiled-in support which pertains to mitigations. */ if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) || IS_ENABLED(CONFIG_SHADOW_PAGING) ) --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -45,6 +45,7 @@ #define MSR_PRED_CMD 0x00000049 #define PRED_CMD_IBPB (_AC(1, ULL) << 0) +#define PRED_CMD_SBPB (_AC(1, ULL) << 7) #define MSR_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -269,6 +269,9 @@ XEN_CPUFEATURE(SSBD, 9*32+31) / /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ +XEN_CPUFEATURE(SBPB, 11*32+27) /*A Selective Branch Predictor Barrier */ +XEN_CPUFEATURE(IBPB_BRTYPE, 11*32+28) /*A IBPB flushes Branch Type predictions too */ +XEN_CPUFEATURE(SRSO_NO, 11*32+29) /*A Hardware not vulenrable to Speculative Return Stack Overflow */ /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -300,6 +300,7 @@ def crunch_numbers(state): # as dependent features simplifies Xen's logic, and prevents the guest # from seeing implausible configurations. IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS], + IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE], # The ARCH_CAPS CPUID bit enumerates the availability of the whole register. ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)),
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