File gcc-power7-sles-11sp1.patch02d of Package gcc43

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File gcc-power7-sles-11sp1.patch02d of Package gcc43 (Revision 726ce42732b30905b8a30ec20fa41c83)

Currently displaying revision 726ce42732b30905b8a30ec20fa41c83 , Show latest

2009-10-15  Michael Meissner  <meissner@linux.vnet.ibm.com>
	    Pat Haugen  <pthaugen@us.ibm.com>
	    Revital Eres <ERES@il.ibm.com>
	    Peter Bergner  <bergner@vnet.ibm.com>
	
	Backport rs6000 changes from GCC 4.5 mainline to 4.3 to enable
	testing power7 in the testsuite.

2009-10-15  Michael Meissner  <meissner@linux.vnet.ibm.com>

* gcc.target/powerpc/altivec-4.c (b): Use VMX result to eliminate
	warnings.
	* g++.dg/ext/altivec-2.C (main): Ditto.

2009-09-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/41331
	* gcc.target/powerpc/bswap64-4.c: New file to test bswap64 on a
	-m32 -mpowerpc64 system.

2009-07-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
		    Pat Haugen  <pthaugen@us.ibm.com>
		    Revital Eres <ERES@il.ibm.com>

* gcc.target/powerpc/altivec-32.c: New file to test
	Altivec simple math function vectorization.

* gcc.target/powerpc/bswap-run.c: New file to test swap
	builtins.
	* gcc.target/powerpc/bswap16.c: Ditto.
	* gcc.target/powerpc/bswap32.c: Ditto.
	* gcc.target/powerpc/bswap64-1.c: Ditto.
	* gcc.target/powerpc/bswap64-2.c: Ditto.
	* gcc.target/powerpc/bswap64-3.c: Ditto.

* gcc.target/powerpc/popcount-2.c: New file to test
	power7 popcntd instructions.
	* gcc.target/powerpc/popcount-3.c: Ditto.

* gcc.target/powerpc/pr39457.c: New VSX test.
	* gcc.target/powerpc/vsx-builtin-1.c: Ditto.
	* gcc.target/powerpc/vsx-builtin-2.c: Ditto.
	* gcc.target/powerpc/vsx-builtin-3.c: Ditto.
	* gcc.target/powerpc/vsx-builtin-4.c: Ditto.
	* gcc.target/powerpc/vsx-builtin-5.c: Ditto.
	* gcc.target/powerpc/vsx-builtin-6.c: Ditto.
	* gcc.target/powerpc/vsx-vector-1.c: Ditto.
	* gcc.target/powerpc/vsx-vector-2.c: Ditto.
	* gcc.target/powerpc/vsx-vector-3.c: Ditto.
	* gcc.target/powerpc/vsx-vector-4.c: Ditto.
	* gcc.target/powerpc/vsx-vector-5.c: Ditto.
	* gcc.target/powerpc/vsx-vector-6.c: Ditto.

* gcc.target/powerpc/altivec-6.c: Store the result of
	vec_add, so the optimizer doesn't remove it.

* gcc.dg/vmx/vmx.exp: Explicitly add -mno-vsx to
	prevent VSX code generation.

* lib/target-supports.exp (check_vsx_hw_available): New
	function to test if VSX available.
	(check_effective_target_powerpc_vsx_ok): Ditto.
	(check_vmx_hw_available): Add explicit -mno-vsx.

diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.dg/vmx/vmx.exp sles-11sp1/gcc/testsuite/gcc.dg/vmx/vmx.exp
--- sles-11sp1-orig/gcc/testsuite/gcc.dg/vmx/vmx.exp	2008-02-19 04:53:21.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.dg/vmx/vmx.exp	2009-10-13 13:08:55.000000000 -0400
@@ -31,7 +31,7 @@ if {![istarget powerpc*-*-*]
 # nothing but extensions.
 global DEFAULT_VMXCFLAGS
 if ![info exists DEFAULT_VMXCFLAGS] then {
-    set DEFAULT_VMXCFLAGS "-maltivec -mabi=altivec -std=gnu99"
+    set DEFAULT_VMXCFLAGS "-maltivec -mabi=altivec -std=gnu99 -mno-vsx"
 }
 
 # If the target system supports AltiVec instructions, the default action
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/altivec-4.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/altivec-4.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/altivec-4.c	2008-02-19 04:53:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/altivec-4.c	2009-10-12 19:47:53.000000000 -0400
@@ -4,7 +4,7 @@
 
 #define vector __attribute__((vector_size(16)))
 
-static int vector x, y;
+static int vector x, y, z;
 
 static vector signed int i,j;
 static vector signed short s,t;
@@ -20,7 +20,7 @@ static int int1, int2;
 void
 b()
 {
-  __builtin_altivec_vadduwm (x, y);
+  z = __builtin_altivec_vadduwm (x, y);
 
   /* Make sure the predicates accept correct argument types.  */
   
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/altivec-6.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/altivec-6.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/altivec-6.c	2008-02-19 04:53:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/altivec-6.c	2009-10-13 14:37:41.000000000 -0400
@@ -5,7 +5,7 @@
 #include <altivec.h>
 
 /* These denote "generic" GCC vectors.  */
-static int __attribute__((vector_size(16))) x, y;
+static int __attribute__((vector_size(16))) x, y, z;
 
 static vector signed int i,j;
 static vector signed short s,t;
@@ -21,7 +21,7 @@ static int int1, int2;
 void
 b()
 {
-  vec_add (x, y);
+  z = vec_add (x, y);
 
   /* Make sure the predicates accept correct argument types.  */
 
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap16.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap16.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap16.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap16.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "lhbrx" } } */
+/* { dg-final { scan-assembler "sthbrx" } } */
+
+unsigned short us;
+unsigned int load_bswap16 (unsigned short *p) { return __builtin_bswap16 (*p); }
+void store_bswap16 (unsigned int a) { us = __builtin_bswap16 (a); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap32.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap32.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap32.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap32.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "lwbrx" } } */
+/* { dg-final { scan-assembler "stwbrx" } } */
+
+unsigned int ui;
+unsigned int load_bswap32 (unsigned int *p) { return __builtin_bswap32 (*p); }
+void store_bswap32 (unsigned int a) { ui = __builtin_bswap32 (a); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-1.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-1.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-1.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-1.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mno-popcntd -mcpu=power5" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-final { scan-assembler "lwbrx" } } */
+/* { dg-final { scan-assembler "stwbrx" } } */
+
+unsigned long ul;
+unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); }
+void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-2.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-2.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-2.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-2.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mpopcntd" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-final { scan-assembler "ldbrx" } } */
+/* { dg-final { scan-assembler "stdbrx" } } */
+
+unsigned long ul;
+unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); }
+void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-3.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-3.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-3.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-3.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mcpu=cell" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_ppu_ok } */
+/* { dg-final { scan-assembler "ldbrx" } } */
+/* { dg-final { scan-assembler "stdbrx" } } */
+
+unsigned long ul;
+unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); }
+void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-4.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-4.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap64-4.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap64-4.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mpowerpc64" } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-final { scan-assembler-times "lwbrx" 2 } } */
+/* { dg-final { scan-assembler-times "stwbrx" 2 } } */
+
+long long swap_load (long long *a) { return __builtin_bswap64 (*a); }
+long long swap_reg (long long a) { return __builtin_bswap64 (a); }
+void swap_store (long long *a, long long b) { *a = __builtin_bswap64 (b); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap-run.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap-run.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/bswap-run.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/bswap-run.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,102 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-options "-O2 -std=gnu99" } */
+
+extern void abort (void);
+
+static unsigned char bytes[] = { 0, 1, 2, 0x80, 0xff };
+
+unsigned short b16a (unsigned short *p) { return __builtin_bswap16 (*p); }
+void b16b (unsigned short *p, unsigned short a) { *p = __builtin_bswap16 (a); }
+int b16c (unsigned short a) { return __builtin_bswap16 (a); }
+
+unsigned int b32a (unsigned int *p) { return __builtin_bswap32 (*p); }
+void b32b (unsigned int *p, unsigned int a) { *p = __builtin_bswap32 (a); }
+static unsigned int b32c (unsigned int a) { return __builtin_bswap32 (a); }
+
+unsigned long long b64a (unsigned long long *p) { return __builtin_bswap64 (*p); }
+void b64b (unsigned long long *p, unsigned long long a) { *p = __builtin_bswap64 (a); }
+unsigned long long b64c (unsigned long long a) { return __builtin_bswap64 (a); }
+
+int
+main (void)
+{
+  unsigned i1, i2, i3, i4, i5;
+  unsigned b1, b2, b3, b4, b5;
+  unsigned short b16_inp, b16_exp, b16_var;
+  unsigned int b32_inp, b32_exp, b32_var;
+  unsigned long long b64_inp, b64_exp, b64_var;
+
+  for (i1 = 0; i1 < sizeof (bytes); i1++)
+    {
+      b1 = bytes[i1];
+      for (i2 = 0; i2 < sizeof (bytes); i2++)
+	{
+	  b2 = bytes[i2];
+	  b16_inp = (b1 << 8) | b2;
+	  b16_exp = (b2 << 8) | b1;
+
+	  if (b16a (&b16_inp) != b16_exp)
+	    abort ();
+
+	  b16b (&b16_var, b16_inp);
+	  if (b16_var != b16_exp)
+	    abort ();
+
+	  if (b16c (b16_inp) != b16_exp)
+	    abort ();
+
+	  for (i3 = 0; i3 < sizeof (bytes); i3++)
+	    {
+	      b3 = bytes[i3];
+	      for (i4 = 0; i4 < sizeof (bytes); i4++)
+		{
+		  b4 = bytes[i4];
+		  b32_inp = (b1 << 24) | (b2 << 16) | (b3 << 8) | b4;
+		  b32_exp = (b4 << 24) | (b3 << 16) | (b2 << 8) | b1;
+
+		  if (b32a (&b32_inp) != b32_exp)
+		    abort ();
+
+		  b32b (&b32_var, b32_inp);
+		  if (b32_var != b32_exp)
+		    abort ();
+
+		  if (b32c (b32_inp) != b32_exp)
+		    abort ();
+
+		  for (i5 = 0; i5 < sizeof (bytes); i5++)
+		    {
+		      b5 = bytes[i5];
+		      b64_inp = (((unsigned long long)b32_inp) << 32) | b5;
+		      b64_exp = (((unsigned long long)b5) << 56) | b32_exp;
+
+		      if (b64a (&b64_inp) != b64_exp)
+			abort ();
+
+		      b64b (&b64_var, b64_inp);
+		      if (b64_var != b64_exp)
+			abort ();
+
+		      if (b64c (b64_inp) != b64_exp)
+			abort ();
+
+		      b64_inp = (((unsigned long long)b5) << 56) | b32_inp;
+		      b64_exp = (((unsigned long long)b32_exp) << 32) | b5;
+
+		      if (b64a (&b64_inp) != b64_exp)
+			abort ();
+
+		      b64b (&b64_var, b64_inp);
+		      if (b64_var != b64_exp)
+			abort ();
+
+		      if (b64c (b64_inp) != b64_exp)
+			abort ();
+		    }
+		}
+	    }
+	}
+    }
+
+  return 0;
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/popcount-2.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/popcount-2.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/popcount-2.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/popcount-2.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7 -m32" } */
+/* { dg-final { scan-assembler "popcntw" } } */
+
+int foo(int x)
+{
+  return __builtin_popcount(x);
+}
+
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/popcount-3.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/popcount-3.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/popcount-3.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/popcount-3.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7 -m64" } */
+/* { dg-final { scan-assembler "popcntd" } } */
+
+long foo(int x)
+{
+  return __builtin_popcountl(x);
+}
+
+
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/pr39457.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/pr39457.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/pr39457.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/pr39457.c	2009-10-13 14:37:41.000000000 -0400
@@ -0,0 +1,56 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-m64 -O2 -mminimal-toc" } */
+
+/* PR 39457 -- fix breakage because the compiler ran out of registers and
+   wanted to stash a floating point value to the LR/CTR register.  */
+
+/* -O2 -m64 -mminimal-toc */
+typedef struct { void *s; } S;
+typedef void (*T1) (void);
+typedef void (*T2) (void *, void *, int, void *);
+char *fn1 (const char *, ...);
+void *fn2 (void);
+int fn3 (char *, int);
+int fn4 (const void *);
+int fn5 (const void *);
+long fn6 (void) __attribute__ ((__const__));
+int fn7 (void *, void *, void *);
+void *fn8 (void *, long);
+void *fn9 (void *, long, const char *, ...);
+void *fn10 (void *);
+long fn11 (void) __attribute__ ((__const__));
+long fn12 (void *, const char *, T1, T2, void *);
+void *fn13 (void *);
+long fn14 (void) __attribute__ ((__const__));
+extern void *v1;
+extern char *v2;
+extern int v3;
+
+void
+foo (void *x, char *z)
+{
+  void *i1, *i2;
+  int y;
+  if (v1)
+    return;
+  v1 = fn9 (fn10 (fn2 ()), fn6 (), "x", 0., "y", 0., 0);
+  y = 520 - (520 - fn4 (x)) / 2;
+  fn9 (fn8 (v1, fn6 ()), fn6 (), "wig", fn8 (v1, fn14 ()), "x", 18.0,
+       "y", 16.0, "wid", 80.0, "hi", 500.0, 0);
+  fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 80.0, "y2",
+       500.0, "f", fn3 ("fff", 0x0D0DFA00), 0);
+  fn13 (((S *) fn8 (v1, fn6 ()))->s);
+  fn12 (fn8 (v1, fn11 ()), "ev", (T1) fn7, 0, fn8 (v1, fn6 ()));
+  fn9 (fn8 (v1, fn6 ()), fn6 (), "wig",
+       fn8 (v1, fn14 ()), "x", 111.0, "y", 14.0, "wid", 774.0, "hi",
+       500.0, 0);
+  v1 = fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 774.0, "y2",
+            500.0, "f", fn3 ("gc", 0x0D0DFA00), 0);
+  fn1 (z, 0);
+  i1 = fn9 (fn8 (v1, fn6 ()), fn6 (), "pixbuf", x, "x",
+            800 - fn5 (x) / 2, "y", y - fn4 (x), 0);
+  fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, "/ok/");
+  fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, 0);
+  i2 = fn9 (fn8 (v1, fn6 ()), fn6 (), "txt", "OK", "fnt", v2, "x",
+            800, "y", y - fn4 (x) + 15, "ar", 0, "f", v3, 0);
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c	2009-10-13 13:05:57.000000000 -0400
@@ -0,0 +1,38 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvsubdp" } } */
+/* { dg-final { scan-assembler "xvmuldp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+/* { dg-final { scan-assembler "xvnmadd" } } */
+/* { dg-final { scan-assembler "xvnmsub" } } */
+/* { dg-final { scan-assembler "xvdivdp" } } */
+/* { dg-final { scan-assembler "xvmaxdp" } } */
+/* { dg-final { scan-assembler "xvmindp" } } */
+/* { dg-final { scan-assembler "xvsqrtdp" } } */
+/* { dg-final { scan-assembler "xvrsqrtedp" } } */
+/* { dg-final { scan-assembler "xvabsdp" } } */
+/* { dg-final { scan-assembler "xvnabsdp" } } */
+/* { dg-final { scan-assembler "xvredp" } } */
+
+void use_builtins (__vector double *p, __vector double *q, __vector double *r, __vector double *s)
+{
+  p[0] = __builtin_vsx_xvadddp (q[0], r[0]);
+  p[1] = __builtin_vsx_xvsubdp (q[1], r[1]);
+  p[2] = __builtin_vsx_xvmuldp (q[2], r[2]);
+  p[3] = __builtin_vsx_xvdivdp (q[3], r[3]);
+  p[4] = __builtin_vsx_xvmaxdp (q[4], r[4]);
+  p[5] = __builtin_vsx_xvmindp (q[5], r[5]);
+  p[6] = __builtin_vsx_xvabsdp (q[6]);
+  p[7] = __builtin_vsx_xvnabsdp (q[7]);
+  p[8] = __builtin_vsx_xvsqrtdp (q[8]);
+  p[9] = __builtin_vsx_xvmadddp (q[9], r[9], s[9]);
+  p[10] = __builtin_vsx_xvmsubdp (q[10], r[10], s[10]);
+  p[11] = __builtin_vsx_xvnmadddp (q[11], r[11], s[11]);
+  p[12] = __builtin_vsx_xvnmsubdp (q[12], r[12], s[12]);
+  p[13] = __builtin_vsx_xvredp (q[13]);
+  p[14] = __builtin_vsx_xvrsqrtedp (q[14]);
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,38 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvaddsp" } } */
+/* { dg-final { scan-assembler "xvsubsp" } } */
+/* { dg-final { scan-assembler "xvmulsp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+/* { dg-final { scan-assembler "xvnmadd" } } */
+/* { dg-final { scan-assembler "xvnmsub" } } */
+/* { dg-final { scan-assembler "xvdivsp" } } */
+/* { dg-final { scan-assembler "xvmaxsp" } } */
+/* { dg-final { scan-assembler "xvminsp" } } */
+/* { dg-final { scan-assembler "xvsqrtsp" } } */
+/* { dg-final { scan-assembler "xvabssp" } } */
+/* { dg-final { scan-assembler "xvnabssp" } } */
+/* { dg-final { scan-assembler "xvresp" } } */
+/* { dg-final { scan-assembler "xvrsqrtesp" } } */
+
+void use_builtins (__vector float *p, __vector float *q, __vector float *r, __vector float *s)
+{
+  p[0] = __builtin_vsx_xvaddsp (q[0], r[0]);
+  p[1] = __builtin_vsx_xvsubsp (q[1], r[1]);
+  p[2] = __builtin_vsx_xvmulsp (q[2], r[2]);
+  p[3] = __builtin_vsx_xvdivsp (q[3], r[3]);
+  p[4] = __builtin_vsx_xvmaxsp (q[4], r[4]);
+  p[5] = __builtin_vsx_xvminsp (q[5], r[5]);
+  p[6] = __builtin_vsx_xvabssp (q[6]);
+  p[7] = __builtin_vsx_xvnabssp (q[7]);
+  p[8] = __builtin_vsx_xvsqrtsp (q[8]);
+  p[9] = __builtin_vsx_xvmaddsp (q[9], r[9], s[9]);
+  p[10] = __builtin_vsx_xvmsubsp (q[10], r[10], s[10]);
+  p[11] = __builtin_vsx_xvnmaddsp (q[11], r[11], s[11]);
+  p[12] = __builtin_vsx_xvnmsubsp (q[12], r[12], s[12]);
+  p[13] = __builtin_vsx_xvresp (q[13]);
+  p[14] = __builtin_vsx_xvrsqrtesp (q[14]);
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,212 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxsel" } } */
+/* { dg-final { scan-assembler "vperm" } } */
+/* { dg-final { scan-assembler "xvrdpi" } } */
+/* { dg-final { scan-assembler "xvrdpic" } } */
+/* { dg-final { scan-assembler "xvrdpim" } } */
+/* { dg-final { scan-assembler "xvrdpip" } } */
+/* { dg-final { scan-assembler "xvrdpiz" } } */
+/* { dg-final { scan-assembler "xvrspi" } } */
+/* { dg-final { scan-assembler "xvrspic" } } */
+/* { dg-final { scan-assembler "xvrspim" } } */
+/* { dg-final { scan-assembler "xvrspip" } } */
+/* { dg-final { scan-assembler "xvrspiz" } } */
+/* { dg-final { scan-assembler "xsrdpi" } } */
+/* { dg-final { scan-assembler "xsrdpic" } } */
+/* { dg-final { scan-assembler "xsrdpim" } } */
+/* { dg-final { scan-assembler "xsrdpip" } } */
+/* { dg-final { scan-assembler "xsrdpiz" } } */
+/* { dg-final { scan-assembler "xsmaxdp" } } */
+/* { dg-final { scan-assembler "xsmindp" } } */
+/* { dg-final { scan-assembler "xxland" } } */
+/* { dg-final { scan-assembler "xxlandc" } } */
+/* { dg-final { scan-assembler "xxlnor" } } */
+/* { dg-final { scan-assembler "xxlor" } } */
+/* { dg-final { scan-assembler "xxlxor" } } */
+/* { dg-final { scan-assembler "xvcmpeqdp" } } */
+/* { dg-final { scan-assembler "xvcmpgtdp" } } */
+/* { dg-final { scan-assembler "xvcmpgedp" } } */
+/* { dg-final { scan-assembler "xvcmpeqsp" } } */
+/* { dg-final { scan-assembler "xvcmpgtsp" } } */
+/* { dg-final { scan-assembler "xvcmpgesp" } } */
+/* { dg-final { scan-assembler "xxsldwi" } } */
+/* { dg-final { scan-assembler-not "call" } } */
+
+extern __vector int si[][4];
+extern __vector short ss[][4];
+extern __vector signed char sc[][4];
+extern __vector float f[][4];
+extern __vector unsigned int ui[][4];
+extern __vector unsigned short us[][4];
+extern __vector unsigned char uc[][4];
+extern __vector __bool int bi[][4];
+extern __vector __bool short bs[][4];
+extern __vector __bool char bc[][4];
+extern __vector __pixel p[][4];
+#ifdef __VSX__
+extern __vector double d[][4];
+extern __vector long sl[][4];
+extern __vector unsigned long ul[][4];
+extern __vector __bool long bl[][4];
+#endif
+
+int do_sel(void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++;
+  ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++;
+  sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++;
+  f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++;
+  d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++;
+
+  si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++;
+  ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++;
+  sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++;
+  f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], bi[i][3]); i++;
+  d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], bl[i][3]); i++;
+
+  si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], ui[i][3]); i++;
+  ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], us[i][3]); i++;
+  sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], uc[i][3]); i++;
+  f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], ui[i][3]); i++;
+  d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], ul[i][3]); i++;
+
+  return i;
+}
+
+int do_perm(void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_vperm_4si (si[i][1], si[i][2], uc[i][3]); i++;
+  ss[i][0] = __builtin_vsx_vperm_8hi (ss[i][1], ss[i][2], uc[i][3]); i++;
+  sc[i][0] = __builtin_vsx_vperm_16qi (sc[i][1], sc[i][2], uc[i][3]); i++;
+  f[i][0] = __builtin_vsx_vperm_4sf (f[i][1], f[i][2], uc[i][3]); i++;
+  d[i][0] = __builtin_vsx_vperm_2df (d[i][1], d[i][2], uc[i][3]); i++;
+
+  si[i][0] = __builtin_vsx_vperm (si[i][1], si[i][2], uc[i][3]); i++;
+  ss[i][0] = __builtin_vsx_vperm (ss[i][1], ss[i][2], uc[i][3]); i++;
+  sc[i][0] = __builtin_vsx_vperm (sc[i][1], sc[i][2], uc[i][3]); i++;
+  f[i][0] = __builtin_vsx_vperm (f[i][1], f[i][2], uc[i][3]); i++;
+  d[i][0] = __builtin_vsx_vperm (d[i][1], d[i][2], uc[i][3]); i++;
+
+  return i;
+}
+
+int do_xxperm (void)
+{
+  int i = 0;
+
+  d[i][0] = __builtin_vsx_xxpermdi_2df (d[i][1], d[i][2], 0); i++;
+  d[i][0] = __builtin_vsx_xxpermdi (d[i][1], d[i][2], 1); i++;
+  return i;
+}
+
+double x, y;
+void do_concat (void)
+{
+  d[0][0] = __builtin_vsx_concat_2df (x, y);
+}
+
+void do_set (void)
+{
+  d[0][0] = __builtin_vsx_set_2df (d[0][1], x, 0);
+  d[1][0] = __builtin_vsx_set_2df (d[1][1], y, 1);
+}
+
+extern double z[][4];
+
+int do_math (void)
+{
+  int i = 0;
+
+  d[i][0] = __builtin_vsx_xvrdpi  (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpic (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpim (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpip (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpiz (d[i][1]); i++;
+
+  f[i][0] = __builtin_vsx_xvrspi  (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspic (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspim (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspip (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspiz (f[i][1]); i++;
+
+  z[i][0] = __builtin_vsx_xsrdpi  (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpic (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpim (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpip (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpiz (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsmaxdp (z[i][1], z[i][0]); i++;
+  z[i][0] = __builtin_vsx_xsmindp (z[i][1], z[i][0]); i++;
+  return i;
+}
+
+int do_cmp (void)
+{
+  int i = 0;
+
+  d[i][0] = __builtin_vsx_xvcmpeqdp (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xvcmpgtdp (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xvcmpgedp (d[i][1], d[i][2]); i++;
+
+  f[i][0] = __builtin_vsx_xvcmpeqsp (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xvcmpgtsp (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xvcmpgesp (f[i][1], f[i][2]); i++;
+  return i;
+}
+
+int do_logical (void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_xxland (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlandc (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlnor (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlor (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlxor (si[i][1], si[i][2]); i++;
+
+  ss[i][0] = __builtin_vsx_xxland (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlandc (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlnor (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlor (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlxor (ss[i][1], ss[i][2]); i++;
+
+  sc[i][0] = __builtin_vsx_xxland (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlandc (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlnor (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlor (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlxor (sc[i][1], sc[i][2]); i++;
+
+  d[i][0] = __builtin_vsx_xxland (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlandc (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlnor (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlor (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlxor (d[i][1], d[i][2]); i++;
+
+  f[i][0] = __builtin_vsx_xxland (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlandc (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlnor (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlor (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlxor (f[i][1], f[i][2]); i++;
+  return i;
+}
+
+int do_xxsldwi (void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_xxsldwi (si[i][1], si[i][2], 0); i++;
+  ss[i][0] = __builtin_vsx_xxsldwi (ss[i][1], ss[i][2], 1); i++;
+  sc[i][0] = __builtin_vsx_xxsldwi (sc[i][1], sc[i][2], 2); i++;
+  ui[i][0] = __builtin_vsx_xxsldwi (ui[i][1], ui[i][2], 3); i++;
+  us[i][0] = __builtin_vsx_xxsldwi (us[i][1], us[i][2], 0); i++;
+  uc[i][0] = __builtin_vsx_xxsldwi (uc[i][1], uc[i][2], 1); i++;
+  f[i][0] = __builtin_vsx_xxsldwi (f[i][1], f[i][2], 2); i++;
+  d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
+  return i;
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,142 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvcmpeqdp." } } */
+/* { dg-final { scan-assembler "xvcmpgtdp." } } */
+/* { dg-final { scan-assembler "xvcmpgedp." } } */
+/* { dg-final { scan-assembler "xvcmpeqsp." } } */
+/* { dg-final { scan-assembler "xvcmpgtsp." } } */
+/* { dg-final { scan-assembler "xvcmpgesp." } } */
+/* { dg-final { scan-assembler "vcmpbfp." } } */
+/* { dg-final { scan-assembler "vcmpequb." } } */
+/* { dg-final { scan-assembler "vcmpequh." } } */
+/* { dg-final { scan-assembler "vcmpequw." } } */
+/* { dg-final { scan-assembler "vcmpgtub." } } */
+/* { dg-final { scan-assembler "vcmpgtuh." } } */
+/* { dg-final { scan-assembler "vcmpgtuw." } } */
+/* { dg-final { scan-assembler "vcmpgtsb." } } */
+/* { dg-final { scan-assembler "vcmpgtsh." } } */
+/* { dg-final { scan-assembler "vcmpgtsw." } } */
+/* { dg-final { scan-assembler-not "vcmpeqfp" } } */
+/* { dg-final { scan-assembler-not "vcmpgtfp" } } */
+/* { dg-final { scan-assembler-not "vcmpgefp" } } */
+
+/* check that Altivec builtins generate VSX if -mvsx.  */
+
+#include <altivec.h>
+
+int *v16qi_s (vector signed char *a, vector signed char *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v16qi_u (vector unsigned char *a, vector unsigned char *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v8hi_s (vector short *a, vector short *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v8hi_u (vector unsigned short *a, vector unsigned short *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v4si_s (vector int *a, vector int *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v4si_u (vector unsigned int *a, vector unsigned int *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v4sf (vector float *a, vector float *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 3;
+
+  if (vec_all_in (*a, *b))	/* veccmpbfp. */
+    *p++ = 4;
+
+  return p;
+}
+
+int *v2df (vector double *a, vector double *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 3;
+
+  return p;
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+
+/* Make sure double extract doesn't use a store instruction.  */
+
+#include <altivec.h>
+
+double d0(__vector double v){ return __builtin_vec_extract (v, 0); }
+double d1(__vector double v){ return __builtin_vec_extract (v, 1); }
+
+double e0(vector double v){ return __builtin_vec_ext_v2df (v, 0); }
+double e1(vector double v){ return __builtin_vec_ext_v2df (v, 1); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,146 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Check whether tdiv and tsqrt instructions generate the correct code.  */
+/* Each of the *tdiv* and *tsqrt* instructions should be generated exactly 3
+   times (the two calls in the _1 function should be combined).  */
+/* { dg-final { scan-assembler-times "xstdivdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtdivdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtdivsp" 3 } } */
+/* { dg-final { scan-assembler-times "xstsqrtdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtsqrtdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtsqrtsp" 3 } } */
+
+void test_div_df_1 (double a, double b, int *p)
+{
+  p[0] = __builtin_vsx_xstdivdp_fe (a, b);
+  p[1] = __builtin_vsx_xstdivdp_fg (a, b);
+}
+
+int *test_div_df_2 (double a, double b, int *p)
+{
+  if (__builtin_vsx_xstdivdp_fe (a, b))
+    *p++ = 1;
+  
+  return p;
+}
+
+int *test_div_df_3 (double a, double b, int *p)
+{
+  if (__builtin_vsx_xstdivdp_fg (a, b))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_sqrt_df_1 (double a, int *p)
+{
+  p[0] = __builtin_vsx_xstsqrtdp_fe (a);
+  p[1] = __builtin_vsx_xstsqrtdp_fg (a);
+}
+
+int *test_sqrt_df_2 (double a, int *p)
+{
+  if (__builtin_vsx_xstsqrtdp_fe (a))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_sqrt_df_3 (double a, int *p)
+{
+  if (__builtin_vsx_xstsqrtdp_fg (a))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_div_v2df_1 (__vector double *a, __vector double *b, int *p)
+{
+  p[0] = __builtin_vsx_xvtdivdp_fe (*a, *b);
+  p[1] = __builtin_vsx_xvtdivdp_fg (*a, *b);
+}
+
+int *test_div_v2df_2 (__vector double *a, __vector double *b, int *p)
+{
+  if (__builtin_vsx_xvtdivdp_fe (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_div_v2df_3 (__vector double *a, __vector double *b, int *p)
+{
+  if (__builtin_vsx_xvtdivdp_fg (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_sqrt_v2df_1 (__vector double *a, int *p)
+{
+  p[0] = __builtin_vsx_xvtsqrtdp_fe (*a);
+  p[1] = __builtin_vsx_xvtsqrtdp_fg (*a);
+}
+
+int *test_sqrt_v2df_2 (__vector double *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtdp_fe (*a))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_sqrt_v2df_3 (__vector double *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtdp_fg (*a))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_div_v4sf_1 (__vector float *a, __vector float *b, int *p)
+{
+  p[0] = __builtin_vsx_xvtdivsp_fe (*a, *b);
+  p[1] = __builtin_vsx_xvtdivsp_fg (*a, *b);
+}
+
+int *test_div_v4sf_2 (__vector float *a, __vector float *b, int *p)
+{
+  if (__builtin_vsx_xvtdivsp_fe (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_div_v4sf_3 (__vector float *a, __vector float *b, int *p)
+{
+  if (__builtin_vsx_xvtdivsp_fg (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_sqrt_v4sf_1 (__vector float *a, int *p)
+{
+  p[0] = __builtin_vsx_xvtsqrtsp_fe (*a);
+  p[1] = __builtin_vsx_xvtsqrtsp_fg (*a);
+}
+
+int *test_sqrt_v4sf_2 (__vector float *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtsp_fe (*a))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_sqrt_v4sf_3 (__vector float *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtsp_fg (*a))
+    *p++ = 1;
+
+  return p;
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,150 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Test simple extract/insert/slat operations.  Make sure all types are
+   supported with various options.  */
+
+#include <altivec.h>
+
+double extract_df_0_reg (vector double p) { return vec_extract (p, 0); }
+double extract_df_1_reg (vector double p) { return vec_extract (p, 1); }
+double extract_df_n_reg (vector double p, int n) { return vec_extract (p, n); }
+
+double extract_df_0_mem (vector double *p) { return vec_extract (*p, 0); }
+double extract_df_1_mem (vector double *p) { return vec_extract (*p, 1); }
+double extract_df_n_mem (vector double *p, int n) { return vec_extract (*p, n); }
+
+vector double insert_df_0 (vector double p, double x) { return vec_insert (x, p, 0); }
+vector double insert_df_1 (vector double p, double x) { return vec_insert (x, p, 1); }
+vector double insert_df_n (vector double p, double x, int n) { return vec_insert (x, p, n); }
+
+vector double splat_df_reg (double x) { return vec_splats (x); }
+vector double splat_df_mem (double *x) { return vec_splats (*x); }
+
+#ifdef _ARCH_PPC64
+#define ll long
+#else
+#define ll long long
+#endif
+
+ll extract_di_0_reg (vector ll p) { return vec_extract (p, 0); }
+ll extract_di_1_reg (vector ll p) { return vec_extract (p, 1); }
+ll extract_di_n_reg (vector ll p, int n) { return vec_extract (p, n); }
+
+ll extract_di_0_mem (vector ll *p) { return vec_extract (*p, 0); }
+ll extract_di_1_mem (vector ll *p) { return vec_extract (*p, 1); }
+ll extract_di_n_mem (vector ll *p, int n) { return vec_extract (*p, n); }
+
+vector ll insert_di_0 (vector ll p, ll x) { return vec_insert (x, p, 0); }
+vector ll insert_di_1 (vector ll p, ll x) { return vec_insert (x, p, 1); }
+vector ll insert_di_n (vector ll p, ll x, int n) { return vec_insert (x, p, n); }
+
+vector ll splat_di_reg (ll x) { return vec_splats (x); }
+vector ll splat_di_mem (ll *x) { return vec_splats (*x); }
+
+float extract_sf_0_reg (vector float p) { return vec_extract (p, 0); }
+float extract_sf_3_reg (vector float p) { return vec_extract (p, 3); }
+float extract_sf_n_reg (vector float p, int n) { return vec_extract (p, n); }
+
+float extract_sf_0_mem (vector float *p) { return vec_extract (*p, 0); }
+float extract_sf_3_mem (vector float *p) { return vec_extract (*p, 3); }
+float extract_sf_n_mem (vector float *p, int n) { return vec_extract (*p, n); }
+
+vector float insert_sf_0 (vector float p, float x) { return vec_insert (x, p, 0); }
+vector float insert_sf_3 (vector float p, float x) { return vec_insert (x, p, 3); }
+vector float insert_sf_n (vector float p, float x, int n) { return vec_insert (x, p, n); }
+
+vector float splat_sf_reg (float x) { return vec_splats (x); }
+vector float splat_sf_mem (float *x) { return vec_splats (*x); }
+
+int extract_si_0_reg (vector int p) { return vec_extract (p, 0); }
+int extract_si_3_reg (vector int p) { return vec_extract (p, 3); }
+int extract_si_n_reg (vector int p, int n) { return vec_extract (p, n); }
+
+int extract_si_0_mem (vector int *p) { return vec_extract (*p, 0); }
+int extract_si_3_mem (vector int *p) { return vec_extract (*p, 3); }
+int extract_si_n_mem (vector int *p, int n) { return vec_extract (*p, n); }
+
+vector int insert_si_0 (vector int p, int x) { return vec_insert (x, p, 0); }
+vector int insert_si_3 (vector int p, int x) { return vec_insert (x, p, 3); }
+vector int insert_si_n (vector int p, int x, int n) { return vec_insert (x, p, n); }
+
+vector int splat_si_reg (int x) { return vec_splats (x); }
+vector int splat_si_mem (int *x) { return vec_splats (*x); }
+
+unsigned int extract_usi_0_reg (vector unsigned int p) { return vec_extract (p, 0); }
+unsigned int extract_usi_3_reg (vector unsigned int p) { return vec_extract (p, 3); }
+unsigned int extract_usi_n_reg (vector unsigned int p, int n) { return vec_extract (p, n); }
+
+unsigned int extract_usi_0_mem (vector unsigned int *p) { return vec_extract (*p, 0); }
+unsigned int extract_usi_3_mem (vector unsigned int *p) { return vec_extract (*p, 3); }
+unsigned int extract_usi_n_mem (vector unsigned int *p, int n) { return vec_extract (*p, n); }
+
+vector unsigned int insert_usi_0 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 0); }
+vector unsigned int insert_usi_3 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 3); }
+vector unsigned int insert_usi_n (vector unsigned int p, unsigned int x, int n) { return vec_insert (x, p, n); }
+
+vector unsigned int splat_usi_reg (unsigned int x) { return vec_splats (x); }
+vector unsigned int splat_usi_mem (unsigned int *x) { return vec_splats (*x); }
+
+short extract_hi_0_reg (vector short p) { return vec_extract (p, 0); }
+short extract_hi_7_reg (vector short p) { return vec_extract (p, 7); }
+short extract_hi_n_reg (vector short p, int n) { return vec_extract (p, n); }
+
+short extract_hi_0_mem (vector short *p) { return vec_extract (*p, 0); }
+short extract_hi_7_mem (vector short *p) { return vec_extract (*p, 7); }
+short extract_hi_n_mem (vector short *p, int n) { return vec_extract (*p, n); }
+
+vector short insert_hi_0 (vector short p, short x) { return vec_insert (x, p, 0); }
+vector short insert_hi_7 (vector short p, short x) { return vec_insert (x, p, 7); }
+vector short insert_hi_n (vector short p, short x, int n) { return vec_insert (x, p, n); }
+
+vector short splat_hi_reg (short x) { return vec_splats (x); }
+vector short splat_hi_mem (short *x) { return vec_splats (*x); }
+
+unsigned short extract_uhi_0_reg (vector unsigned short p) { return vec_extract (p, 0); }
+unsigned short extract_uhi_7_reg (vector unsigned short p) { return vec_extract (p, 7); }
+unsigned short extract_uhi_n_reg (vector unsigned short p, int n) { return vec_extract (p, n); }
+
+unsigned short extract_uhi_0_mem (vector unsigned short *p) { return vec_extract (*p, 0); }
+unsigned short extract_uhi_7_mem (vector unsigned short *p) { return vec_extract (*p, 7); }
+unsigned short extract_uhi_n_mem (vector unsigned short *p, int n) { return vec_extract (*p, n); }
+
+vector unsigned short insert_uhi_0 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 0); }
+vector unsigned short insert_uhi_7 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 7); }
+vector unsigned short insert_uhi_n (vector unsigned short p, unsigned short x, int n) { return vec_insert (x, p, n); }
+
+vector unsigned short splat_uhi_reg (unsigned short x) { return vec_splats (x); }
+vector unsigned short splat_uhi_mem (unsigned short *x) { return vec_splats (*x); }
+
+signed char extract_qi_0_reg (vector signed char p) { return vec_extract (p, 0); }
+signed char extract_qi_1_reg5 (vector signed char p) { return vec_extract (p, 15); }
+signed char extract_qi_n_reg (vector signed char p, int n) { return vec_extract (p, n); }
+
+signed char extract_qi_0_mem (vector signed char *p) { return vec_extract (*p, 0); }
+signed char extract_qi_1_mem5 (vector signed char *p) { return vec_extract (*p, 15); }
+signed char extract_qi_n_mem (vector signed char *p, int n) { return vec_extract (*p, n); }
+
+vector signed char insert_qi_0 (vector signed char p, signed char x) { return vec_insert (x, p, 0); }
+vector signed char insert_qi_15 (vector signed char p, signed char x) { return vec_insert (x, p, 15); }
+vector signed char insert_qi_n (vector signed char p, signed char x, int n) { return vec_insert (x, p, n); }
+
+vector signed char splat_qi_reg (signed char x) { return vec_splats (x); }
+vector signed char splat_qi_mem (signed char *x) { return vec_splats (*x); }
+
+unsigned char extract_uqi_0_reg (vector unsigned char p) { return vec_extract (p, 0); }
+unsigned char extract_uqi_1_reg5 (vector unsigned char p) { return vec_extract (p, 15); }
+unsigned char extract_uqi_n_reg (vector unsigned char p, int n) { return vec_extract (p, n); }
+
+unsigned char extract_uqi_0_mem (vector unsigned char *p) { return vec_extract (*p, 0); }
+unsigned char extract_uqi_1_mem5 (vector unsigned char *p) { return vec_extract (*p, 15); }
+unsigned char extract_uqi_n_mem (vector unsigned char *p, int n) { return vec_extract (*p, n); }
+
+vector unsigned char insert_uqi_0 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 0); }
+vector unsigned char insert_uqi_15 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 15); }
+vector unsigned char insert_uqi_n (vector unsigned char p, unsigned char x, int n) { return vec_insert (x, p, n); }
+
+vector unsigned char splat_uqi_reg (unsigned char x) { return vec_splats (x); }
+vector unsigned char splat_uqi_mem (unsigned char *x) { return vec_splats (*x); }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,74 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -m64" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvsubdp" } } */
+/* { dg-final { scan-assembler "xvmuldp" } } */
+/* { dg-final { scan-assembler "xvdivdp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double a[SIZE] __attribute__((__aligned__(32)));
+double b[SIZE] __attribute__((__aligned__(32)));
+double c[SIZE] __attribute__((__aligned__(32)));
+double d[SIZE] __attribute__((__aligned__(32)));
+double e[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+void
+vector_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
+void
+vector_multiply (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] * c[i];
+}
+
+void
+vector_multiply_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) + d[i];
+}
+
+void
+vector_multiply_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) - d[i];
+}
+
+void
+vector_divide (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] / c[i];
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,74 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -m64" } */
+/* { dg-final { scan-assembler "xvaddsp" } } */
+/* { dg-final { scan-assembler "xvsubsp" } } */
+/* { dg-final { scan-assembler "xvmulsp" } } */
+/* { dg-final { scan-assembler "xvdivsp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+float d[SIZE] __attribute__((__aligned__(32)));
+float e[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+void
+vector_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
+void
+vector_multiply (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] * c[i];
+}
+
+void
+vector_multiply_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) + d[i];
+}
+
+void
+vector_multiply_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) - d[i];
+}
+
+void
+vector_divide (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] / c[i];
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -m64" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvsubdp" } } */
+/* { dg-final { scan-assembler "xvmuldp" } } */
+/* { dg-final { scan-assembler "xvdivdp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+
+__vector double a, b, c, d;
+
+void
+vector_add (void)
+{
+  a = b + c;
+}
+
+void
+vector_subtract (void)
+{
+  a = b - c;
+}
+
+void
+vector_multiply (void)
+{
+  a = b * c;
+}
+
+void
+vector_multiply_add (void)
+{
+  a = (b * c) + d;
+}
+
+void
+vector_multiply_subtract (void)
+{
+  a = (b * c) - d;
+}
+
+void
+vector_divide (void)
+{
+  a = b / c;
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c
--- sles-11sp1-orig/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c	1969-12-31 19:00:00.000000000 -0500
+++ sles-11sp1/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c	2009-10-13 13:05:58.000000000 -0400
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -m64" } */
+/* { dg-final { scan-assembler "xvaddsp" } } */
+/* { dg-final { scan-assembler "xvsubsp" } } */
+/* { dg-final { scan-assembler "xvmulsp" } } */
+/* { dg-final { scan-assembler "xvdivsp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+
+__vector float a, b, c, d;
+
+void
+vector_add (void)
+{
+  a = b + c;
+}
+
+void
+vector_subtract (void)
+{
+  a = b - c;
+}
+
+void
+vector_multiply (void)
+{
+  a = b * c;
+}
+
+void
+vector_multiply_add (void)
+{
+  a = (b * c) + d;
+}
+
+void
+vector_multiply_subtract (void)
+{
+  a = (b * c) - d;
+}
+
+void
+vector_divide (void)
+{
+  a = b / c;
+}
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/g++.dg/ext/altivec-2.C sles-11sp1/gcc/testsuite/g++.dg/ext/altivec-2.C
--- sles-11sp1-orig/gcc/testsuite/g++.dg/ext/altivec-2.C	2008-02-19 04:54:07.000000000 -0500
+++ sles-11sp1/gcc/testsuite/g++.dg/ext/altivec-2.C	2009-10-12 19:47:54.000000000 -0400
@@ -8,6 +8,8 @@
 #include <altivec.h>
 #include "altivec_check.h"
 
+vector unsigned char use_lvsl;
+
 int main (int argc, const char * argv[])
 {
   int i;
@@ -20,7 +22,7 @@ int main (int argc, const char * argv[])
   vec_dst(&cv, i, 0);
   v = vec_ld(0, &cv);	
   v = vec_lde(0, &cf);
-  vec_lvsl(0, &cf);
+  use_lvsl = vec_lvsl(0, &cf);
   
   return 0;
 }
diff -rupN --exclude='*~' --exclude=autom4te.cache sles-11sp1-orig/gcc/testsuite/lib/target-supports.exp sles-11sp1/gcc/testsuite/lib/target-supports.exp
--- sles-11sp1-orig/gcc/testsuite/lib/target-supports.exp	2009-10-09 17:11:23.000000000 -0400
+++ sles-11sp1/gcc/testsuite/lib/target-supports.exp	2009-10-13 13:08:03.000000000 -0400
@@ -1,4 +1,4 @@
-#   Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007
+#   Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009
 #    Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
@@ -794,6 +794,32 @@ proc check_sse2_hw_available { } {
     }]
 }
 
+# Return 1 if the target supports executing VSX instructions, 0
+# otherwise.  Cache the result.
+
+proc check_vsx_hw_available { } {
+    return [check_cached_effective_target vsx_hw_available {
+	# Some simulators are known to not support VSX instructions.
+	# For now, disable on Darwin
+	if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
+	    expr 0
+	} else {
+	    set options "-mvsx"
+	    check_runtime_nocache vsx_hw_available {
+		int main()
+		{
+		#ifdef __MACH__
+		  asm volatile ("xxlor vs0,vs0,vs0");
+		#else
+		  asm volatile ("xxlor 0,0,0");
+	        #endif
+		  return 0;
+		}
+	    } $options
+	}
+    }]
+}
+
 # Return 1 if the target supports executing AltiVec instructions, 0
 # otherwise.  Cache the result.
 
@@ -804,12 +830,13 @@ proc check_vmx_hw_available { } {
 	    expr 0
 	} else {
 	    # Most targets don't require special flags for this test case, but
-	    # Darwin does.
+	    # Darwin does.  Just to be sure, make sure VSX is not enabled for
+	    # the altivec tests.
 	    if { [istarget *-*-darwin*]
 		 || [istarget *-*-aix*] } {
-		set options "-maltivec"
+		set options "-maltivec -mno-vsx"
 	    } else {
-		set options ""
+		set options "-mno-vsx"
 	    }
 	    check_runtime_nocache vmx_hw_available {
 		int main()
@@ -826,6 +853,99 @@ proc check_vmx_hw_available { } {
     }]
 }
 
+# Return 1 if the target supports executing AltiVec and Cell PPU
+# instructions, 0 otherwise.  Cache the result.
+
+proc check_effective_target_cell_hw { } {
+    return [check_cached_effective_target cell_hw_available {
+	# Some simulators are known to not support VMX and PPU instructions.
+	if { [istarget powerpc-*-eabi*] } {
+	    expr 0
+	} else {
+	    # Most targets don't require special flags for this test
+	    # case, but Darwin and AIX do.
+	    if { [istarget *-*-darwin*]
+		 || [istarget *-*-aix*] } {
+		set options "-maltivec -mcpu=cell"
+	    } else {
+		set options "-mcpu=cell"
+	    }
+	    check_runtime_nocache cell_hw_available {
+		int main()
+		{
+		#ifdef __MACH__
+		  asm volatile ("vor v0,v0,v0");
+                  asm volatile ("lvlx v0,r0,r0");
+		#else
+		  asm volatile ("vor 0,0,0");
+                  asm volatile ("lvlx 0,0,0");
+	        #endif
+		  return 0;
+		}
+	    } $options
+	}
+    }]
+}
+
+# Return 1 if the target supports executing 64-bit instructions, 0
+# otherwise.  Cache the result.
+
+proc check_effective_target_powerpc64 { } {
+    global powerpc64_available_saved
+    global tool
+
+    if [info exists powerpc64_available_saved] {
+	verbose "check_effective_target_powerpc64 returning saved $powerpc64_available_saved" 2
+    } else {
+	set powerpc64_available_saved 0
+
+	# Some simulators are known to not support powerpc64 instructions.
+	if { [istarget powerpc-*-eabi*] || [istarget powerpc-ibm-aix*] } {
+	    verbose "check_effective_target_powerpc64 returning 0" 2
+	    return $powerpc64_available_saved
+	}
+
+	# Set up, compile, and execute a test program containing a 64-bit
+	# instruction.  Include the current process ID in the file
+	# names to prevent conflicts with invocations for multiple
+	# testsuites.
+	set src ppc[pid].c
+	set exe ppc[pid].x
+
+	set f [open $src "w"]
+	puts $f "int main() {"
+	puts $f "#ifdef __MACH__"
+	puts $f "  asm volatile (\"extsw r0,r0\");"
+	puts $f "#else"
+	puts $f "  asm volatile (\"extsw 0,0\");"
+	puts $f "#endif"
+	puts $f "  return 0; }"
+	close $f
+
+	set opts "additional_flags=-mcpu=G5"
+
+	verbose "check_effective_target_powerpc64 compiling testfile $src" 2
+	set lines [${tool}_target_compile $src $exe executable "$opts"]
+	file delete $src
+
+	if [string match "" $lines] then {
+	    # No error message, compilation succeeded.
+	    set result [${tool}_load "./$exe" "" ""]
+	    set status [lindex $result 0]
+	    remote_file build delete $exe
+	    verbose "check_effective_target_powerpc64 testfile status is <$status>" 2
+
+	    if { $status == "pass" } then {
+		set powerpc64_available_saved 1
+	    }
+	} else {
+	    verbose "check_effective_target_powerpc64 testfile compilation failed" 2
+	}
+    }
+
+    return $powerpc64_available_saved
+}
+
 # GCC 3.4.0 for powerpc64-*-linux* included an ABI fix for passing
 # complex float arguments.  This affects gfortran tests that call cabsf
 # in libm built by an earlier compiler.  Return 1 if libm uses the same
@@ -1001,6 +1121,18 @@ proc check_effective_target_lp64 { } {
     }]
 }
 
+# Return 1 if we're generating 64-bit code using default llp64 options,
+# 0 otherwise.
+
+proc check_effective_target_llp64 { } {
+    return [check_no_compiler_messages llp64 object {
+	int dummy[sizeof (int) == 4
+		  && sizeof (void *) == 8
+		  && sizeof (long long) == 8
+		  && sizeof (long) == 4 ? 1 : -1];
+    }]
+}
+
 # Return 1 if the target supports long double larger than double,
 # 0 otherwise.
 
@@ -1086,7 +1218,8 @@ proc check_effective_target_vect_cmdline
 	verbose "check_effective_target_vect_cmdline_needed: using cached result" 2
     } else {
 	set et_vect_cmdline_needed_saved 1
-	if { [istarget ia64-*-*]
+	if { [istarget alpha*-*-*]
+	     || [istarget ia64-*-*]
 	     || (([istarget x86_64-*-*] || [istarget i?86-*-*])
 		 && [check_effective_target_lp64])
 	     || ([istarget powerpc*-*-*]
@@ -1332,6 +1465,52 @@ proc check_effective_target_powerpc_alti
     }
 }
 
+# Return 1 if this is a PowerPC target supporting -mvsx
+
+proc check_effective_target_powerpc_vsx_ok { } {
+    if { ([istarget powerpc*-*-*]
+         && ![istarget powerpc-*-linux*paired*])
+	 || [istarget rs6000-*-*] } {
+	# AltiVec is not supported on AIX before 5.3.
+	if { [istarget powerpc*-*-aix4*]
+	     || [istarget powerpc*-*-aix5.1*] 
+	     || [istarget powerpc*-*-aix5.2*] } {
+	    return 0
+	}
+	return [check_no_compiler_messages powerpc_vsx_ok object {
+	    int main (void) {
+#ifdef __MACH__
+		asm volatile ("xxlor vs0,vs0,vs0");
+#else
+		asm volatile ("xxlor 0,0,0");
+#endif
+		return 0;
+	    }
+	} "-mvsx"]
+    } else {
+	return 0
+    }
+}
+
+# Return 1 if this is a PowerPC target supporting -mcpu=cell.
+
+proc check_effective_target_powerpc_ppu_ok { } {
+    if [check_effective_target_powerpc_altivec_ok] {
+	return [check_no_compiler_messages cell_asm_available object {
+	    int main (void) {
+#ifdef __MACH__
+		asm volatile ("lvlx v0,v0,v0");
+#else
+		asm volatile ("lvlx 0,0,0");
+#endif
+		return 0;
+	    }
+	}]
+    } else {
+	return 0
+    }
+}
+
 # Return 1 if this is a PowerPC target that supports SPU.
 
 proc check_effective_target_powerpc_spu { } {
@@ -1342,6 +1521,23 @@ proc check_effective_target_powerpc_spu 
     }
 }
 
+# Return 1 if this is a PowerPC SPE target.  The check includes options
+# specified by dg-options for this test, so don't cache the result.
+
+proc check_effective_target_powerpc_spe_nocache { } {
+    if { [istarget powerpc*-*-*] } {
+	return [check_no_compiler_messages_nocache powerpc_spe object {
+	    #ifndef __SPE__
+	    #error not SPE
+	    #else
+	    int dummy;
+	    #endif
+	} [current_compiler_flags]]
+    } else {
+	return 0
+    }
+}
+
 # Return 1 if this is a PowerPC target with SPE enabled.
 
 proc check_effective_target_powerpc_spe { } {
@@ -1374,6 +1570,23 @@ proc check_effective_target_powerpc_alti
     }
 }
 
+# Return 1 if this is a PowerPC 405 target.  The check includes options
+# specified by dg-options for this test, so don't cache the result.
+
+proc check_effective_target_powerpc_405_nocache { } {
+    if { [istarget powerpc*-*-*] || [istarget rs6000-*-*] } {
+	return [check_no_compiler_messages_nocache powerpc_405 object {
+	    #ifdef __PPC405__
+	    int dummy;
+	    #else
+	    #error not a PPC405
+	    #endif
+	} [current_compiler_flags]]
+    } else {
+	return 0
+    }
+}
+
 # Return 1 if this is a SPU target with a toolchain that
 # supports automatic overlay generation.
 
@@ -1768,7 +1981,8 @@ proc check_effective_target_vect_pack_tr
         set et_vect_pack_trunc_saved 0
         if { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
              || [istarget i?86-*-*]
-             || [istarget x86_64-*-*] } {
+             || [istarget x86_64-*-*]
+             || [istarget spu-*-*] } {
             set et_vect_pack_trunc_saved 1
         }
     }
@@ -1790,7 +2004,8 @@ proc check_effective_target_vect_unpack 
         set et_vect_unpack_saved 0
         if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
              || [istarget i?86-*-*]
-             || [istarget x86_64-*-*] } {
+             || [istarget x86_64-*-*] 
+             || [istarget spu-*-*] } {
             set et_vect_unpack_saved 1
         }
     }
@@ -1999,8 +2214,10 @@ proc check_effective_target_vect_short_m
     } else {
 	set et_vect_short_mult_saved 0
 	if { [istarget ia64-*-*]
+	     || [istarget spu-*-*]
 	     || [istarget i?86-*-*]
-	     || [istarget x86_64-*-*] } {
+	     || [istarget x86_64-*-*] 
+             || [istarget powerpc*-*-*]  } {
 	   set et_vect_short_mult_saved 1
 	}
     }
@@ -2039,7 +2256,8 @@ proc check_effective_target_vect_extract
         verbose "check_effective_target_vect_extract_even_odd: using cached result" 2
     } else {
         set et_vect_extract_even_odd_saved 0 
-        if { [istarget powerpc*-*-*] } {
+        if { [istarget powerpc*-*-*]
+             || [istarget spu-*-*] } {
            set et_vect_extract_even_odd_saved 1
         }
     }
@@ -2080,7 +2298,8 @@ proc check_effective_target_vect_interle
         set et_vect_interleave_saved 0
         if { [istarget powerpc*-*-*]
              || [istarget i?86-*-*]
-             || [istarget x86_64-*-*] } {
+             || [istarget x86_64-*-*]
+             || [istarget spu-*-*] } {
            set et_vect_interleave_saved 1
         }
     }

Places

File gcc-power7-sles-11sp1.patch02d of Package gcc43 (Revision 726ce42732b30905b8a30ec20fa41c83)

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