File gcc48-ibm-power8-fixes3.diff of Package libffi48

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File gcc48-ibm-power8-fixes3.diff of Package libffi48 (Revision 7e1fcf754a01582fbe3b5965022cae17)

Currently displaying revision 7e1fcf754a01582fbe3b5965022cae17 , Show latest

Pull fixes from IBM 4.8 branch, -r208054:208288

2014-03-03  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

Backport from mainline r208287
	2014-03-03  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow
	reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax
	constraint on constants to permit them being loaded into
	GENERAL_REGS or BASE_REGS.

2014-02-26  Alan Modra  <amodra@gmail.com>

Apply mainline r207798
	PR target/58675
	PR target/57935
	* config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use
	find_replacement on parts of insn rtl that might be reloaded.

2014-02-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/vector.md (*vector_unordered<mode>): Change split
	to use canonical form for nor<mode>3.

2014-02-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

Backport from mainline 208120
	2014-02-25  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* gcc.dg/vmx/ld-vsx.c: Don't use vec_all_eq.
	* gcc.dg/vmx/ld-vsx-be-order.c: Likewise.
	* gcc.dg/vmx/ldl-vsx.c: Likewise.
	* gcc.dg/vmx/ldl-vsx-be-order.c: Likewise.
	* gcc.dg/vmx/merge-vsx.c: Likewise.
	* gcc.dg/vmx/merge-vsx-be-order.c: Likewise.

Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c
===================================================================
--- gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c	(revision 208054)
+++ gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c	(revision 208288)
@@ -29,12 +29,16 @@ static void test ()
 
   vector unsigned long vul;
   vector double vd;
+  unsigned i;
 
   init ();
 
   vul = vec_ldl (0, (vector unsigned long *)svul);
   vd  = vec_ldl (0, (vector double *)svd);
 
-  check (vec_all_eq (vul, evul), "vul");
-  check (vec_all_eq (vd,  evd ), "vd" );
+  for (i = 0; i < 2; ++i)
+    {
+      check (vul[i] == evul[i], "vul");
+      check (vd[i]  == evd[i],  "vd" );
+    }
 }
Index: gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c
===================================================================
--- gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c	(revision 208054)
+++ gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c	(revision 208288)
@@ -29,12 +29,16 @@ static void test ()
 
   vector unsigned long vul;
   vector double vd;
+  unsigned i;
 
   init ();
 
   vul = vec_ld (0, (vector unsigned long *)svul);
   vd  = vec_ld (0, (vector double *)svd);
 
-  check (vec_all_eq (vul, evul), "vul");
-  check (vec_all_eq (vd,  evd ), "vd" );
+  for (i = 0; i < 2; ++i)
+    {
+      check (vul[i] == evul[i], "vul");
+      check (vd[i]  == evd[i],  "vd" );
+    }
 }
Index: gcc/testsuite/gcc.dg/vmx/ld-vsx.c
===================================================================
--- gcc/testsuite/gcc.dg/vmx/ld-vsx.c	(revision 208054)
+++ gcc/testsuite/gcc.dg/vmx/ld-vsx.c	(revision 208288)
@@ -24,12 +24,16 @@ static void test ()
 
   vector unsigned long vul;
   vector double vd;
+  unsigned i;
 
   init ();
 
   vul = vec_ld (0, (vector unsigned long *)svul);
   vd  = vec_ld (0, (vector double *)svd);
 
-  check (vec_all_eq (vul, evul), "vul");
-  check (vec_all_eq (vd,  evd ), "vd" );
+  for (i = 0; i < 2; ++i)
+    {
+      check (vul[i] == evul[i], "vul");
+      check (vd[i]  == evd[i],  "vd" );
+    }
 }
Index: gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c
===================================================================
--- gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c	(revision 208054)
+++ gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c	(revision 208288)
@@ -9,6 +9,11 @@ static int vec_long_eq (vector long x, v
   return (x[0] == y[0] && x[1] == y[1]);
 }
 
+static int vec_double_eq (vector double x, vector double y)
+{
+  return (x[0] == y[0] && x[1] == y[1]);
+}
+
 static void test()
 {
   /* Input vectors.  */
@@ -41,6 +46,6 @@ static void test()
 
   check (vec_long_eq (vlh, vlrh), "vlh");
   check (vec_long_eq (vll, vlrl), "vll");
-  check (vec_all_eq (vdh, vdrh), "vdh" );
-  check (vec_all_eq (vdl, vdrl), "vdl" );
+  check (vec_double_eq (vdh, vdrh), "vdh" );
+  check (vec_double_eq (vdl, vdrl), "vdl" );
 }
Index: gcc/testsuite/gcc.dg/vmx/ldl-vsx.c
===================================================================
--- gcc/testsuite/gcc.dg/vmx/ldl-vsx.c	(revision 208054)
+++ gcc/testsuite/gcc.dg/vmx/ldl-vsx.c	(revision 208288)
@@ -24,12 +24,16 @@ static void test ()
 
   vector unsigned long vul;
   vector double vd;
+  unsigned i;
 
   init ();
 
   vul = vec_ldl (0, (vector unsigned long *)svul);
   vd  = vec_ldl (0, (vector double *)svd);
 
-  check (vec_all_eq (vul, evul), "vul");
-  check (vec_all_eq (vd,  evd ), "vd" );
+  for (i = 0; i < 2; ++i)
+    {
+      check (vul[i] == evul[i], "vul");
+      check (vd[i]  == evd[i],  "vd" );
+    }
 }
Index: gcc/testsuite/gcc.dg/vmx/merge-vsx.c
===================================================================
--- gcc/testsuite/gcc.dg/vmx/merge-vsx.c	(revision 208054)
+++ gcc/testsuite/gcc.dg/vmx/merge-vsx.c	(revision 208288)
@@ -9,6 +9,11 @@ static int vec_long_eq (vector long x, v
   return (x[0] == y[0] && x[1] == y[1]);
 }
 
+static int vec_double_eq (vector double x, vector double y)
+{
+  return (x[0] == y[0] && x[1] == y[1]);
+}
+
 static void test()
 {
   /* Input vectors.  */
@@ -34,6 +39,6 @@ static void test()
 
   check (vec_long_eq (vlh, vlrh), "vlh");
   check (vec_long_eq (vll, vlrl), "vll");
-  check (vec_all_eq (vdh, vdrh), "vdh" );
-  check (vec_all_eq (vdl, vdrl), "vdl" );
+  check (vec_double_eq (vdh, vdrh), "vdh" );
+  check (vec_double_eq (vdl, vdrl), "vdl" );
 }
Index: gcc/config/rs6000/vector.md
===================================================================
--- gcc/config/rs6000/vector.md	(revision 208054)
+++ gcc/config/rs6000/vector.md	(revision 208288)
@@ -608,8 +608,8 @@ (define_insn_and_split "*vector_unordere
 	(ge:VEC_F (match_dup 2)
 		  (match_dup 1)))
    (set (match_dup 0)
-	(not:VEC_F (ior:VEC_F (match_dup 3)
-			      (match_dup 4))))]
+        (and:VEC_F (not:VEC_F (match_dup 3))
+                   (not:VEC_F (match_dup 4))))]
   "
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 208054)
+++ gcc/config/rs6000/rs6000.c	(revision 208288)
@@ -16380,7 +16380,7 @@ rs6000_secondary_reload_inner (rtx reg,
     rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
 
   rclass = REGNO_REG_CLASS (regno);
-  addr = XEXP (mem, 0);
+  addr = find_replacement (&XEXP (mem, 0));
 
   switch (rclass)
     {
@@ -16391,19 +16391,18 @@ rs6000_secondary_reload_inner (rtx reg,
       if (GET_CODE (addr) == AND)
 	{
 	  and_op2 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
+	  addr = find_replacement (&XEXP (addr, 0));
 	}
 
       if (GET_CODE (addr) == PRE_MODIFY)
 	{
-	  scratch_or_premodify = XEXP (addr, 0);
+	  scratch_or_premodify = find_replacement (&XEXP (addr, 0));
 	  if (!REG_P (scratch_or_premodify))
 	    rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
 
-	  if (GET_CODE (XEXP (addr, 1)) != PLUS)
+	  addr = find_replacement (&XEXP (addr, 1));
+	  if (GET_CODE (addr) != PLUS)
 	    rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-
-	  addr = XEXP (addr, 1);
 	}
 
       if (GET_CODE (addr) == PLUS
@@ -16411,6 +16410,8 @@ rs6000_secondary_reload_inner (rtx reg,
 	      || !rs6000_legitimate_offset_address_p (PTImode, addr,
 						      false, true)))
 	{
+	  /* find_replacement already recurses into both operands of
+	     PLUS so we don't need to call it here.  */
 	  addr_op1 = XEXP (addr, 0);
 	  addr_op2 = XEXP (addr, 1);
 	  if (!legitimate_indirect_address_p (addr_op1, false))
@@ -16486,7 +16487,7 @@ rs6000_secondary_reload_inner (rtx reg,
 	      || !VECTOR_MEM_ALTIVEC_P (mode)))
 	{
 	  and_op2 = XEXP (addr, 1);
-	  addr = XEXP (addr, 0);
+	  addr = find_replacement (&XEXP (addr, 0));
 	}
 
       /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
@@ -16498,14 +16499,13 @@ rs6000_secondary_reload_inner (rtx reg,
 	      || and_op2 != NULL_RTX
 	      || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
 	{
-	  scratch_or_premodify = XEXP (addr, 0);
+	  scratch_or_premodify = find_replacement (&XEXP (addr, 0));
 	  if (!legitimate_indirect_address_p (scratch_or_premodify, false))
 	    rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
 
-	  if (GET_CODE (XEXP (addr, 1)) != PLUS)
+	  addr = find_replacement (&XEXP (addr, 1));
+	  if (GET_CODE (addr) != PLUS)
 	    rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
-
-	  addr = XEXP (addr, 1);
 	}
 
       if (legitimate_indirect_address_p (addr, false)	/* reg */
@@ -16765,8 +16765,14 @@ rs6000_preferred_reload_class (rtx x, en
       && easy_vector_constant (x, mode))
     return ALTIVEC_REGS;
 
-  if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
-    return NO_REGS;
+  if ((CONSTANT_P (x) || GET_CODE (x) == PLUS))
+    {
+      if (reg_class_subset_p (GENERAL_REGS, rclass))
+	return GENERAL_REGS;
+      if (reg_class_subset_p (BASE_REGS, rclass))
+	return BASE_REGS;
+      return NO_REGS;
+    }
 
   if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
     return GENERAL_REGS;

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