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backport-llvm-r204451
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File backport-llvm-r204451 of Package llvm
------------------------------------------------------------------------ r204451 | rsandifo | 2014-03-21 11:56:30 +0100 (Fri, 21 Mar 2014) | 4 lines [SystemZ] Add support for z196 float<->unsigned conversions These complement the older float<->signed instructions. ------------------------------------------------------------------------ Index: lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.cpp.orig +++ lib/Target/SystemZ/SystemZISelLowering.cpp @@ -177,8 +177,9 @@ SystemZTargetLowering::SystemZTargetLowe setOperationAction(ISD::SMUL_LOHI, VT, Custom); setOperationAction(ISD::UMUL_LOHI, VT, Custom); - // We have instructions for signed but not unsigned FP conversion. - setOperationAction(ISD::FP_TO_UINT, VT, Expand); + // Only z196 and above have native support for conversions to unsigned. + if (!Subtarget.hasFPExtension()) + setOperationAction(ISD::FP_TO_UINT, VT, Expand); } } @@ -198,10 +199,12 @@ SystemZTargetLowering::SystemZTargetLowe setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); - // We have instructions for signed but not unsigned FP conversion. + // z10 has instructions for signed but not unsigned FP conversion. // Handle unsigned 32-bit types as signed 64-bit types. - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + if (!Subtarget.hasFPExtension()) { + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + } // We have native support for a 64-bit CTLZ, via FLOGR. setOperationAction(ISD::CTLZ, MVT::i32, Promote); Index: lib/Target/SystemZ/SystemZInstrFP.td =================================================================== --- lib/Target/SystemZ/SystemZInstrFP.td.orig +++ lib/Target/SystemZ/SystemZInstrFP.td @@ -157,6 +157,25 @@ def CEGBR : UnaryRRE<"cegb", 0xB3A4, sin def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>; def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>; +// Convert am unsigned integer register value to a floating-point one. +let Predicates = [FeatureFPExtension] in { + def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>; + def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>; + def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>; + + def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>; + def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>; + def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>; + + def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; + def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; + def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; + + def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; + def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; + def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; +} + // Convert a floating-point register value to a signed integer value, // with the second operand (modifier M3) specifying the rounding mode. let Defs = [CC] in { @@ -178,6 +197,28 @@ def : Pat<(i64 (fp_to_sint FP32:$src)), def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; +// Convert a floating-point register value to an unsigned integer value. +let Predicates = [FeatureFPExtension] in { + let Defs = [CC] in { + def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>; + def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>; + def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>; + + def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>; + def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>; + def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>; + } + + def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; + def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; + def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; + + def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; + def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; + def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; +} + + //===----------------------------------------------------------------------===// // Unary arithmetic //===----------------------------------------------------------------------===// Index: test/MC/Disassembler/SystemZ/insns.txt =================================================================== --- test/MC/Disassembler/SystemZ/insns.txt.orig +++ test/MC/Disassembler/SystemZ/insns.txt @@ -907,6 +907,42 @@ # CHECK: cdgbr %f15, %r15 0xb3 0xa5 0x00 0xff +# CHECK: cdlfbr %f0, 0, %r0, 1 +0xb3 0x91 0x01 0x00 + +# CHECK: cdlfbr %f0, 0, %r0, 15 +0xb3 0x91 0x0f 0x00 + +# CHECK: cdlfbr %f0, 0, %r15, 1 +0xb3 0x91 0x01 0x0f + +# CHECK: cdlfbr %f0, 15, %r0, 1 +0xb3 0x91 0xf1 0x00 + +# CHECK: cdlfbr %f4, 5, %r6, 7 +0xb3 0x91 0x57 0x46 + +# CHECK: cdlfbr %f15, 0, %r0, 1 +0xb3 0x91 0x01 0xf0 + +# CHECK: cdlgbr %f0, 0, %r0, 1 +0xb3 0xa1 0x01 0x00 + +# CHECK: cdlgbr %f0, 0, %r0, 15 +0xb3 0xa1 0x0f 0x00 + +# CHECK: cdlgbr %f0, 0, %r15, 1 +0xb3 0xa1 0x01 0x0f + +# CHECK: cdlgbr %f0, 15, %r0, 1 +0xb3 0xa1 0xf1 0x00 + +# CHECK: cdlgbr %f4, 5, %r6, 7 +0xb3 0xa1 0x57 0x46 + +# CHECK: cdlgbr %f15, 0, %r0, 1 +0xb3 0xa1 0x01 0xf0 + # CHECK: cebr %f0, %f0 0xb3 0x09 0x00 0x00 @@ -970,6 +1006,42 @@ # CHECK: cegbr %f15, %r15 0xb3 0xa4 0x00 0xff +# CHECK: celfbr %f0, 0, %r0, 1 +0xb3 0x90 0x01 0x00 + +# CHECK: celfbr %f0, 0, %r0, 15 +0xb3 0x90 0x0f 0x00 + +# CHECK: celfbr %f0, 0, %r15, 1 +0xb3 0x90 0x01 0x0f + +# CHECK: celfbr %f0, 15, %r0, 1 +0xb3 0x90 0xf1 0x00 + +# CHECK: celfbr %f4, 5, %r6, 7 +0xb3 0x90 0x57 0x46 + +# CHECK: celfbr %f15, 0, %r0, 1 +0xb3 0x90 0x01 0xf0 + +# CHECK: celgbr %f0, 0, %r0, 1 +0xb3 0xa0 0x01 0x00 + +# CHECK: celgbr %f0, 0, %r0, 15 +0xb3 0xa0 0x0f 0x00 + +# CHECK: celgbr %f0, 0, %r15, 1 +0xb3 0xa0 0x01 0x0f + +# CHECK: celgbr %f0, 15, %r0, 1 +0xb3 0xa0 0xf1 0x00 + +# CHECK: celgbr %f4, 5, %r6, 7 +0xb3 0xa0 0x57 0x46 + +# CHECK: celgbr %f15, 0, %r0, 1 +0xb3 0xa0 0x01 0xf0 + # CHECK: cfdbr %r0, 0, %f0 0xb3 0x99 0x00 0x00 @@ -1480,6 +1552,114 @@ # CHECK: clc 0(256,%r15), 0 0xd5 0xff 0xf0 0x00 0x00 0x00 +# CHECK: clfdbr %r0, 0, %f0, 1 +0xb3 0x9d 0x01 0x00 + +# CHECK: clfdbr %r0, 0, %f0, 15 +0xb3 0x9d 0x0f 0x00 + +# CHECK: clfdbr %r0, 0, %f15, 1 +0xb3 0x9d 0x01 0x0f + +# CHECK: clfdbr %r0, 15, %f0, 1 +0xb3 0x9d 0xf1 0x00 + +# CHECK: clfdbr %r4, 5, %f6, 7 +0xb3 0x9d 0x57 0x46 + +# CHECK: clfdbr %r15, 0, %f0, 1 +0xb3 0x9d 0x01 0xf0 + +# CHECK: clfebr %r0, 0, %f0, 1 +0xb3 0x9c 0x01 0x00 + +# CHECK: clfebr %r0, 0, %f0, 15 +0xb3 0x9c 0x0f 0x00 + +# CHECK: clfebr %r0, 0, %f15, 1 +0xb3 0x9c 0x01 0x0f + +# CHECK: clfebr %r0, 15, %f0, 1 +0xb3 0x9c 0xf1 0x00 + +# CHECK: clfebr %r4, 5, %f6, 7 +0xb3 0x9c 0x57 0x46 + +# CHECK: clfebr %r15, 0, %f0, 1 +0xb3 0x9c 0x01 0xf0 + +# CHECK: clfxbr %r0, 0, %f0, 1 +0xb3 0x9e 0x01 0x00 + +# CHECK: clfxbr %r0, 0, %f0, 15 +0xb3 0x9e 0x0f 0x00 + +# CHECK: clfxbr %r0, 0, %f13, 1 +0xb3 0x9e 0x01 0x0d + +# CHECK: clfxbr %r0, 15, %f0, 1 +0xb3 0x9e 0xf1 0x00 + +# CHECK: clfxbr %r4, 5, %f8, 9 +0xb3 0x9e 0x59 0x48 + +# CHECK: clfxbr %r15, 0, %f0, 1 +0xb3 0x9e 0x01 0xf0 + +# CHECK: clgdbr %r0, 0, %f0, 1 +0xb3 0xad 0x01 0x00 + +# CHECK: clgdbr %r0, 0, %f0, 15 +0xb3 0xad 0x0f 0x00 + +# CHECK: clgdbr %r0, 0, %f15, 1 +0xb3 0xad 0x01 0x0f + +# CHECK: clgdbr %r0, 15, %f0, 1 +0xb3 0xad 0xf1 0x00 + +# CHECK: clgdbr %r4, 5, %f6, 7 +0xb3 0xad 0x57 0x46 + +# CHECK: clgdbr %r15, 0, %f0, 1 +0xb3 0xad 0x01 0xf0 + +# CHECK: clgebr %r0, 0, %f0, 1 +0xb3 0xac 0x01 0x00 + +# CHECK: clgebr %r0, 0, %f0, 15 +0xb3 0xac 0x0f 0x00 + +# CHECK: clgebr %r0, 0, %f15, 1 +0xb3 0xac 0x01 0x0f + +# CHECK: clgebr %r0, 15, %f0, 1 +0xb3 0xac 0xf1 0x00 + +# CHECK: clgebr %r4, 5, %f6, 7 +0xb3 0xac 0x57 0x46 + +# CHECK: clgebr %r15, 0, %f0, 1 +0xb3 0xac 0x01 0xf0 + +# CHECK: clgxbr %r0, 0, %f0, 1 +0xb3 0xae 0x01 0x00 + +# CHECK: clgxbr %r0, 0, %f0, 15 +0xb3 0xae 0x0f 0x00 + +# CHECK: clgxbr %r0, 0, %f13, 1 +0xb3 0xae 0x01 0x0d + +# CHECK: clgxbr %r0, 15, %f0, 1 +0xb3 0xae 0xf1 0x00 + +# CHECK: clgxbr %r4, 5, %f8, 9 +0xb3 0xae 0x59 0x48 + +# CHECK: clgxbr %r15, 0, %f0, 1 +0xb3 0xae 0x01 0xf0 + # CHECK: clfhsi 0, 0 0xe5 0x5d 0x00 0x00 0x00 0x00 @@ -1996,6 +2176,42 @@ # CHECK: cxgbr %f13, %r15 0xb3 0xa6 0x00 0xdf +# CHECK: cxlfbr %f0, 0, %r0, 1 +0xb3 0x92 0x01 0x00 + +# CHECK: cxlfbr %f0, 0, %r0, 15 +0xb3 0x92 0x0f 0x00 + +# CHECK: cxlfbr %f0, 0, %r15, 1 +0xb3 0x92 0x01 0x0f + +# CHECK: cxlfbr %f0, 15, %r0, 1 +0xb3 0x92 0xf1 0x00 + +# CHECK: cxlfbr %f4, 5, %r6, 7 +0xb3 0x92 0x57 0x46 + +# CHECK: cxlfbr %f13, 0, %r0, 1 +0xb3 0x92 0x01 0xd0 + +# CHECK: cxlgbr %f0, 0, %r0, 1 +0xb3 0xa2 0x01 0x00 + +# CHECK: cxlgbr %f0, 0, %r0, 15 +0xb3 0xa2 0x0f 0x00 + +# CHECK: cxlgbr %f0, 0, %r15, 1 +0xb3 0xa2 0x01 0x0f + +# CHECK: cxlgbr %f0, 15, %r0, 1 +0xb3 0xa2 0xf1 0x00 + +# CHECK: cxlgbr %f4, 5, %r6, 7 +0xb3 0xa2 0x57 0x46 + +# CHECK: cxlgbr %f13, 0, %r0, 1 +0xb3 0xa2 0x01 0xd0 + # CHECK: cy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x59 Index: test/MC/SystemZ/insn-bad.s =================================================================== --- test/MC/SystemZ/insn-bad.s.orig +++ test/MC/SystemZ/insn-bad.s @@ -386,6 +386,16 @@ cdb %f0, -1 cdb %f0, 4096 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: cdlfbr %f0, 0, %r0, 0 + + cdlfbr %f0, 0, %r0, 0 + +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: cdlgbr %f0, 0, %r0, 0 + + cdlgbr %f0, 0, %r0, 0 + #CHECK: error: invalid operand #CHECK: ceb %f0, -1 #CHECK: error: invalid operand @@ -394,6 +404,16 @@ ceb %f0, -1 ceb %f0, 4096 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: celfbr %f0, 0, %r0, 0 + + celfbr %f0, 0, %r0, 0 + +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: celgbr %f0, 0, %r0, 0 + + celgbr %f0, 0, %r0, 0 + #CHECK: error: invalid operand #CHECK: cfdbr %r0, -1, %f0 #CHECK: error: invalid operand @@ -784,6 +804,16 @@ clhf %r0, 0 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: clfdbr %r0, 0, %f0, 0 + + clfdbr %r0, 0, %f0, 0 + +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: clfebr %r0, 0, %f0, 0 + + clfebr %r0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: clfhsi -1, 0 #CHECK: error: invalid operand @@ -809,6 +839,11 @@ clfi %r0, -1 clfi %r0, (1 << 32) +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: clfxbr %r0, 0, %f0, 0 + + clfxbr %r0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: clg %r0, -524289 #CHECK: error: invalid operand @@ -817,6 +852,16 @@ clg %r0, -524289 clg %r0, 524288 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: clgdbr %r0, 0, %f0, 0 + + clgdbr %r0, 0, %f0, 0 + +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: clgebr %r0, 0, %f0, 0 + + clgebr %r0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: clgf %r0, -524289 #CHECK: error: invalid operand @@ -936,6 +981,11 @@ clgrl %r0, 1 clgrl %r0, 0x100000000 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: clgxbr %r0, 0, %f0, 0 + + clgxbr %r0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: clhhsi -1, 0 #CHECK: error: invalid operand @@ -1167,6 +1217,16 @@ cxgbr %f2, %r0 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: cxlfbr %f0, 0, %r0, 0 + + cxlfbr %f0, 0, %r0, 0 + +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: cxlgbr %f0, 0, %r0, 0 + + cxlgbr %f0, 0, %r0, 0 + #CHECK: error: invalid operand #CHECK: cy %r0, -524289 #CHECK: error: invalid operand Index: test/MC/SystemZ/insn-bad-z196.s =================================================================== --- test/MC/SystemZ/insn-bad-z196.s.orig +++ test/MC/SystemZ/insn-bad-z196.s @@ -33,6 +33,62 @@ aih %r0, (1 << 31) #CHECK: error: invalid operand +#CHECK: cdlfbr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cdlfbr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cdlfbr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cdlfbr %f0, 16, %r0, 0 + + cdlfbr %f0, 0, %r0, -1 + cdlfbr %f0, 0, %r0, 16 + cdlfbr %f0, -1, %r0, 0 + cdlfbr %f0, 16, %r0, 0 + +#CHECK: error: invalid operand +#CHECK: cdlgbr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cdlgbr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cdlgbr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cdlgbr %f0, 16, %r0, 0 + + cdlgbr %f0, 0, %r0, -1 + cdlgbr %f0, 0, %r0, 16 + cdlgbr %f0, -1, %r0, 0 + cdlgbr %f0, 16, %r0, 0 + +#CHECK: error: invalid operand +#CHECK: celfbr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: celfbr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: celfbr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: celfbr %f0, 16, %r0, 0 + + celfbr %f0, 0, %r0, -1 + celfbr %f0, 0, %r0, 16 + celfbr %f0, -1, %r0, 0 + celfbr %f0, 16, %r0, 0 + +#CHECK: error: invalid operand +#CHECK: celgbr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: celgbr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: celgbr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: celgbr %f0, 16, %r0, 0 + + celgbr %f0, 0, %r0, -1 + celgbr %f0, 0, %r0, 16 + celgbr %f0, -1, %r0, 0 + celgbr %f0, 16, %r0, 0 + +#CHECK: error: invalid operand #CHECK: chf %r0, -524289 #CHECK: error: invalid operand #CHECK: chf %r0, 524288 @@ -49,6 +105,96 @@ cih %r0, (1 << 31) #CHECK: error: invalid operand +#CHECK: clfdbr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clfdbr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clfdbr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clfdbr %r0, 16, %f0, 0 + + clfdbr %r0, 0, %f0, -1 + clfdbr %r0, 0, %f0, 16 + clfdbr %r0, -1, %f0, 0 + clfdbr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: clfebr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clfebr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clfebr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clfebr %r0, 16, %f0, 0 + + clfebr %r0, 0, %f0, -1 + clfebr %r0, 0, %f0, 16 + clfebr %r0, -1, %f0, 0 + clfebr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: clfxbr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clfxbr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clfxbr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clfxbr %r0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: clfxbr %r0, 0, %f14, 0 + + clfxbr %r0, 0, %f0, -1 + clfxbr %r0, 0, %f0, 16 + clfxbr %r0, -1, %f0, 0 + clfxbr %r0, 16, %f0, 0 + clfxbr %r0, 0, %f14, 0 + +#CHECK: error: invalid operand +#CHECK: clgdbr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clgdbr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clgdbr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clgdbr %r0, 16, %f0, 0 + + clgdbr %r0, 0, %f0, -1 + clgdbr %r0, 0, %f0, 16 + clgdbr %r0, -1, %f0, 0 + clgdbr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: clgebr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clgebr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clgebr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clgebr %r0, 16, %f0, 0 + + clgebr %r0, 0, %f0, -1 + clgebr %r0, 0, %f0, 16 + clgebr %r0, -1, %f0, 0 + clgebr %r0, 16, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: clgxbr %r0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: clgxbr %r0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: clgxbr %r0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: clgxbr %r0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: clgxbr %r0, 0, %f14, 0 + + clgxbr %r0, 0, %f0, -1 + clgxbr %r0, 0, %f0, 16 + clgxbr %r0, -1, %f0, 0 + clgxbr %r0, 16, %f0, 0 + clgxbr %r0, 0, %f14, 0 + +#CHECK: error: invalid operand #CHECK: clhf %r0, -524289 #CHECK: error: invalid operand #CHECK: clhf %r0, 524288 @@ -65,6 +211,40 @@ clih %r0, (1 << 32) #CHECK: error: invalid operand +#CHECK: cxlfbr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cxlfbr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cxlfbr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxlfbr %f0, 16, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxlfbr %f2, 0, %r0, 0 + + cxlfbr %f0, 0, %r0, -1 + cxlfbr %f0, 0, %r0, 16 + cxlfbr %f0, -1, %r0, 0 + cxlfbr %f0, 16, %r0, 0 + cxlfbr %f2, 0, %r0, 0 + +#CHECK: error: invalid operand +#CHECK: cxlgbr %f0, 0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cxlgbr %f0, 0, %r0, 16 +#CHECK: error: invalid operand +#CHECK: cxlgbr %f0, -1, %r0, 0 +#CHECK: error: invalid operand +#CHECK: cxlgbr %f0, 16, %r0, 0 +#CHECK: error: invalid register pair +#CHECK: cxlgbr %f2, 0, %r0, 0 + + cxlgbr %f0, 0, %r0, -1 + cxlgbr %f0, 0, %r0, 16 + cxlgbr %f0, -1, %r0, 0 + cxlgbr %f0, 16, %r0, 0 + cxlgbr %f2, 0, %r0, 0 + +#CHECK: error: invalid operand #CHECK: fidbra %f0, 0, %f0, -1 #CHECK: error: invalid operand #CHECK: fidbra %f0, 0, %f0, 16 Index: test/MC/SystemZ/insn-good-z196.s =================================================================== --- test/MC/SystemZ/insn-good-z196.s.orig +++ test/MC/SystemZ/insn-good-z196.s @@ -135,6 +135,62 @@ ark %r15,%r0,%r0 ark %r7,%r8,%r9 +#CHECK: cdlfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x91,0x00,0x00] +#CHECK: cdlfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x91,0x0f,0x00] +#CHECK: cdlfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x91,0x00,0x0f] +#CHECK: cdlfbr %f0, 15, %r0, 0 # encoding: [0xb3,0x91,0xf0,0x00] +#CHECK: cdlfbr %f4, 5, %r6, 7 # encoding: [0xb3,0x91,0x57,0x46] +#CHECK: cdlfbr %f15, 0, %r0, 0 # encoding: [0xb3,0x91,0x00,0xf0] + + cdlfbr %f0, 0, %r0, 0 + cdlfbr %f0, 0, %r0, 15 + cdlfbr %f0, 0, %r15, 0 + cdlfbr %f0, 15, %r0, 0 + cdlfbr %f4, 5, %r6, 7 + cdlfbr %f15, 0, %r0, 0 + +#CHECK: cdlgbr %f0, 0, %r0, 0 # encoding: [0xb3,0xa1,0x00,0x00] +#CHECK: cdlgbr %f0, 0, %r0, 15 # encoding: [0xb3,0xa1,0x0f,0x00] +#CHECK: cdlgbr %f0, 0, %r15, 0 # encoding: [0xb3,0xa1,0x00,0x0f] +#CHECK: cdlgbr %f0, 15, %r0, 0 # encoding: [0xb3,0xa1,0xf0,0x00] +#CHECK: cdlgbr %f4, 5, %r6, 7 # encoding: [0xb3,0xa1,0x57,0x46] +#CHECK: cdlgbr %f15, 0, %r0, 0 # encoding: [0xb3,0xa1,0x00,0xf0] + + cdlgbr %f0, 0, %r0, 0 + cdlgbr %f0, 0, %r0, 15 + cdlgbr %f0, 0, %r15, 0 + cdlgbr %f0, 15, %r0, 0 + cdlgbr %f4, 5, %r6, 7 + cdlgbr %f15, 0, %r0, 0 + +#CHECK: celfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x90,0x00,0x00] +#CHECK: celfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x90,0x0f,0x00] +#CHECK: celfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x90,0x00,0x0f] +#CHECK: celfbr %f0, 15, %r0, 0 # encoding: [0xb3,0x90,0xf0,0x00] +#CHECK: celfbr %f4, 5, %r6, 7 # encoding: [0xb3,0x90,0x57,0x46] +#CHECK: celfbr %f15, 0, %r0, 0 # encoding: [0xb3,0x90,0x00,0xf0] + + celfbr %f0, 0, %r0, 0 + celfbr %f0, 0, %r0, 15 + celfbr %f0, 0, %r15, 0 + celfbr %f0, 15, %r0, 0 + celfbr %f4, 5, %r6, 7 + celfbr %f15, 0, %r0, 0 + +#CHECK: celgbr %f0, 0, %r0, 0 # encoding: [0xb3,0xa0,0x00,0x00] +#CHECK: celgbr %f0, 0, %r0, 15 # encoding: [0xb3,0xa0,0x0f,0x00] +#CHECK: celgbr %f0, 0, %r15, 0 # encoding: [0xb3,0xa0,0x00,0x0f] +#CHECK: celgbr %f0, 15, %r0, 0 # encoding: [0xb3,0xa0,0xf0,0x00] +#CHECK: celgbr %f4, 5, %r6, 7 # encoding: [0xb3,0xa0,0x57,0x46] +#CHECK: celgbr %f15, 0, %r0, 0 # encoding: [0xb3,0xa0,0x00,0xf0] + + celgbr %f0, 0, %r0, 0 + celgbr %f0, 0, %r0, 15 + celgbr %f0, 0, %r15, 0 + celgbr %f0, 15, %r0, 0 + celgbr %f4, 5, %r6, 7 + celgbr %f15, 0, %r0, 0 + #CHECK: chf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xcd] #CHECK: chf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xcd] #CHECK: chf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xcd] @@ -171,6 +227,90 @@ cih %r0, (1 << 31) - 1 cih %r15, 0 +#CHECK: clfdbr %r0, 0, %f0, 0 # encoding: [0xb3,0x9d,0x00,0x00] +#CHECK: clfdbr %r0, 0, %f0, 15 # encoding: [0xb3,0x9d,0x0f,0x00] +#CHECK: clfdbr %r0, 0, %f15, 0 # encoding: [0xb3,0x9d,0x00,0x0f] +#CHECK: clfdbr %r0, 15, %f0, 0 # encoding: [0xb3,0x9d,0xf0,0x00] +#CHECK: clfdbr %r4, 5, %f6, 7 # encoding: [0xb3,0x9d,0x57,0x46] +#CHECK: clfdbr %r15, 0, %f0, 0 # encoding: [0xb3,0x9d,0x00,0xf0] + + clfdbr %r0, 0, %f0, 0 + clfdbr %r0, 0, %f0, 15 + clfdbr %r0, 0, %f15, 0 + clfdbr %r0, 15, %f0, 0 + clfdbr %r4, 5, %f6, 7 + clfdbr %r15, 0, %f0, 0 + +#CHECK: clfebr %r0, 0, %f0, 0 # encoding: [0xb3,0x9c,0x00,0x00] +#CHECK: clfebr %r0, 0, %f0, 15 # encoding: [0xb3,0x9c,0x0f,0x00] +#CHECK: clfebr %r0, 0, %f15, 0 # encoding: [0xb3,0x9c,0x00,0x0f] +#CHECK: clfebr %r0, 15, %f0, 0 # encoding: [0xb3,0x9c,0xf0,0x00] +#CHECK: clfebr %r4, 5, %f6, 7 # encoding: [0xb3,0x9c,0x57,0x46] +#CHECK: clfebr %r15, 0, %f0, 0 # encoding: [0xb3,0x9c,0x00,0xf0] + + clfebr %r0, 0, %f0, 0 + clfebr %r0, 0, %f0, 15 + clfebr %r0, 0, %f15, 0 + clfebr %r0, 15, %f0, 0 + clfebr %r4, 5, %f6, 7 + clfebr %r15, 0, %f0, 0 + +#CHECK: clfxbr %r0, 0, %f0, 0 # encoding: [0xb3,0x9e,0x00,0x00] +#CHECK: clfxbr %r0, 0, %f0, 15 # encoding: [0xb3,0x9e,0x0f,0x00] +#CHECK: clfxbr %r0, 0, %f13, 0 # encoding: [0xb3,0x9e,0x00,0x0d] +#CHECK: clfxbr %r0, 15, %f0, 0 # encoding: [0xb3,0x9e,0xf0,0x00] +#CHECK: clfxbr %r7, 5, %f8, 9 # encoding: [0xb3,0x9e,0x59,0x78] +#CHECK: clfxbr %r15, 0, %f0, 0 # encoding: [0xb3,0x9e,0x00,0xf0] + + clfxbr %r0, 0, %f0, 0 + clfxbr %r0, 0, %f0, 15 + clfxbr %r0, 0, %f13, 0 + clfxbr %r0, 15, %f0, 0 + clfxbr %r7, 5, %f8, 9 + clfxbr %r15, 0, %f0, 0 + +#CHECK: clgdbr %r0, 0, %f0, 0 # encoding: [0xb3,0xad,0x00,0x00] +#CHECK: clgdbr %r0, 0, %f0, 15 # encoding: [0xb3,0xad,0x0f,0x00] +#CHECK: clgdbr %r0, 0, %f15, 0 # encoding: [0xb3,0xad,0x00,0x0f] +#CHECK: clgdbr %r0, 15, %f0, 0 # encoding: [0xb3,0xad,0xf0,0x00] +#CHECK: clgdbr %r4, 5, %f6, 7 # encoding: [0xb3,0xad,0x57,0x46] +#CHECK: clgdbr %r15, 0, %f0, 0 # encoding: [0xb3,0xad,0x00,0xf0] + + clgdbr %r0, 0, %f0, 0 + clgdbr %r0, 0, %f0, 15 + clgdbr %r0, 0, %f15, 0 + clgdbr %r0, 15, %f0, 0 + clgdbr %r4, 5, %f6, 7 + clgdbr %r15, 0, %f0, 0 + +#CHECK: clgebr %r0, 0, %f0, 0 # encoding: [0xb3,0xac,0x00,0x00] +#CHECK: clgebr %r0, 0, %f0, 15 # encoding: [0xb3,0xac,0x0f,0x00] +#CHECK: clgebr %r0, 0, %f15, 0 # encoding: [0xb3,0xac,0x00,0x0f] +#CHECK: clgebr %r0, 15, %f0, 0 # encoding: [0xb3,0xac,0xf0,0x00] +#CHECK: clgebr %r4, 5, %f6, 7 # encoding: [0xb3,0xac,0x57,0x46] +#CHECK: clgebr %r15, 0, %f0, 0 # encoding: [0xb3,0xac,0x00,0xf0] + + clgebr %r0, 0, %f0, 0 + clgebr %r0, 0, %f0, 15 + clgebr %r0, 0, %f15, 0 + clgebr %r0, 15, %f0, 0 + clgebr %r4, 5, %f6, 7 + clgebr %r15, 0, %f0, 0 + +#CHECK: clgxbr %r0, 0, %f0, 0 # encoding: [0xb3,0xae,0x00,0x00] +#CHECK: clgxbr %r0, 0, %f0, 15 # encoding: [0xb3,0xae,0x0f,0x00] +#CHECK: clgxbr %r0, 0, %f13, 0 # encoding: [0xb3,0xae,0x00,0x0d] +#CHECK: clgxbr %r0, 15, %f0, 0 # encoding: [0xb3,0xae,0xf0,0x00] +#CHECK: clgxbr %r7, 5, %f8, 9 # encoding: [0xb3,0xae,0x59,0x78] +#CHECK: clgxbr %r15, 0, %f0, 0 # encoding: [0xb3,0xae,0x00,0xf0] + + clgxbr %r0, 0, %f0, 0 + clgxbr %r0, 0, %f0, 15 + clgxbr %r0, 0, %f13, 0 + clgxbr %r0, 15, %f0, 0 + clgxbr %r7, 5, %f8, 9 + clgxbr %r15, 0, %f0, 0 + #CHECK: clhf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xcf] #CHECK: clhf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xcf] #CHECK: clhf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xcf] @@ -203,6 +343,34 @@ clih %r0, (1 << 32) - 1 clih %r15, 0 +#CHECK: cxlfbr %f0, 0, %r0, 0 # encoding: [0xb3,0x92,0x00,0x00] +#CHECK: cxlfbr %f0, 0, %r0, 15 # encoding: [0xb3,0x92,0x0f,0x00] +#CHECK: cxlfbr %f0, 0, %r15, 0 # encoding: [0xb3,0x92,0x00,0x0f] +#CHECK: cxlfbr %f0, 15, %r0, 0 # encoding: [0xb3,0x92,0xf0,0x00] +#CHECK: cxlfbr %f4, 5, %r9, 10 # encoding: [0xb3,0x92,0x5a,0x49] +#CHECK: cxlfbr %f13, 0, %r0, 0 # encoding: [0xb3,0x92,0x00,0xd0] + + cxlfbr %f0, 0, %r0, 0 + cxlfbr %f0, 0, %r0, 15 + cxlfbr %f0, 0, %r15, 0 + cxlfbr %f0, 15, %r0, 0 + cxlfbr %f4, 5, %r9, 10 + cxlfbr %f13, 0, %r0, 0 + +#CHECK: cxlgbr %f0, 0, %r0, 0 # encoding: [0xb3,0xa2,0x00,0x00] +#CHECK: cxlgbr %f0, 0, %r0, 15 # encoding: [0xb3,0xa2,0x0f,0x00] +#CHECK: cxlgbr %f0, 0, %r15, 0 # encoding: [0xb3,0xa2,0x00,0x0f] +#CHECK: cxlgbr %f0, 15, %r0, 0 # encoding: [0xb3,0xa2,0xf0,0x00] +#CHECK: cxlgbr %f4, 5, %r9, 10 # encoding: [0xb3,0xa2,0x5a,0x49] +#CHECK: cxlgbr %f13, 0, %r0, 0 # encoding: [0xb3,0xa2,0x00,0xd0] + + cxlgbr %f0, 0, %r0, 0 + cxlgbr %f0, 0, %r0, 15 + cxlgbr %f0, 0, %r15, 0 + cxlgbr %f0, 15, %r0, 0 + cxlgbr %f4, 5, %r9, 10 + cxlgbr %f13, 0, %r0, 0 + #CHECK: fidbra %f0, 0, %f0, 0 # encoding: [0xb3,0x5f,0x00,0x00] #CHECK: fidbra %f0, 0, %f0, 15 # encoding: [0xb3,0x5f,0x0f,0x00] #CHECK: fidbra %f0, 0, %f15, 0 # encoding: [0xb3,0x5f,0x00,0x0f] Index: test/CodeGen/SystemZ/fp-conv-14.ll =================================================================== --- /dev/null +++ test/CodeGen/SystemZ/fp-conv-14.ll @@ -0,0 +1,63 @@ +; Test conversion of floating-point values to unsigned integers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Test f32->i32. +define i32 @f1(float %f) { +; CHECK-LABEL: f1: +; CHECK: clfebr %r2, 5, %f0, 0 +; CHECK: br %r14 + %conv = fptoui float %f to i32 + ret i32 %conv +} + +; Test f64->i32. +define i32 @f2(double %f) { +; CHECK-LABEL: f2: +; CHECK: clfdbr %r2, 5, %f0, 0 +; CHECK: br %r14 + %conv = fptoui double %f to i32 + ret i32 %conv +} + +; Test f128->i32. +define i32 @f3(fp128 *%src) { +; CHECK-LABEL: f3: +; CHECK-DAG: ld %f0, 0(%r2) +; CHECK-DAG: ld %f2, 8(%r2) +; CHECK: clfxbr %r2, 5, %f0, 0 +; CHECK: br %r14 + %f = load fp128 *%src + %conv = fptoui fp128 %f to i32 + ret i32 %conv +} + +; Test f32->i64. +define i64 @f4(float %f) { +; CHECK-LABEL: f4: +; CHECK: clgebr %r2, 5, %f0, 0 +; CHECK: br %r14 + %conv = fptoui float %f to i64 + ret i64 %conv +} + +; Test f64->i64. +define i64 @f5(double %f) { +; CHECK-LABEL: f5: +; CHECK: clgdbr %r2, 5, %f0, 0 +; CHECK: br %r14 + %conv = fptoui double %f to i64 + ret i64 %conv +} + +; Test f128->i64. +define i64 @f6(fp128 *%src) { +; CHECK-LABEL: f6: +; CHECK-DAG: ld %f0, 0(%r2) +; CHECK-DAG: ld %f2, 8(%r2) +; CHECK: clgxbr %r2, 5, %f0, 0 +; CHECK: br %r14 + %f = load fp128 *%src + %conv = fptoui fp128 %f to i64 + ret i64 %conv +} Index: test/CodeGen/SystemZ/fp-conv-06.ll =================================================================== --- test/CodeGen/SystemZ/fp-conv-06.ll.orig +++ test/CodeGen/SystemZ/fp-conv-06.ll @@ -1,6 +1,6 @@ -; Test conversions of unsigned i32s to floating-point values. +; Test conversions of unsigned i32s to floating-point values (z10 only). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Check i32->f32. There is no native instruction, so we must promote ; to i64 first. Index: test/CodeGen/SystemZ/fp-conv-10.ll =================================================================== --- test/CodeGen/SystemZ/fp-conv-10.ll.orig +++ test/CodeGen/SystemZ/fp-conv-10.ll @@ -1,6 +1,6 @@ -; Test conversion of floating-point values to unsigned i32s. +; Test conversion of floating-point values to unsigned i32s (z10 only). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; z10 doesn't have native support for unsigned fp-to-i32 conversions; ; they were added in z196 as the Convert to Logical family of instructions. Index: test/CodeGen/SystemZ/fp-conv-08.ll =================================================================== --- test/CodeGen/SystemZ/fp-conv-08.ll.orig +++ test/CodeGen/SystemZ/fp-conv-08.ll @@ -1,6 +1,6 @@ -; Test conversions of unsigned i64s to floating-point values. +; Test conversions of unsigned i64s to floating-point values (z10 only). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; Test i64->f32. There's no native support for unsigned i64-to-fp conversions, ; but we should be able to implement them using signed i64-to-fp conversions. Index: test/CodeGen/SystemZ/fp-conv-12.ll =================================================================== --- test/CodeGen/SystemZ/fp-conv-12.ll.orig +++ test/CodeGen/SystemZ/fp-conv-12.ll @@ -1,6 +1,6 @@ -; Test conversion of floating-point values to unsigned i64s. +; Test conversion of floating-point values to unsigned i64s (z10 only). ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s ; z10 doesn't have native support for unsigned fp-to-i64 conversions; ; they were added in z196 as the Convert to Logical family of instructions. Index: test/CodeGen/SystemZ/fp-conv-13.ll =================================================================== --- /dev/null +++ test/CodeGen/SystemZ/fp-conv-13.ll @@ -0,0 +1,64 @@ +; Test conversions of unsigned integers to floating-point values +; (z196 and above). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s + +; Check i32->f32. +define float @f1(i32 %i) { +; CHECK-LABEL: f1: +; CHECK: celfbr %f0, 0, %r2, 0 +; CHECK: br %r14 + %conv = uitofp i32 %i to float + ret float %conv +} + +; Check i32->f64. +define double @f2(i32 %i) { +; CHECK-LABEL: f2: +; CHECK: cdlfbr %f0, 0, %r2, 0 +; CHECK: br %r14 + %conv = uitofp i32 %i to double + ret double %conv +} + +; Check i32->f128. +define void @f3(i32 %i, fp128 *%dst) { +; CHECK-LABEL: f3: +; CHECK: cxlfbr %f0, 0, %r2, 0 +; CHECK-DAG: std %f0, 0(%r3) +; CHECK-DAG: std %f2, 8(%r3) +; CHECK: br %r14 + %conv = uitofp i32 %i to fp128 + store fp128 %conv, fp128 *%dst + ret void +} + +; Check i64->f32. +define float @f4(i64 %i) { +; CHECK-LABEL: f4: +; CHECK: celgbr %f0, 0, %r2, 0 +; CHECK: br %r14 + %conv = uitofp i64 %i to float + ret float %conv +} + +; Check i64->f64. +define double @f5(i64 %i) { +; CHECK-LABEL: f5: +; CHECK: cdlgbr %f0, 0, %r2, 0 +; CHECK: br %r14 + %conv = uitofp i64 %i to double + ret double %conv +} + +; Check i64->f128. +define void @f6(i64 %i, fp128 *%dst) { +; CHECK-LABEL: f6: +; CHECK: cxlgbr %f0, 0, %r2, 0 +; CHECK-DAG: std %f0, 0(%r3) +; CHECK-DAG: std %f2, 8(%r3) +; CHECK: br %r14 + %conv = uitofp i64 %i to fp128 + store fp128 %conv, fp128 *%dst + ret void +}
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