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home:Alexander_Naumov:SLE-12:Update
qemu-linux-user.7445
0435-cirrus-fix-oob-access-in-mode4and5-.patch
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File 0435-cirrus-fix-oob-access-in-mode4and5-.patch of Package qemu-linux-user.7445
From a9871c187d243766541fc49cf7750273a31302f6 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann <kraxel@redhat.com> Date: Wed, 18 Oct 2017 14:54:15 -0600 Subject: [PATCH] cirrus: fix oob access in mode4and5 write functions Move dst calculation into the loop, so we apply the mask on each interation and will not overflow vga memory. Cc: Prasad J Pandit <pjp@fedoraproject.org> Reported-by: Niu Guoxiang <niuguoxiang@huawei.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20171011084314.21752-1-kraxel@redhat.com [BR: BSC#1063122 CVE-2017-15289] Signed-off-by: Bruce Rogers <brogers@suse.com --- hw/display/cirrus_vga.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index 1370c29e41..18cad65bfb 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2018,15 +2018,14 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, unsigned val = mem_value; uint8_t *dst; - dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); for (x = 0; x < 8; x++) { + dst = s->vga.vram_ptr + ((offset + x) & s->cirrus_addr_mask); if (val & 0x80) { *dst = s->cirrus_shadow_gr1; } else if (mode == 5) { *dst = s->cirrus_shadow_gr0; } val <<= 1; - dst++; } memory_region_set_dirty(&s->vga.vram, offset, 8); } @@ -2040,8 +2039,8 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, unsigned val = mem_value; uint8_t *dst; - dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); for (x = 0; x < 8; x++) { + dst = s->vga.vram_ptr + ((offset + 2 * x) & s->cirrus_addr_mask & ~1); if (val & 0x80) { *dst = s->cirrus_shadow_gr1; *(dst + 1) = s->vga.gr[0x11]; @@ -2050,7 +2049,6 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, *(dst + 1) = s->vga.gr[0x10]; } val <<= 1; - dst += 2; } memory_region_set_dirty(&s->vga.vram, offset, 16); }
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