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File riscv.patch of Package gdb (Revision b3be5bf52a648a61bdcf03bb83b290a3)

Currently displaying revision b3be5bf52a648a61bdcf03bb83b290a3 , Show latest

Index: gdb-8.1.90/gdb/Makefile.in
===================================================================
--- gdb-8.1.90.orig/gdb/Makefile.in
+++ gdb-8.1.90/gdb/Makefile.in
@@ -763,6 +763,7 @@ ALL_TARGET_OBS = \
 	ppc64-tdep.o \
 	ravenscar-thread.o \
 	riscv-tdep.o \
+	riscv-linux-tdep.o \
 	rl78-tdep.o \
 	rs6000-aix-tdep.o \
 	rs6000-lynx178-tdep.o \
@@ -2361,6 +2362,8 @@ ALLDEPFILES = \
 	ravenscar-thread.c \
 	remote-sim.c \
 	riscv-tdep.c \
+	riscv-linux-nat.c \
+	riscv-linux-tdep.c \
 	rl78-tdep.c \
 	rs6000-lynx178-tdep.c \
 	rs6000-nat.c \
Index: gdb-8.1.90/gdb/configure.host
===================================================================
--- gdb-8.1.90.orig/gdb/configure.host
+++ gdb-8.1.90/gdb/configure.host
@@ -66,6 +66,7 @@ i[34567]86*)		gdb_host_cpu=i386 ;;
 m68*)			gdb_host_cpu=m68k ;;
 mips*)			gdb_host_cpu=mips ;;
 powerpc* | rs6000)	gdb_host_cpu=powerpc ;;
+riscv*)                 gdb_host_cpu=riscv ;;
 sparcv9 | sparc64)	gdb_host_cpu=sparc ;;
 s390*)			gdb_host_cpu=s390 ;;
 sh*)			gdb_host_cpu=sh ;;
@@ -149,6 +150,8 @@ powerpc64*-*-linux*)	gdb_host=ppc64-linu
 			;;
 powerpc*-*-linux*)	gdb_host=linux ;;
 
+riscv*-linux*)          gdb_host=linux ;;
+
 s390*-*-linux*)		gdb_host=linux ;;
 
 sh*-*-netbsdelf* | sh*-*-knetbsd*-gnu)
Index: gdb-8.1.90/gdb/configure.nat
===================================================================
--- gdb-8.1.90.orig/gdb/configure.nat
+++ gdb-8.1.90/gdb/configure.nat
@@ -268,6 +268,10 @@ case ${gdb_host} in
 		# Host: PowerPC, running Linux
 		NATDEPFILES="${NATDEPFILES} ppc-linux-nat.o ppc-linux.o"
 		;;
+	    riscv)
+		# Host: RISC-V, running Linux
+		NATDEPFILES="${NATDEPFILES} riscv-linux-nat.o"
+		;;
 	    s390)
 		# Host: S390, running Linux
 		NATDEPFILES="${NATDEPFILES} s390-linux-nat.o"
Index: gdb-8.1.90/gdb/configure.tgt
===================================================================
--- gdb-8.1.90.orig/gdb/configure.tgt
+++ gdb-8.1.90/gdb/configure.tgt
@@ -517,9 +517,17 @@ s390*-*-linux*)
 	build_gdbserver=yes
 	;;
 
+riscv*-*-linux*)
+	# Target Linux/RISC-V
+	gdb_target_obs="riscv-linux-tdep.o riscv-tdep.o glibc-tdep.o \
+			linux-tdep.o solib-svr4.o symfile-mem.o linux-record.o"
+	build_gdbserver=yes
+	;;
+
 riscv*-*-*)
 	# Target: RISC-V architecture
 	gdb_target_obs="riscv-tdep.o"
+	gdb_sim=../sim/riscv/libsim.a
 	;;
 
 rl78-*-elf)
Index: gdb-8.1.90/gdb/features/Makefile
===================================================================
--- gdb-8.1.90.orig/gdb/features/Makefile
+++ gdb-8.1.90/gdb/features/Makefile
@@ -66,6 +66,7 @@ WHICH = aarch64 \
 	microblaze-with-stack-protect \
 	mips64-linux mips64-dsp-linux \
 	nios2-linux \
+	riscv \
 	rs6000/powerpc-32 \
 	rs6000/powerpc-32l rs6000/powerpc-altivec32l rs6000/powerpc-e500l \
 	rs6000/powerpc-64l rs6000/powerpc-altivec64l rs6000/powerpc-vsx32l \
@@ -138,6 +139,7 @@ XMLTOC = \
 	nds32.xml \
 	nios2.xml \
 	or1k.xml \
+	riscv.xml \
 	rs6000/powerpc-32.xml \
 	rs6000/powerpc-32l.xml \
 	rs6000/powerpc-403.xml \
Index: gdb-8.1.90/gdb/features/riscv.c
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/features/riscv.c
@@ -0,0 +1,86 @@
+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
+  Original: riscv.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_riscv;
+static void
+initialize_tdesc_riscv (void)
+{
+  struct target_desc *result = allocate_target_description ();
+  struct tdesc_feature *feature;
+
+  set_tdesc_architecture (result, bfd_scan_arch ("riscv:rv64"));
+
+  feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.rv64i");
+  tdesc_create_reg (feature, "x0", 0, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x1", 1, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x2", 2, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x3", 3, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x4", 4, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x5", 5, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x6", 6, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x7", 7, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x8", 8, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x9", 9, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x10", 10, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x11", 11, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x12", 12, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x13", 13, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x14", 14, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x15", 15, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x16", 16, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x17", 17, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x18", 18, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x19", 19, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x20", 20, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x21", 21, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x22", 22, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x23", 23, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x24", 24, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x25", 25, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x26", 26, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x27", 27, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x28", 28, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x29", 29, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x30", 30, 1, "general", 64, "int");
+  tdesc_create_reg (feature, "x31", 31, 1, "general", 64, "int");
+
+  feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.rv64d");
+  tdesc_create_reg (feature, "f0", 32, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f1", 33, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f2", 34, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f3", 35, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f4", 36, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f5", 37, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f6", 38, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f7", 39, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f8", 40, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f9", 41, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f10", 42, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f11", 43, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f12", 44, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f13", 45, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f14", 46, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f15", 47, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f16", 48, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f17", 49, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f18", 50, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f19", 51, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f20", 52, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f21", 53, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f22", 54, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f23", 55, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f24", 56, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f25", 57, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f26", 58, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f27", 59, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f28", 60, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f29", 61, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f30", 62, 1, "float", 64, "float");
+  tdesc_create_reg (feature, "f31", 63, 1, "float", 64, "float");
+
+  tdesc_riscv = result;
+}
Index: gdb-8.1.90/gdb/features/riscv.xml
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/features/riscv.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0"?>
+
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+  <architecture>riscv:rv64</architecture>
+
+  <feature name="org.gnu.gdb.riscv.rv64i">
+    <reg name="x0"  bitsize="64" group="general"/>
+    <reg name="x1"  bitsize="64" group="general"/>
+    <reg name="x2"  bitsize="64" group="general"/>
+    <reg name="x3"  bitsize="64" group="general"/>
+    <reg name="x4"  bitsize="64" group="general"/>
+    <reg name="x5"  bitsize="64" group="general"/>
+    <reg name="x6"  bitsize="64" group="general"/>
+    <reg name="x7"  bitsize="64" group="general"/>
+    <reg name="x8"  bitsize="64" group="general"/>
+    <reg name="x9"  bitsize="64" group="general"/>
+    <reg name="x10" bitsize="64" group="general"/>
+    <reg name="x11" bitsize="64" group="general"/>
+    <reg name="x12" bitsize="64" group="general"/>
+    <reg name="x13" bitsize="64" group="general"/>
+    <reg name="x14" bitsize="64" group="general"/>
+    <reg name="x15" bitsize="64" group="general"/>
+    <reg name="x16" bitsize="64" group="general"/>
+    <reg name="x17" bitsize="64" group="general"/>
+    <reg name="x18" bitsize="64" group="general"/>
+    <reg name="x19" bitsize="64" group="general"/>
+    <reg name="x20" bitsize="64" group="general"/>
+    <reg name="x21" bitsize="64" group="general"/>
+    <reg name="x22" bitsize="64" group="general"/>
+    <reg name="x23" bitsize="64" group="general"/>
+    <reg name="x24" bitsize="64" group="general"/>
+    <reg name="x25" bitsize="64" group="general"/>
+    <reg name="x26" bitsize="64" group="general"/>
+    <reg name="x27" bitsize="64" group="general"/>
+    <reg name="x28" bitsize="64" group="general"/>
+    <reg name="x29" bitsize="64" group="general"/>
+    <reg name="x30" bitsize="64" group="general"/>
+    <reg name="x31" bitsize="64" group="general"/>
+  </feature>
+
+  <feature name="org.gnu.gdb.riscv.rv64d">
+    <reg name="f0"  bitsize="64" group="float" type="float"/>
+    <reg name="f1"  bitsize="64" group="float" type="float"/>
+    <reg name="f2"  bitsize="64" group="float" type="float"/>
+    <reg name="f3"  bitsize="64" group="float" type="float"/>
+    <reg name="f4"  bitsize="64" group="float" type="float"/>
+    <reg name="f5"  bitsize="64" group="float" type="float"/>
+    <reg name="f6"  bitsize="64" group="float" type="float"/>
+    <reg name="f7"  bitsize="64" group="float" type="float"/>
+    <reg name="f8"  bitsize="64" group="float" type="float"/>
+    <reg name="f9"  bitsize="64" group="float" type="float"/>
+    <reg name="f10" bitsize="64" group="float" type="float"/>
+    <reg name="f11" bitsize="64" group="float" type="float"/>
+    <reg name="f12" bitsize="64" group="float" type="float"/>
+    <reg name="f13" bitsize="64" group="float" type="float"/>
+    <reg name="f14" bitsize="64" group="float" type="float"/>
+    <reg name="f15" bitsize="64" group="float" type="float"/>
+    <reg name="f16" bitsize="64" group="float" type="float"/>
+    <reg name="f17" bitsize="64" group="float" type="float"/>
+    <reg name="f18" bitsize="64" group="float" type="float"/>
+    <reg name="f19" bitsize="64" group="float" type="float"/>
+    <reg name="f20" bitsize="64" group="float" type="float"/>
+    <reg name="f21" bitsize="64" group="float" type="float"/>
+    <reg name="f22" bitsize="64" group="float" type="float"/>
+    <reg name="f23" bitsize="64" group="float" type="float"/>
+    <reg name="f24" bitsize="64" group="float" type="float"/>
+    <reg name="f25" bitsize="64" group="float" type="float"/>
+    <reg name="f26" bitsize="64" group="float" type="float"/>
+    <reg name="f27" bitsize="64" group="float" type="float"/>
+    <reg name="f28" bitsize="64" group="float" type="float"/>
+    <reg name="f29" bitsize="64" group="float" type="float"/>
+    <reg name="f30" bitsize="64" group="float" type="float"/>
+    <reg name="f31" bitsize="64" group="float" type="float"/>
+  </feature>
+</target>
Index: gdb-8.1.90/gdb/gdbserver/configure.srv
===================================================================
--- gdb-8.1.90.orig/gdb/gdbserver/configure.srv
+++ gdb-8.1.90/gdb/gdbserver/configure.srv
@@ -263,6 +263,11 @@ case "${target}" in
 			srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu.xml"
 			srv_lynxos=yes
 			;;
+  riscv*-*-linux*)	srv_regobj=riscv.o
+			srv_tgtobj="$srv_linux_obj linux-riscv-low.o"
+			srv_linux_regsets=yes
+			srv_linux_thread_db=yes
+			;;
   s390*-*-linux*)	srv_regobj="s390-linux32.o"
 			srv_regobj="${srv_regobj} s390-linux32v1.o"
 			srv_regobj="${srv_regobj} s390-linux32v2.o"
Index: gdb-8.1.90/gdb/gdbserver/linux-riscv-low.c
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/gdbserver/linux-riscv-low.c
@@ -0,0 +1,209 @@
+/* GNU/Linux/RISC-V specific low level interface, GDBserver.
+
+   Copyright (C) 2012-2017 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "server.h"
+#include "linux-low.h"
+
+#include "nat/gdb_ptrace.h"
+
+/* Defined in auto-generated file reg-riscv.c.  */
+void init_registers_riscv (void);
+extern const struct target_desc *tdesc_riscv;
+
+#define riscv_num_regs 32
+
+static int riscv_regmap[] =
+{
+   0,  1,  2,  3,  4,  5,  6,  7,
+   8,  9, 10, 11, 12, 13, 14, 15,
+  16, 17, 18, 19, 20, 21, 22, 23,
+  24, 25, 26, 27, 28, 29, 30, 31,
+  32, 33, 34, 35, 36, 37, 38, 39,
+  40, 41, 42, 43, 44, 45, 46, 47,
+  48, 49, 50, 51, 52, 53, 54, 55,
+  56, 57, 58, 59, 60, 61, 62, 63
+};
+
+static int
+riscv_cannot_fetch_register (int regno)
+{
+  if (regno >= 0 && regno < 63)
+    return 0;
+  else
+    return 1;
+}
+
+static int
+riscv_cannot_store_register (int regno)
+{
+  if (regno >= 0 && regno < 63)
+    return 0;
+  else
+    return 1;
+}
+
+/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
+
+static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
+static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
+
+static const gdb_byte *
+riscv_sw_breakpoint_from_kind (int kind, int *size)
+{
+  *size = kind;
+  switch (kind)
+    {
+    case 2:
+      return c_ebreak;
+    case 4:
+      return ebreak;
+    default:
+      gdb_assert(0);
+    }
+}
+
+static int
+riscv_breakpoint_at (CORE_ADDR where)
+{
+  uint8_t insn[4];
+
+  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
+  if (insn[0] == ebreak[0] && insn[1] == ebreak[1]
+      && insn[2] == ebreak[2] && insn[3] == ebreak[3])
+    return 1;
+  if (insn[0] == c_ebreak[0] && insn[1] == c_ebreak[1])
+    return 1;
+
+  /* If necessary, recognize more trap instructions here.  GDB only uses the
+     one.  */
+  return 0;
+}
+
+static void
+riscv_fill_gregset (struct regcache *regcache, void *buf)
+{
+  int i;
+
+  for (i = 0; i < riscv_num_regs; i++)
+    if (riscv_regmap[i] != -1)
+      collect_register (regcache, i, ((unsigned long *) buf) + riscv_regmap[i]);
+}
+
+static void
+riscv_store_gregset (struct regcache *regcache, const void *buf)
+{
+  int i;
+
+  for (i = 0; i < riscv_num_regs; i++)
+    if (riscv_regmap[i] != -1)
+      supply_register (regcache, i, ((unsigned long *) buf) + riscv_regmap[i]);
+}
+
+static struct regset_info riscv_regsets[] =
+{
+  { PTRACE_GETREGS, PTRACE_SETREGS, 0, riscv_num_regs * 8,
+    GENERAL_REGS, riscv_fill_gregset, riscv_store_gregset },
+  NULL_REGSET
+};
+
+static struct regsets_info riscv_regsets_info =
+  {
+    riscv_regsets, /* regsets */
+    0, /* num_regsets */
+    NULL, /* disabled_regsets */
+  };
+
+static struct usrregs_info riscv_usrregs_info =
+  {
+    riscv_num_regs,
+    riscv_regmap,
+  };
+
+static struct regs_info regs_info =
+  {
+    NULL, /* regset_bitmap */
+    &riscv_usrregs_info,
+    &riscv_regsets_info,
+  };
+
+static const struct regs_info *
+riscv_regs_info (void)
+{
+  return &regs_info;
+}
+
+static void
+riscv_arch_setup (void)
+{
+  current_process ()->tdesc = tdesc_riscv;
+}
+
+/* Support for hardware single step.  */
+
+static int
+riscv_supports_hardware_single_step (void)
+{
+  return 0;
+}
+
+
+struct linux_target_ops the_low_target =
+{
+  riscv_arch_setup,
+  riscv_regs_info,
+  riscv_cannot_fetch_register,
+  riscv_cannot_store_register,
+  NULL,
+  linux_get_pc_64bit,
+  linux_set_pc_64bit,
+  NULL, /* breakpoint_kind_from_pc */
+  riscv_sw_breakpoint_from_kind,
+  NULL,
+  0,
+  riscv_breakpoint_at,
+  NULL, /* supports_z_point_type */
+  NULL, /* insert_point */
+  NULL, /* remove_point */
+  NULL, /* stopped_by_watchpoint */
+  NULL, /* stopped_data_address */
+  NULL, /* collect_ptrace_register */
+  NULL, /* supply_ptrace_register */
+  NULL, /* siginfo_fixup */
+  NULL, /* new_process */
+  NULL, /* new_thread */
+  NULL, /* new_fork */
+  NULL, /* prepare_to_resume */
+  NULL, /* process_qsupported */
+  NULL, /* supports_tracepoints */
+  NULL, /* get_thread_area */
+  NULL, /* install_fast_tracepoint_jump_pad */
+  NULL, /* emit_ops */
+  NULL, /* get_min_fast_tracepoint_insn_len */
+  NULL, /* supports_range_stepping */
+  NULL, /* breakpoint_kind_from_current_state */
+  riscv_supports_hardware_single_step,
+};
+
+void
+initialize_low_arch (void)
+{
+  init_registers_riscv();
+
+  initialize_regsets_info (&riscv_regsets_info);
+}
Index: gdb-8.1.90/gdb/regformats/riscv.dat
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/regformats/riscv.dat
@@ -0,0 +1,69 @@
+# THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: riscv.xml
+name:riscv
+xmltarget:riscv.xml
+expedite:
+64:x0
+64:x1
+64:x2
+64:x3
+64:x4
+64:x5
+64:x6
+64:x7
+64:x8
+64:x9
+64:x10
+64:x11
+64:x12
+64:x13
+64:x14
+64:x15
+64:x16
+64:x17
+64:x18
+64:x19
+64:x20
+64:x21
+64:x22
+64:x23
+64:x24
+64:x25
+64:x26
+64:x27
+64:x28
+64:x29
+64:x30
+64:x31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
Index: gdb-8.1.90/gdb/riscv-linux-nat.c
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/riscv-linux-nat.c
@@ -0,0 +1,168 @@
+/* Native-dependent code for GNU/Linux RISC-V.
+   Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "defs.h"
+#include "regcache.h"
+#include "gregset.h"
+#include "linux-nat.h"
+#include "elf.h"
+#include "riscv-tdep.h"
+
+#include <sys/ptrace.h>
+
+class riscv_linux_nat_target final : public linux_nat_target
+{
+public:
+  /* Add our register access methods.  */
+  void fetch_registers (struct regcache *regcache, int regnum) override;
+  void store_registers (struct regcache *regcache, int regnum) override;
+};
+
+static riscv_linux_nat_target the_riscv_linux_nat_target;
+
+void
+supply_gregset (struct regcache *regcache, const prgregset_t *gregs)
+{
+  int i;
+  const elf_greg_t *regp = *gregs;
+
+  for (i = 1; i < 32; i++)
+    regcache->raw_supply (i, regp + i);
+
+  /* GDB stores PC in reg 32.  Linux kernel stores it in reg 0.  */
+  regcache->raw_supply (32, regp + 0);
+
+  /* Fill the inaccessible zero register with zero.  */
+  regcache->raw_supply_zeroed (0);
+}
+
+void
+supply_fpregset (struct regcache *regcache, const prfpregset_t *fpregs)
+{
+  abort ();
+}
+
+void
+fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)
+{
+  struct gdbarch *gdbarch = regcache->arch ();
+  elf_greg_t *regp = *gregs;
+
+  if (regnum == -1 || 1)
+    {
+      for (int i = 1; i < 32; i++)
+	regcache->raw_collect (i, regp + i);
+
+      regcache->raw_collect (32, regp);
+    }
+}
+
+void
+fill_fpregset (const struct regcache *regcache,
+	       prfpregset_t *fpregs, int regnum)
+{
+  abort ();
+}
+
+/* Fetch REGNUM (or all registers if REGNUM == -1) from the target
+   using any working method.  */
+
+void
+riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
+{
+  struct gdbarch *gdbarch = regcache->arch ();
+  int tid;
+
+  tid = get_ptrace_pid (regcache->ptid());
+
+  if (regnum == -1 || (regnum >= 0 && regnum <= 32))
+    {
+      struct iovec iov;
+      elf_gregset_t regs;
+
+      iov.iov_base = &regs;
+      iov.iov_len = sizeof (regs);
+
+      if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
+		  (PTRACE_TYPE_ARG3) &iov) == -1)
+	perror_with_name (_("Couldn't get registers"));
+      else
+	supply_gregset (regcache, &regs);
+    }
+  else if (regnum >= 33 && regnum <= 64)
+    {
+      printf ("unsupported fp register read\n");
+    }
+  else if (regnum == RISCV_CSR_MISA_REGNUM)
+    {
+      /* ??? Need to add a ptrace call for this.  */
+      regcache->raw_supply_zeroed (regnum);
+    }
+  else if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
+    {
+      printf ("unsupported csr read\n");
+    }
+  else
+    {
+      printf ("unknown register read\n");
+    }
+}
+
+/* Store REGNUM (or all registers if REGNUM == -1) to the target
+   using any working method.  */
+
+void
+riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
+{
+  struct gdbarch *gdbarch = regcache->arch ();
+  int tid;
+
+  elf_greg_t reg;
+  regcache->raw_collect (regnum, &reg);
+
+  tid = get_ptrace_pid (regcache->ptid ());
+
+  if (regnum == -1 || 1)
+    {
+      struct iovec iov;
+      elf_gregset_t regs;
+
+      iov.iov_base = &regs;
+      iov.iov_len = sizeof (regs);
+
+      if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
+		  (PTRACE_TYPE_ARG3) &iov) == -1)
+	perror_with_name (_("Couldn't get registers"));
+      else
+	{
+	  fill_gregset (regcache, &regs, regnum);
+
+	  if (ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS,
+		      (PTRACE_TYPE_ARG3) &iov) == -1)
+	    perror_with_name (_("Couldn't set registers"));
+	}
+    }
+}
+
+void
+_initialize_riscv_linux_nat (void)
+{
+  /* Register the target.  */
+  linux_target = &the_riscv_linux_nat_target;
+  add_inf_child_target (&the_riscv_linux_nat_target);
+}
Index: gdb-8.1.90/gdb/riscv-linux-tdep.c
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/riscv-linux-tdep.c
@@ -0,0 +1,57 @@
+/* Target-dependent code for GNU/Linux on RISC-V processors.
+   Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "defs.h"
+#include "riscv-tdep.h"
+#include "osabi.h"
+#include "glibc-tdep.h"
+#include "linux-tdep.h"
+#include "solib-svr4.h"
+
+static void
+riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+{
+  set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
+
+  linux_init_abi (info, gdbarch);
+
+  /* GNU/Linux uses SVR4-style shared libraries.  */
+  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+
+  /* ??? This needs to depend on the ABI.  */
+  set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					 svr4_lp64_fetch_link_map_offsets);
+
+#if 0
+  /* GNU/Linux uses the dynamic linker included in the GNU C Library.  */
+  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+#endif
+
+#if 0
+  /* Enable TLS support.  */
+  set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                             svr4_fetch_objfile_link_map);
+#endif
+}
+
+void
+_initialize_riscv_linux_tdep (void)
+{
+  gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
+			  riscv_linux_init_abi);
+}
Index: gdb-8.1.90/gdb/riscv-linux-tdep.h
===================================================================
--- /dev/null
+++ gdb-8.1.90/gdb/riscv-linux-tdep.h
@@ -0,0 +1,30 @@
+/* Target-dependent header for GNU/Linux RISC-V.
+
+   Copyright (C) 2015 Free Software Foundation, Inc.
+   Contributed by Albert Ou <albert@sifive.com>.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef RISCV_LINUX_TDEP_H
+#define RISCV_LINUX_TDEP_H
+
+#include "regset.h"
+
+#define RISCV_NGREG (32)
+
+extern const struct regset riscv_linux_gregset;
+
+#endif
Index: gdb-8.1.90/gdb/riscv-tdep.c
===================================================================
--- gdb-8.1.90.orig/gdb/riscv-tdep.c
+++ gdb-8.1.90/gdb/riscv-tdep.c
@@ -889,6 +889,18 @@ public:
       LUI,
       SD,
       SW,
+      /* These are needed for software breakopint support.  */
+      JAL,
+      JALR,
+      BEQ,
+      BNE,
+      BLT,
+      BGE,
+      BLTU,
+      BGEU,
+      /* These are needed for stepping over atomic sequences.  */
+      LR,
+      SC,
 
       /* Other instructions are not interesting during the prologue scan, and
 	 are ignored.  */
@@ -945,6 +957,12 @@ private:
     return (opcode >> offset) & 0x1F;
   }
 
+  /* Extract 5 bit register field at OFFSET from instruction OPCODE.  */
+  int decode_register_index_short (unsigned long opcode, int offset)
+  {
+    return ((opcode >> offset) & 0x7) + 8;
+  }
+
   /* Helper for DECODE, decode 32-bit R-type instruction.  */
   void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
   {
@@ -996,6 +1014,36 @@ private:
     m_imm.s = EXTRACT_UTYPE_IMM (ival);
   }
 
+  /* Helper for DECODE, decode 32-bit J-type instruction.  */
+  void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
+  {
+    m_opcode = opcode;
+    m_rd = decode_register_index (ival, OP_SH_RD);
+    m_imm.s = EXTRACT_UJTYPE_IMM (ival);
+  }
+
+  /* Helper for DECODE, decode 32-bit J-type instruction.  */
+  void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
+  {
+    m_opcode = opcode;
+    m_imm.s = EXTRACT_RVC_J_IMM (ival);
+  }
+
+  void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
+  {
+    m_opcode = opcode;
+    m_rs1 = decode_register_index (ival, OP_SH_RS1);
+    m_rs2 = decode_register_index (ival, OP_SH_RS2);
+    m_imm.s = EXTRACT_SBTYPE_IMM (ival);
+  }
+
+  void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
+  {
+    m_opcode = opcode;
+    m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
+    m_imm.s = EXTRACT_RVC_B_IMM (ival);
+  }
+
   /* Fetch instruction from target memory at ADDR, return the content of
      the instruction, and update LEN with the instruction length.  */
   static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
@@ -1092,32 +1140,83 @@ riscv_insn::decode (struct gdbarch *gdba
 	decode_s_type_insn (SD, ival);
       else if (is_sw_insn (ival))
 	decode_s_type_insn (SW, ival);
+      else if (is_jal_insn (ival))
+	decode_j_type_insn (JAL, ival);
+      else if (is_jalr_insn (ival))
+	decode_i_type_insn (JALR, ival);
+      else if (is_beq_insn (ival))
+	decode_b_type_insn (BEQ, ival);
+      else if (is_bne_insn (ival))
+	decode_b_type_insn (BNE, ival);
+      else if (is_blt_insn (ival))
+	decode_b_type_insn (BLT, ival);
+      else if (is_bge_insn (ival))
+	decode_b_type_insn (BGE, ival);
+      else if (is_bltu_insn (ival))
+	decode_b_type_insn (BLTU, ival);
+      else if (is_bgeu_insn (ival))
+	decode_b_type_insn (BGEU, ival);
+      else if (is_lr_w_insn (ival))
+	decode_r_type_insn (LR, ival);
+      else if (is_lr_d_insn (ival))
+	decode_r_type_insn (LR, ival);
+      else if (is_sc_w_insn (ival))
+	decode_r_type_insn (SC, ival);
+      else if (is_sc_d_insn (ival))
+	decode_r_type_insn (SC, ival);
       else
 	/* None of the other fields are valid in this case.  */
 	m_opcode = OTHER;
     }
   else if (m_length == 2)
     {
-      if (is_c_add_insn (ival))
+      int xlen = riscv_isa_xlen (gdbarch);
+
+      /* C_ADD and C_JALR have the same opcode.  If RS2 is 0, then this is a
+	 C_JALR.  So must try to match C_JALR first as it has more bits in
+	 mask.  */
+      if (is_c_jalr_insn (ival))
+	decode_cr_type_insn (JALR, ival);
+      else if (is_c_add_insn (ival))
 	decode_cr_type_insn (ADD, ival);
-      else if (is_c_addw_insn (ival))
+      /* C_ADDW is RV64 and RV128 only.  */
+      else if (xlen != 4 && is_c_addw_insn (ival))
 	decode_cr_type_insn (ADDW, ival);
       else if (is_c_addi_insn (ival))
 	decode_ci_type_insn (ADDI, ival);
-      else if (is_c_addiw_insn (ival))
+      /* C_ADDIW and C_JAL have the same opcode.  C_ADDIW is RV64 and RV128
+	 only and C_JAL is RV32 only.  */
+      else if (xlen != 4 && is_c_addiw_insn (ival))
 	decode_ci_type_insn (ADDIW, ival);
+      else if (xlen == 4 && is_c_jal_insn (ival))
+	decode_cj_type_insn (JAL, ival);
+      /* C_ADDI16SP and C_LUI have the same opcode.  If RD is 2, then this is a
+	 C_ADDI16SP.  So must try to match C_ADDI16SP first as it has more bits
+	 in mask.  */
       else if (is_c_addi16sp_insn (ival))
 	{
 	  m_opcode = ADDI;
 	  m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
 	  m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
 	}
-      else if (is_lui_insn (ival))
+      else if (is_c_lui_insn (ival))
 	m_opcode = OTHER;
-      else if (is_c_sd_insn (ival))
+      /* C_SD and C_FSW have the same opcode.  If C_SD is RV64 and RV128 only,
+	 and C_FSW is RV32 only.  */
+      else if (xlen != 4 && is_c_sd_insn (ival))
 	m_opcode = OTHER;
-      else if (is_sw_insn (ival))
+      else if (is_c_sw_insn (ival))
 	m_opcode = OTHER;
+      /* C_JR and C_MV have the same opcode.  If RS2 is 0, then this is a C_JR.
+	 So must try to match C_JR first as it ahs more bits in mask.  */
+      else if (is_c_jr_insn (ival))
+	decode_cr_type_insn (JALR, ival);
+      else if (is_c_j_insn (ival))
+	decode_cj_type_insn (JAL, ival);
+      else if (is_c_beqz_insn (ival))
+	decode_cb_type_insn (BEQ, ival);
+      else if (is_c_bnez_insn (ival))
+	decode_cb_type_insn (BNE, ival);
       else
 	/* None of the other fields of INSN are valid in this case.  */
 	m_opcode = OTHER;
@@ -2433,7 +2532,7 @@ riscv_gdbarch_init (struct gdbarch_info
   struct gdbarch *gdbarch;
   struct gdbarch_tdep *tdep;
   struct gdbarch_tdep tmp_tdep;
-  bool has_compressed_isa = false;
+  // bool has_compressed_isa = false;
   int i;
 
   /* Ideally, we'd like to get as much information from the target for
@@ -2466,7 +2565,7 @@ riscv_gdbarch_init (struct gdbarch_info
 
       if (e_flags & EF_RISCV_RVC)
 	{
-	  has_compressed_isa = true;
+	  // has_compressed_isa = true;
 	  tmp_tdep.core_features |= (1 << ('C' - 'A'));
 	}
 
@@ -2499,6 +2598,7 @@ riscv_gdbarch_init (struct gdbarch_info
   for (arches = gdbarch_list_lookup_by_info (arches, &info);
        arches != NULL;
        arches = gdbarch_list_lookup_by_info (arches->next, &info))
+    /* ??? Shouldn't this also check tmp_tdep.core_features?  */
     if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
       return arches->gdbarch;
 
@@ -2538,7 +2638,8 @@ riscv_gdbarch_init (struct gdbarch_info
   set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
 
   /* Functions to analyze frames.  */
-  set_gdbarch_decr_pc_after_break (gdbarch, (has_compressed_isa ? 2 : 4));
+  /* ??? Must hardwire to 4 to match breakpoints.  */
+  // set_gdbarch_decr_pc_after_break (gdbarch, (has_compressed_isa ? 4 : 4));
   set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
   set_gdbarch_frame_align (gdbarch, riscv_frame_align);
@@ -2562,6 +2663,9 @@ riscv_gdbarch_init (struct gdbarch_info
     user_reg_add (gdbarch, riscv_register_aliases[i].name,
 		  value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
 
+  /* Hook in OS ABI-specific overrides, if they have been registered.  */
+  gdbarch_init_osabi (info, gdbarch);
+
   return gdbarch;
 }
 
@@ -2628,6 +2732,145 @@ riscv_invalidate_inferior_data (struct i
     }
 }
 
+/* This decodes the current instruction and determines the address of the
+   next instruction.  */
+
+static CORE_ADDR
+riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
+{
+  struct gdbarch *gdbarch = regcache->arch ();
+  struct riscv_insn insn;
+  CORE_ADDR next_pc;
+
+  insn.decode (gdbarch, pc);
+  next_pc = pc + insn.length ();
+
+  if (insn.opcode () == riscv_insn::JAL)
+    next_pc = pc + insn.imm_signed ();
+  else if (insn.opcode () == riscv_insn::JALR)
+    {
+      LONGEST source;
+      regcache->cooked_read (insn.rs1 (), &source);
+      next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR)0x1;
+    }
+  else if (insn.opcode () == riscv_insn::BEQ)
+    {
+      LONGEST src1, src2;
+      regcache->cooked_read (insn.rs1 (), &src1);
+      regcache->cooked_read (insn.rs2 (), &src2);
+      if (src1 == src2)
+	next_pc = pc + insn.imm_signed ();
+    }
+  else if (insn.opcode () == riscv_insn::BNE)
+    {
+      LONGEST src1, src2;
+      regcache->cooked_read (insn.rs1 (), &src1);
+      regcache->cooked_read (insn.rs2 (), &src2);
+      if (src1 != src2)
+	next_pc = pc + insn.imm_signed ();
+    }
+  else if (insn.opcode () == riscv_insn::BLT)
+    {
+      LONGEST src1, src2;
+      regcache->cooked_read (insn.rs1 (), &src1);
+      regcache->cooked_read (insn.rs2 (), &src2);
+      if (src1 < src2)
+	next_pc = pc + insn.imm_signed ();
+    }
+  else if (insn.opcode () == riscv_insn::BGE)
+    {
+      LONGEST src1, src2;
+      regcache->cooked_read (insn.rs1 (), &src1);
+      regcache->cooked_read (insn.rs2 (), &src2);
+      if (src1 >= src2)
+	next_pc = pc + insn.imm_signed ();
+    }
+  else if (insn.opcode () == riscv_insn::BLTU)
+    {
+      ULONGEST src1, src2;
+      regcache->cooked_read (insn.rs1 (), &src1);
+      regcache->cooked_read (insn.rs2 (), &src2);
+      if (src1 < src2)
+	next_pc = pc + insn.imm_signed ();
+    }
+  else if (insn.opcode () == riscv_insn::BGEU)
+    {
+      ULONGEST src1, src2;
+      regcache->cooked_read (insn.rs1 (), &src1);
+      regcache->cooked_read (insn.rs2 (), &src2);
+      if (src1 >= src2)
+	next_pc = pc + insn.imm_signed ();
+    }
+
+  return next_pc;
+}
+
+/* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
+   for the end of the sequence and put the breakpoint there.  */
+
+static bool
+riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
+			       CORE_ADDR *next_pc)
+{
+  struct gdbarch *gdbarch = regcache->arch ();
+  struct riscv_insn insn;
+  CORE_ADDR cur_step_pc = pc;
+  CORE_ADDR last_addr = 0;
+
+  /* First instruction has to be a load reserved.  */
+  insn.decode (gdbarch, cur_step_pc);
+  if (insn.opcode () != riscv_insn::LR)
+    return false;
+  cur_step_pc = cur_step_pc + insn.length ();
+  
+  /* Next instruction should be branch to exit.  */
+  insn.decode (gdbarch, cur_step_pc);
+  if (insn.opcode () != riscv_insn::BNE)
+    return false;
+  last_addr = cur_step_pc + insn.imm_signed ();
+  cur_step_pc = cur_step_pc + insn.length ();
+
+  /* Next instruction should be store conditional.  */
+  insn.decode (gdbarch, cur_step_pc);
+  if (insn.opcode () != riscv_insn::SC)
+    return false;
+  cur_step_pc = cur_step_pc + insn.length ();
+  
+  /* Next instruction should be branch to start.  */
+  insn.decode (gdbarch, cur_step_pc);
+  if (insn.opcode () != riscv_insn::BNE)
+    return false;
+  if (pc != (cur_step_pc + insn.imm_signed ()))
+    return false;
+  cur_step_pc = cur_step_pc + insn.length ();
+
+  /* We should now be at the end of the sequence.  */
+  if (cur_step_pc != last_addr)
+    return false;
+
+  *next_pc = cur_step_pc;
+  return true;
+}
+
+/* This is called just before we want to resume the inferior, if we want to
+   single-step it but there is no hardware or kernel single-step support.  We
+   find the target of the coming instruction and breakpoint it.  */
+
+std::vector<CORE_ADDR>
+riscv_software_single_step (struct regcache *regcache)
+{
+  CORE_ADDR pc, next_pc;
+
+  pc = regcache_read_pc (regcache);
+
+  if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
+    return {next_pc};
+
+  next_pc = riscv_next_pc (regcache, pc);
+
+  return {next_pc};
+}
+
 void
 _initialize_riscv_tdep (void)
 {
@@ -2673,6 +2916,9 @@ of the inferior call mechanism."),
 		  &showriscvcmdlist, "show riscv ", 0, &showlist);
 
 
+  /* ??? After c.ebreak, pc is bp addr + 4.  QEMU bug?  Linux kernel bug?  */
+  /* ??? use-compressed-breakpoints command doesn't work, because doesn't
+     change decr_pc_after_break value.  */
   use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
   add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
 				&use_compressed_breakpoints,
Index: gdb-8.1.90/gdb/riscv-tdep.h
===================================================================
--- gdb-8.1.90.orig/gdb/riscv-tdep.h
+++ gdb-8.1.90/gdb/riscv-tdep.h
@@ -39,11 +39,11 @@ enum
   RISCV_LAST_FP_REGNUM = 64,	/* Last Floating Point Register */
 
   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
-#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
+#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
 #include "opcode/riscv-opc.h"
 #undef DECLARE_CSR
   RISCV_LAST_CSR_REGNUM = 4160,
-  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10,
+  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
 
   RISCV_PRIV_REGNUM = 4161,
 
@@ -76,4 +76,8 @@ struct gdbarch_tdep
   unsigned core_features;
 };
 
+/* Single step based on where the current instruction will take us.  */
+extern std::vector<CORE_ADDR>
+riscv_software_single_step (struct regcache *regcache);
+
 #endif /* RISCV_TDEP_H */
Index: gdb-8.1.90/include/gdb/sim-riscv.h
===================================================================
--- /dev/null
+++ gdb-8.1.90/include/gdb/sim-riscv.h
@@ -0,0 +1,98 @@
+/* This file defines the interface between the RISC-V simulator and GDB.
+
+   Copyright (C) 2005-2015 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* Order has to match gdb riscv-tdep list.  */
+enum sim_riscv_regnum {
+  SIM_RISCV_ZERO_REGNUM = 0,
+  SIM_RISCV_RA_REGNUM,
+  SIM_RISCV_SP_REGNUM,
+  SIM_RISCV_GP_REGNUM,
+  SIM_RISCV_TP_REGNUM,
+  SIM_RISCV_T0_REGNUM,
+  SIM_RISCV_T1_REGNUM,
+  SIM_RISCV_T2_REGNUM,
+  SIM_RISCV_S0_REGNUM,
+#define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM
+  SIM_RISCV_S1_REGNUM,
+  SIM_RISCV_A0_REGNUM,
+  SIM_RISCV_A1_REGNUM,
+  SIM_RISCV_A2_REGNUM,
+  SIM_RISCV_A3_REGNUM,
+  SIM_RISCV_A4_REGNUM,
+  SIM_RISCV_A5_REGNUM,
+  SIM_RISCV_A6_REGNUM,
+  SIM_RISCV_A7_REGNUM,
+  SIM_RISCV_S2_REGNUM,
+  SIM_RISCV_S3_REGNUM,
+  SIM_RISCV_S4_REGNUM,
+  SIM_RISCV_S5_REGNUM,
+  SIM_RISCV_S6_REGNUM,
+  SIM_RISCV_S7_REGNUM,
+  SIM_RISCV_S8_REGNUM,
+  SIM_RISCV_S9_REGNUM,
+  SIM_RISCV_S10_REGNUM,
+  SIM_RISCV_S11_REGNUM,
+  SIM_RISCV_T3_REGNUM,
+  SIM_RISCV_T4_REGNUM,
+  SIM_RISCV_T5_REGNUM,
+  SIM_RISCV_T6_REGNUM,
+  SIM_RISCV_PC_REGNUM,
+  SIM_RISCV_FT0_REGNUM,
+#define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM
+  SIM_RISCV_FT1_REGNUM,
+  SIM_RISCV_FT2_REGNUM,
+  SIM_RISCV_FT3_REGNUM,
+  SIM_RISCV_FT4_REGNUM,
+  SIM_RISCV_FT5_REGNUM,
+  SIM_RISCV_FT6_REGNUM,
+  SIM_RISCV_FT7_REGNUM,
+  SIM_RISCV_FS0_REGNUM,
+  SIM_RISCV_FS1_REGNUM,
+  SIM_RISCV_FA0_REGNUM,
+  SIM_RISCV_FA1_REGNUM,
+  SIM_RISCV_FA2_REGNUM,
+  SIM_RISCV_FA3_REGNUM,
+  SIM_RISCV_FA4_REGNUM,
+  SIM_RISCV_FA5_REGNUM,
+  SIM_RISCV_FA6_REGNUM,
+  SIM_RISCV_FA7_REGNUM,
+  SIM_RISCV_FS2_REGNUM,
+  SIM_RISCV_FS3_REGNUM,
+  SIM_RISCV_FS4_REGNUM,
+  SIM_RISCV_FS5_REGNUM,
+  SIM_RISCV_FS6_REGNUM,
+  SIM_RISCV_FS7_REGNUM,
+  SIM_RISCV_FS8_REGNUM,
+  SIM_RISCV_FS9_REGNUM,
+  SIM_RISCV_FS10_REGNUM,
+  SIM_RISCV_FS11_REGNUM,
+  SIM_RISCV_FT8_REGNUM,
+  SIM_RISCV_FT9_REGNUM,
+  SIM_RISCV_FT10_REGNUM,
+  SIM_RISCV_FT11_REGNUM,
+#define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM
+
+#define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1
+#define DECLARE_CSR(name, num) SIM_RISCV_ ## num ## _REGNUM,
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+#define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1
+
+  SIM_RISCV_LAST_REGNUM
+};

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File riscv.patch of Package gdb (Revision b3be5bf52a648a61bdcf03bb83b290a3)

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