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home:dirkmueller:acdc:sp5-rebuild
qemu.29315
target-arm-Update-REV-PUNPK-for-pred_des.patch
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File target-arm-Update-REV-PUNPK-for-pred_des.patch of Package qemu.29315
From: Richard Henderson <richard.henderson@linaro.org> Date: Tue, 12 Jan 2021 20:26:50 -1000 Subject: target/arm: Update REV, PUNPK for pred_desc Git-commit: 70acaafef2e053a312d54c09b6721c730690e72c Update all users of do_perm_pred2 for the new predicate descriptor field definitions. Cc: qemu-stable@nongnu.org Buglink: https://bugs.launchpad.net/bugs/1908551 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bruce Rogers <brogers@suse.com> --- target/arm/sve_helper.c | 8 ++++---- target/arm/translate-sve.c | 13 ++++--------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 7eec4b6b73a273ecaf2fc218d8d4..844db08bd577016081329d6c4002 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2036,8 +2036,8 @@ static uint8_t reverse_bits_8(uint8_t x, int n) void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + int esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); intptr_t i, oprsz_2 = oprsz / 2; if (oprsz <= 8) { @@ -2066,8 +2066,8 @@ void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc) void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc) { - intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + intptr_t high = FIELD_EX32(pred_desc, PREDDESC, DATA); uint64_t *d = vd; intptr_t i; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 0baca176a090001de915a7866af4..27402af23c0b58fa94b4ac185951 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2145,19 +2145,14 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, TCGv_ptr t_d = tcg_temp_new_ptr(); TCGv_ptr t_n = tcg_temp_new_ptr(); TCGv_i32 t_desc; - int desc; + uint32_t desc = 0; tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); - /* Predicate sizes may be smaller and cannot use simd_desc. - We cannot round up, as we do elsewhere, because we need - the exact size for ZIP2 and REV. We retain the style for - the other helpers for consistency. */ - - desc = vsz - 2; - desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); - desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); + desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); + desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); + desc = FIELD_DP32(desc, PREDDESC, DATA, high_odd); t_desc = tcg_const_i32(desc); fn(t_d, t_n, t_desc);
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