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File ibm434505-spu of Package libffi43
2008-10-13 Andrew Pinski <andrew_pinski@playstation.sony.com> Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com> Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> Grace Cao <grace_cao@playstation.sony.com> * doc/invoke.texi (-mgen-cell-microcode): Document. (-mwarn-cell-microcode): Document. * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate. * rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype. * config/rs6000/rs6000.opt (mgen-cell-microcode): New option. (mwarn-cell-microcode): New option. * rs6000/rs6000.c (rs6000_cell_dont_microcode): Delete unused variable. (rs6000_override_options): Set rs6000_gen_cell_microcode if tuning for cell and not already set. Turn off string instructions if not generating cell microcode. (rs6000_final_prescan_insn): New function that warns about microcoded instructions. * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define. * config/rs6000/rs6000.md Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if the instruction would have been microcoded on the Cell. Set cell_micro to always on unnamed patterns for the string instructions. (cell_micro): Update definition, remove load/store conditional microcoded. (sign_extend:DI): Define new pattern for non microcoded version. (sign_extend:SI): Likewise. (compare (div:P)): Set cell_micro to not. (andsi3): Define as an expand. (andsi3_mc): New pattern. (andsi3_nomc): New pattern. (andsi3_internal0_nomc): New pattern. (andsi3_internal2): Rename to ... (andsi3_internal2_mc): this and enable iff generating microcode. (andsi3_internal3): Rename to ... (andsi3_internal3_mc): this and enable iff generating microcode. (andsi3_internal4): Enable iif generating microcode. (andsi3_internal5): Rename to .. (andsi3_internal5_mc): this and enable iff generating microcode. (andsi3_internal5_nomc): New pattern. (extzvdi_internal1): Enable iff generating microcode. (extzvdi_internal2): Likewise. (rotlsi3_internal7): Set cell_micro to always if non immediate form. (anddi3): Change to expand. (anddi3_mc): Rename from anddi3. (anddi3_no_mc): New pattern. (anddi3_internal2): Rename to .. (anddi3_internal2_mc): this and enable iff generating microcode. (anddi3_internal2_nomc): New pattern. (anddi3_internal3): Rename to .. (anddi3_internal3_mc): this and enable iff generating microcode. (anddi3_internal3_nomc): New pattern. (movti_string): Set cell_micro to always if TARGET_STRING. (stmsi8): Set cell_micro to always. (stmsi7): Likewise. (stmsi6): Likewise. (stmsi5): Likewise. (stmsi4): Likewise. (stmsi3): Likewise. (stmsi8_power): Likewise. (stmsi7_power): Likewise. (stmsi6_power): Likewise. (stmsi5_power): Likewise. (stmsi4_power): Likewise. (stmsi3_power): Likewise. (movsi_update2): Enable iff generating microcode. (movhi_update3): Likewise. (lmw): Set cell_micro to always. Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi.orig 2009-11-20 13:52:03.000000000 +0100 +++ gcc/doc/invoke.texi 2009-11-20 13:52:14.000000000 +0100 @@ -709,6 +709,7 @@ See RS/6000 and PowerPC Options. -mspe -mno-spe @gol -mspe=yes -mspe=no @gol -mpaired @gol +-mgen-cell-microcode -mwarn-cell-microcode @gol -mvrsave -mno-vrsave @gol -mmulhw -mno-mulhw @gol -mdlmzb -mno-dlmzb @gol @@ -13034,6 +13035,15 @@ enhancements. @opindex mno-vrsave Generate VRSAVE instructions when generating AltiVec code. +@item -mgen-cell-microcode +@opindex mgen-cell-microcode +Generate Cell microcode instructions + +@item -mwarn-cell-microcode +@opindex mwarn-cell-microcode +Warning when a Cell microcode instruction is going to emitted. An example +of a Cell microcode instruction is a variable shift. + @item -msecure-plt @opindex msecure-plt Generate code that allows ld and ld.so to build executables and shared Index: gcc/config/rs6000/predicates.md =================================================================== --- gcc/config/rs6000/predicates.md.orig 2008-11-05 22:19:47.000000000 +0100 +++ gcc/config/rs6000/predicates.md 2009-11-20 13:52:14.000000000 +0100 @@ -104,6 +104,14 @@ || REGNO (op) > LAST_VIRTUAL_REGISTER || CR_REGNO_NOT_CR0_P (REGNO (op))"))) +;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0. +(define_predicate "cc_reg_not_micro_cr0_operand" + (and (match_operand 0 "register_operand") + (match_test "GET_CODE (op) != REG + || REGNO (op) > LAST_VIRTUAL_REGISTER + || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op))) + || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))"))) + ;; Return 1 if op is a constant integer valid for D field ;; or non-special register register. (define_predicate "reg_or_short_operand" Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h.orig 2008-11-05 22:19:47.000000000 +0100 +++ gcc/config/rs6000/rs6000-protos.h 2009-11-20 13:52:14.000000000 +0100 @@ -179,5 +179,7 @@ extern void rs6000_cpu_cpp_builtins (str char *output_call (rtx, rtx *, int, int); #endif +void rs6000_final_prescan_insn (rtx, rtx *operand, int num_operands); + extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER]; #endif /* rs6000-protos.h */ Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt.orig 2008-02-19 10:55:53.000000000 +0100 +++ gcc/config/rs6000/rs6000.opt 2009-11-20 13:52:14.000000000 +0100 @@ -233,6 +233,14 @@ mlongcall Target Report Var(rs6000_default_long_calls) Avoid all range limits on call instructions +mgen-cell-microcode +Target Report Var(rs6000_gen_cell_microcode) Init(-1) +Generate Cell microcode + +mwarn-cell-microcode +Target Var(rs6000_warn_cell_microcode) Init(0) Warning +Emitting warning when a Cell microcode is emitted + mwarn-altivec-long Target Var(rs6000_warn_altivec_long) Init(1) Warn about deprecated 'vector long ...' AltiVec type usage Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c.orig 2009-11-20 13:52:05.000000000 +0100 +++ gcc/config/rs6000/rs6000.c 2009-11-20 13:52:14.000000000 +0100 @@ -143,8 +143,6 @@ struct rs6000_cpu_select rs6000_select[3 { (const char *)0, "-mtune=", 1, 0 }, }; -static GTY(()) bool rs6000_cell_dont_microcode; - /* Always emit branch hint bits. */ static GTY(()) bool rs6000_always_hint; @@ -1529,9 +1527,16 @@ rs6000_override_options (const char *def if (TARGET_E500) rs6000_isel = 1; + /* Disable cell micro code if we are optimizing for the cell + and not optimizing for size. */ + if (rs6000_gen_cell_microcode == -1) + rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL + && !optimize_size); + /* If we are optimizing big endian systems for space, use the load/store - multiple and string instructions. */ - if (BYTES_BIG_ENDIAN && optimize_size) + multiple and string instructions unless we are not generating + Cell microcode. */ + if (BYTES_BIG_ENDIAN && optimize_size && !rs6000_gen_cell_microcode) target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems @@ -22177,4 +22182,30 @@ rs6000_stack_protect_fail (void) : default_external_stack_protect_fail (); } +void +rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED, + int num_operands ATTRIBUTE_UNUSED) +{ + if (rs6000_warn_cell_microcode) + { + const char *temp; + int insn_code_number = recog_memoized (insn); + + /* Punt on insns we cannot recognize. */ + if (insn_code_number < 0) + return; + + temp = get_insn_template (insn_code_number, insn); + + if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS) + warning (OPT_mwarn_cell_microcode, + "emitting microcode insn %s\t[%s] #%d", + temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn)); + else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL) + warning (OPT_mwarn_cell_microcode, + "emitting conditional microcode insn %s\t[%s] #%d", + temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn)); + } +} + #include "gt-rs6000.h" Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h.orig 2009-11-20 13:52:05.000000000 +0100 +++ gcc/config/rs6000/rs6000.h 2009-11-20 13:52:14.000000000 +0100 @@ -1855,7 +1855,8 @@ do { \ /* Define this if some processing needs to be done immediately before emitting code for an insn. */ -/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ +#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ + rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md.orig 2009-11-20 13:51:56.000000000 +0100 +++ gcc/config/rs6000/rs6000.md 2009-11-20 13:52:14.000000000 +0100 @@ -138,19 +138,11 @@ ;; If this instruction is microcoded on the CELL processor -; The default for load and stores is conditional -; The default for load extended and the recorded instructions is always microcoded +; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded (define_attr "cell_micro" "not,conditional,always" - (if_then_else (ior (ior (eq_attr "type" "load") - (eq_attr "type" "store")) - (ior (eq_attr "type" "fpload") - (eq_attr "type" "fpstore"))) - (const_string "conditional") - (if_then_else (ior (eq_attr "type" "load_ext") - (ior (eq_attr "type" "compare") - (eq_attr "type" "delayed_compare"))) + (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare") (const_string "always") - (const_string "not")))) + (const_string "not"))) (automata_option "ndfa") @@ -248,7 +240,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:DI 2 ""))] @@ -274,7 +266,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") @@ -307,7 +299,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:DI 2 ""))] @@ -333,7 +325,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") @@ -355,13 +347,20 @@ (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && rs6000_gen_cell_microcode" "@ lha%U1%X1 %0,%1 extsh %0,%1" [(set_attr "type" "load_ext,exts")]) (define_insn "" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))] + "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" + "extsh %0,%1" + [(set_attr "type" "exts")]) + +(define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -374,7 +373,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:DI 2 ""))] @@ -400,7 +399,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") @@ -422,13 +421,20 @@ (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && rs6000_gen_cell_microcode" "@ lwa%U1%X1 %0,%1 extsw %0,%1" [(set_attr "type" "load_ext,exts")]) (define_insn "" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))] + "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" + "extsw %0,%1" + [(set_attr "type" "exts")]) + +(define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -441,7 +447,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:DI 2 ""))] @@ -467,7 +473,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") @@ -508,7 +514,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] @@ -534,7 +540,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") @@ -582,7 +588,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] @@ -608,7 +614,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") @@ -675,7 +681,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:HI 2 ""))] @@ -701,7 +707,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:HI 0 "gpc_reg_operand" "") @@ -749,7 +755,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:HI 2 ""))] @@ -775,7 +781,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:HI 0 "gpc_reg_operand" "") @@ -844,7 +850,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] @@ -870,7 +876,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") @@ -892,13 +898,20 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] - "" + "rs6000_gen_cell_microcode" "@ lha%U1%X1 %0,%1 {exts|extsh} %0,%1" [(set_attr "type" "load_ext,exts")]) (define_insn "" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))] + "!rs6000_gen_cell_microcode" + "{exts|extsh} %0,%1" + [(set_attr "type" "exts")]) + +(define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) (const_int 0))) @@ -911,7 +924,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 2 ""))] @@ -1468,7 +1481,7 @@ }) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1651,7 +1664,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:P 2 ""))] @@ -1677,7 +1690,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:P 0 "gpc_reg_operand" "") @@ -2332,7 +2345,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) @@ -2392,7 +2405,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) @@ -2584,7 +2597,8 @@ {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3 #" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8,12") + (set_attr "cell_micro" "not")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") @@ -2613,7 +2627,8 @@ {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0 #" [(set_attr "type" "compare") - (set_attr "length" "8,12")]) + (set_attr "length" "8,12") + (set_attr "cell_micro" "not")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") @@ -2807,12 +2822,21 @@ ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all ;; those rotate-and-mask operations. Thus, the AND insns come first. -(define_insn "andsi3" +(define_expand "andsi3" + [(parallel + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "and_operand" ""))) + (clobber (match_scratch:CC 3 ""))])] + "" + "") + +(define_insn "andsi3_mc" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "?r,T,K,L"))) (clobber (match_scratch:CC 3 "=X,X,x,x"))] - "" + "rs6000_gen_cell_microcode" "@ and %0,%1,%2 {rlinm|rlwinm} %0,%1,0,%m2,%M2 @@ -2820,18 +2844,38 @@ {andiu.|andis.} %0,%1,%u2" [(set_attr "type" "*,*,compare,compare")]) +(define_insn "andsi3_nomc" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "and_operand" "?r,T"))) + (clobber (match_scratch:CC 3 "=X,X"))] + "!rs6000_gen_cell_microcode" + "@ + and %0,%1,%2 + {rlinm|rlwinm} %0,%1,0,%m2,%M2") + +(define_insn "andsi3_internal0_nomc" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "and_operand" "?r,T")))] + "!rs6000_gen_cell_microcode" + "@ + and %0,%1,%2 + {rlinm|rlwinm} %0,%1,0,%m2,%M2") + + ;; Note to set cr's other than cr0 we do the and immediate and then ;; the test again -- this avoids a mfcr which on the higher end ;; machines causes an execution serialization -(define_insn "*andsi3_internal2" +(define_insn "*andsi3_internal2_mc" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_32BIT" + "TARGET_32BIT && rs6000_gen_cell_microcode" "@ and. %3,%1,%2 {andil.|andi.} %3,%1,%b2 @@ -2844,14 +2888,14 @@ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") (set_attr "length" "4,4,4,4,8,8,8,8")]) -(define_insn "*andsi3_internal3" +(define_insn "*andsi3_internal3_mc" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_64BIT" + "TARGET_64BIT && rs6000_gen_cell_microcode" "@ # {andil.|andi.} %3,%1,%b2 @@ -2865,7 +2909,7 @@ (set_attr "length" "8,4,4,4,8,8,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") (match_operand:GPR 2 "and_operand" "")) (const_int 0))) @@ -2910,7 +2954,7 @@ (and:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_32BIT" + "TARGET_32BIT && rs6000_gen_cell_microcode" "@ and. %0,%1,%2 {andil.|andi.} %0,%1,%b2 @@ -2923,7 +2967,7 @@ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") (set_attr "length" "4,4,4,4,8,8,8,8")]) -(define_insn "*andsi3_internal5" +(define_insn "*andsi3_internal5_mc" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) @@ -2932,7 +2976,7 @@ (and:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_64BIT" + "TARGET_64BIT && rs6000_gen_cell_microcode" "@ # {andil.|andi.} %0,%1,%b2 @@ -2945,8 +2989,22 @@ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") (set_attr "length" "8,4,4,4,8,8,8,8")]) +(define_insn "*andsi3_internal5_nomc" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,r,K,L,T")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 "=X,X,x,x,X"))] + "TARGET_64BIT && !rs6000_gen_cell_microcode" + "#" + [(set_attr "type" "compare") + (set_attr "length" "8,8,8,8,8")]) + (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "and_operand" "")) (const_int 0))) @@ -3077,7 +3135,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:SI 4 "boolean_operator" [(match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "gpc_reg_operand" "")]) @@ -3106,7 +3164,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:SI 4 "boolean_operator" [(match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "gpc_reg_operand" "")]) @@ -3165,7 +3223,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:SI 4 "boolean_operator" [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) (match_operand:SI 2 "gpc_reg_operand" "")]) @@ -3194,7 +3252,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:SI 4 "boolean_operator" [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) (match_operand:SI 2 "gpc_reg_operand" "")]) @@ -3231,7 +3289,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:SI 4 "boolean_operator" [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) @@ -3260,7 +3318,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:SI 4 "boolean_operator" [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) @@ -3767,7 +3825,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" "")) @@ -3818,7 +3876,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" "")) @@ -3859,7 +3917,7 @@ (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) (clobber (match_scratch:DI 4 "=r"))] - "TARGET_64BIT" + "TARGET_64BIT && rs6000_gen_cell_microcode" "* { int start = INTVAL (operands[3]) & 63; @@ -3882,7 +3940,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] - "TARGET_64BIT" + "TARGET_64BIT && rs6000_gen_cell_microcode" "* { int start = INTVAL (operands[3]) & 63; @@ -3923,7 +3981,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -3953,7 +4011,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -3996,7 +4054,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) @@ -4032,7 +4090,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) @@ -4055,7 +4113,11 @@ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] "" - "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") + "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff" + [(set (attr "cell_micro") + (if_then_else (match_operand:SI 2 "const_int_operand" "") + (const_string "not") + (const_string "always")))]) (define_insn "*rotlsi3_internal8" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") @@ -4075,7 +4137,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:QI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -4111,7 +4173,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:QI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -4158,7 +4220,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:HI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -4194,7 +4256,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:HI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -4397,7 +4459,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -4430,7 +4492,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -4642,7 +4704,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -4675,7 +4737,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -4717,7 +4779,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:QI @@ -4753,7 +4815,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:QI @@ -4796,7 +4858,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:HI @@ -4832,7 +4894,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI (subreg:HI @@ -4960,7 +5022,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -5024,7 +5086,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -6684,7 +6746,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "gpc_reg_operand" "")) (const_int 0))) @@ -6748,7 +6810,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -6778,7 +6840,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -6821,7 +6883,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_cint_operand" "")) @@ -6857,7 +6919,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_cint_operand" "")) @@ -6903,7 +6965,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (subreg:QI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -6939,7 +7001,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (subreg:QI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -6985,7 +7047,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (subreg:HI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7021,7 +7083,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (subreg:HI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7067,7 +7129,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (subreg:SI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7103,7 +7165,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI (subreg:SI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7231,7 +7293,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -7265,7 +7327,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -7307,7 +7369,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -7341,7 +7403,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "const_int_operand" "")) @@ -7403,7 +7465,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -7433,7 +7495,7 @@ (set_attr "length" "4,4,8,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) @@ -7541,12 +7603,21 @@ (const_int 0)))] "") -(define_insn "anddi3" +(define_expand "anddi3" + [(parallel + [(set (match_operand:DI 0 "gpc_reg_operand" "") + (and:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "and64_2_operand" ""))) + (clobber (match_scratch:CC 3 ""))])] + "TARGET_POWERPC64" + "") + +(define_insn "anddi3_mc" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && rs6000_gen_cell_microcode" "@ and %0,%1,%2 rldic%B2 %0,%1,0,%S2 @@ -7557,6 +7628,19 @@ [(set_attr "type" "*,*,*,compare,compare,*") (set_attr "length" "4,4,4,4,4,8")]) +(define_insn "anddi3_nomc" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:DI 2 "and64_2_operand" "?r,S,T,t"))) + (clobber (match_scratch:CC 3 "=X,X,X,X"))] + "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" + "@ + and %0,%1,%2 + rldic%B2 %0,%1,0,%S2 + rlwinm %0,%1,0,%m2,%M2 + #" + [(set_attr "length" "4,4,4,8")]) + (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") (and:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7578,14 +7662,14 @@ build_mask64_2_operands (operands[2], &operands[4]); }) -(define_insn "*anddi3_internal2" +(define_insn "*anddi3_internal2_mc" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] - "TARGET_64BIT" + "TARGET_64BIT && rs6000_gen_cell_microcode" "@ and. %3,%1,%2 rldic%B2. %3,%1,0,%S2 @@ -7602,6 +7686,18 @@ [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare") (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) +(define_insn "*anddi3_internal2_nomc" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y,?y,??y,??y,?y") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") + (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t")) + (const_int 0))) + (clobber (match_scratch:DI 3 "=r,r,r,r,r,r")) + (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))] + "TARGET_64BIT && !rs6000_gen_cell_microcode" + "#" + [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare") + (set_attr "length" "8,8,8,8,8,12")]) + (define_split [(set (match_operand:CC 0 "cc_reg_operand" "") (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7628,7 +7724,7 @@ build_mask64_2_operands (operands[2], &operands[5]); }") -(define_insn "*anddi3_internal3" +(define_insn "*anddi3_internal3_mc" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) @@ -7636,7 +7732,7 @@ (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r") (and:DI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] - "TARGET_64BIT" + "TARGET_64BIT && rs6000_gen_cell_microcode" "@ and. %0,%1,%2 rldic%B2. %0,%1,0,%S2 @@ -7653,8 +7749,20 @@ [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare") (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) +(define_insn "*anddi3_internal3_nomc" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,?y,??y,??y,?y") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") + (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t")) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") + (and:DI (match_dup 1) (match_dup 2))) + (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))] + "TARGET_64BIT && !rs6000_gen_cell_microcode" + "#" + [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare") + (set_attr "length" "8,8,8,8,8,12")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "and64_2_operand" "")) (const_int 0))) @@ -7794,7 +7902,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:DI 4 "boolean_operator" [(match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "gpc_reg_operand" "")]) @@ -7823,7 +7931,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:DI 4 "boolean_operator" [(match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "gpc_reg_operand" "")]) @@ -7894,7 +8002,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:DI 4 "boolean_operator" [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) (match_operand:DI 2 "gpc_reg_operand" "")]) @@ -7923,7 +8031,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:DI 4 "boolean_operator" [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) (match_operand:DI 2 "gpc_reg_operand" "")]) @@ -7960,7 +8068,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:DI 4 "boolean_operator" [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) @@ -7989,7 +8097,7 @@ (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operator:DI 4 "boolean_operator" [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) @@ -8130,7 +8238,7 @@ (set_attr "length" "4,4,8")]) (define_split - [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") (compare:CC (match_operand:P 1 "gpc_reg_operand" "") (const_int 0))) (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))] @@ -9151,7 +9259,10 @@ return \"#\"; } }" - [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")]) + [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*") + (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1)) + (const_string "always") + (const_string "conditional")))]) (define_insn "*movti_ppc64" [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") @@ -9410,7 +9521,8 @@ (match_operand:SI 10 "gpc_reg_operand" "r"))])] "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi7" [(match_parallel 0 "store_multiple_operation" @@ -9431,7 +9543,8 @@ (match_operand:SI 9 "gpc_reg_operand" "r"))])] "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi6" [(match_parallel 0 "store_multiple_operation" @@ -9450,7 +9563,8 @@ (match_operand:SI 8 "gpc_reg_operand" "r"))])] "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi5" [(match_parallel 0 "store_multiple_operation" @@ -9467,7 +9581,8 @@ (match_operand:SI 7 "gpc_reg_operand" "r"))])] "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi4" [(match_parallel 0 "store_multiple_operation" @@ -9482,7 +9597,8 @@ (match_operand:SI 6 "gpc_reg_operand" "r"))])] "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi3" [(match_parallel 0 "store_multiple_operation" @@ -9495,7 +9611,8 @@ (match_operand:SI 5 "gpc_reg_operand" "r"))])] "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi8_power" [(match_parallel 0 "store_multiple_operation" @@ -9518,7 +9635,8 @@ (match_operand:SI 10 "gpc_reg_operand" "r"))])] "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi7_power" [(match_parallel 0 "store_multiple_operation" @@ -9539,7 +9657,8 @@ (match_operand:SI 9 "gpc_reg_operand" "r"))])] "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi6_power" [(match_parallel 0 "store_multiple_operation" @@ -9558,7 +9677,8 @@ (match_operand:SI 8 "gpc_reg_operand" "r"))])] "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi5_power" [(match_parallel 0 "store_multiple_operation" @@ -9575,7 +9695,8 @@ (match_operand:SI 7 "gpc_reg_operand" "r"))])] "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi4_power" [(match_parallel 0 "store_multiple_operation" @@ -9590,7 +9711,8 @@ (match_operand:SI 6 "gpc_reg_operand" "r"))])] "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_insn "*stmsi3_power" [(match_parallel 0 "store_multiple_operation" @@ -9603,7 +9725,8 @@ (match_operand:SI 5 "gpc_reg_operand" "r"))])] "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4" "{stsi|stswi} %2,%1,%O0" - [(set_attr "type" "store_ux")]) + [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always")]) (define_expand "setmemsi" [(parallel [(set (match_operand:BLK 0 "" "") @@ -9685,6 +9808,7 @@ && REGNO (operands[4]) == 5" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) (define_insn "" @@ -9709,6 +9833,7 @@ && REGNO (operands[4]) == 5" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) ;; Move up to 24 bytes at a time. The fixed registers are needed because the @@ -9748,6 +9873,7 @@ && REGNO (operands[4]) == 5" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) (define_insn "" @@ -9769,6 +9895,7 @@ && REGNO (operands[4]) == 5" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill @@ -9804,6 +9931,7 @@ && REGNO (operands[4]) == 5" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) (define_insn "" @@ -9823,6 +9951,7 @@ && REGNO (operands[4]) == 5" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) ;; Move up to 8 bytes at a time. @@ -9847,6 +9976,7 @@ && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) (define_insn "" @@ -9860,6 +9990,7 @@ && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) ;; Move up to 4 bytes at a time. @@ -9884,6 +10015,7 @@ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) (define_insn "" @@ -9897,6 +10029,7 @@ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" [(set_attr "type" "store_ux") + (set_attr "cell_micro" "always") (set_attr "length" "8")]) ;; Define insns that do load or store with update. Some of these we can @@ -9951,7 +10084,7 @@ (match_operand:DI 2 "gpc_reg_operand" "r"))))) (set (match_operand:DI 0 "gpc_reg_operand" "=b") (plus:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && rs6000_gen_cell_microcode" "lwaux %3,%0,%2" [(set_attr "type" "load_ext_ux")]) @@ -9999,7 +10132,7 @@ (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_UPDATE" + "TARGET_UPDATE && rs6000_gen_cell_microcode" "@ lhaux %3,%0,%2 lhau %3,%2(%0)" @@ -12290,7 +12423,7 @@ (set_attr "length" "8,16")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (ashift:SI (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "") @@ -12700,7 +12833,7 @@ (set_attr "length" "8,12")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) @@ -12779,7 +12912,7 @@ (set_attr "length" "8,12")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) @@ -13487,7 +13620,7 @@ (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (geu:P (match_operand:P 1 "gpc_reg_operand" "") (match_operand:P 2 "reg_or_neg_short_operand" "")) @@ -13777,7 +13910,7 @@ (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") (const_int 0)) @@ -13843,7 +13976,7 @@ (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") (const_int 0)) @@ -14631,7 +14764,8 @@ (match_operand:SI 2 "memory_operand" "m"))])] "TARGET_MULTIPLE" "{lm|lmw} %1,%2" - [(set_attr "type" "load_ux")]) + [(set_attr "type" "load_ux") + (set_attr "cell_micro" "always")]) (define_insn "*return_internal_<mode>" [(return)
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