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File s390-tools-sles15sp1-01-cpumf-Add-extended-counter-defintion-files-for-IBM-z.patch of Package s390-tools (Revision dd8f1b8f8ea9a0e6172ac2aa1b32cb32)

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Subject: cpumf: Add extended counter defintion files for IBM z14
From: Hendrik Brueckner <brueckner@linux.ibm.com>

Summary:     cpumf: Add CPU-MF hardware counters for z14
Description: Add hardware counter definitions for IBM z14.
Upstream-ID: 57f18c5f59766832822a74cc029a8d3b60e3ba0f
Problem-ID:  KRN1608

Upstream-Description:

cpumf: Add extended counter defintion files for IBM z14

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
             [brueckner: Prefer plural for counter names]
             Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
             Signed-off-by: Stefan Haberland <sth@linux.vnet.ibm.com>

Signed-off-by: Hendrik Brueckner <brueckner@linux.ibm.com>
---
 cpumf/Makefile                      |    2 
 cpumf/bin/cpumf_helper.in           |    1 
 cpumf/data/cpum-cf-extended-z14.ctr |  303 ++++++++++++++++++++++++++++++++++++
 cpumf/data/cpum-cf-hw-counter.map   |    1 
 4 files changed, 306 insertions(+), 1 deletion(-)

--- a/cpumf/Makefile
+++ b/cpumf/Makefile
@@ -7,7 +7,7 @@ CPUMF_DATADIR = $(TOOLS_DATADIR)/cpumf
 DATA_FILES = cpum-cf-hw-counter.map cpum-cf-generic.ctr \
              cpum-cf-extended-z10.ctr cpum-cf-extended-z196.ctr \
 	     cpum-cf-extended-zEC12.ctr cpum-sf-modes.ctr \
-	     cpum-cf-extended-z13.ctr
+	     cpum-cf-extended-z13.ctr cpum-cf-extended-z14.ctr
 LIB_FILES = bin/cpumf_helper
 USRBIN_SCRIPTS = bin/lscpumf
 USRSBIN_SCRIPTS = bin/chcpumf
--- a/cpumf/bin/cpumf_helper.in
+++ b/cpumf/bin/cpumf_helper.in
@@ -210,6 +210,7 @@ my $system_z_hwtype_map = {
 	2828		=> 'IBM zEnterprise BC12',
 	2964		=> 'IBM z13',
 	2965		=> 'IBM z13s',
+	3906		=> 'IBM z14',
 };
 
 sub get_hardware_type()
--- /dev/null
+++ b/cpumf/data/cpum-cf-extended-z14.ctr
@@ -0,0 +1,303 @@
+# Counter decriptions for the
+#	IBM z14 extended counter and MT-diagnostic counter set
+#
+# Notes for transactional-execution mode symbolic names:
+#	TX .. transactional-execution mode
+#	NC .. nonconstrained
+#	 C .. constrained
+#
+# Undefined counters in the extended counter set:
+#	142
+#	158-161
+#	176-223
+#	227-231
+#	233-242
+#	246-255
+# Undefined counters in the MT-diagnostic counter set:
+#	450-495
+#
+#
+# Extended Counter Set
+# ---------------------------------------------------------------------
+Counter:128	Name:L1D_WRITES_RO_EXCL
+A directory write to the Level-1 Data cache where the line was
+originally in a Read-Only state in the cache but has been updated
+to be in the Exclusive state that allows stores to the cache line
+.
+Counter:129	Name:DTLB2_WRITES
+Description:
+A translation has been written into The Translation Lookaside
+Buffer 2 (TLB2) and the request was made by the data cache
+.
+Counter:130	Name:DTLB2_MISSES
+Description:
+A TLB2 miss is in progress for a request made by the data cache.
+Incremented by one for every TLB2 miss in progress for the Level-1
+Data cache on this cycle
+.
+Counter:131	Name:DTLB2_HPAGE_WRITES
+Description:
+A translation entry was written into the Combined Region and Segment
+Table Entry array in the Level-2 TLB for a one-megabyte page or a
+Last Host Translation was done
+.
+Counter:132	Name:DTLB2_GPAGE_WRITES
+Description:
+A translation entry for a two-gigabyte page was written into the
+Level-2 TLB
+.
+Counter:133	Name:L1D_L2D_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the
+returned cache line was sourced from the Level-2 Data cache
+.
+Counter:134	Name:ITLB2_WRITES
+Description:
+A translation entry has been written into the Translation Lookaside
+Buffer 2 (TLB2) and the request was made by the instruction cache
+.
+Counter:135	Name:ITLB2_MISSES
+Description:
+A TLB2 miss is in progress for a request made by the instruction cache.
+Incremented by one for every TLB2 miss in progress for the Level-1
+Instruction cache in a cycle
+.
+Counter:136	Name:L1I_L2I_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from the Level-2 Instruction cache
+.
+Counter:137	Name:TLB2_PTE_WRITES
+Description:
+A translation entry was written into the Page Table Entry array in the
+Level-2 TLB
+.
+Counter:138	Name:TLB2_CRSTE_WRITES
+Description:
+Translation entries were written into the Combined Region and Segment
+Table Entry array and the Page Table Entry array in the Level-2 TLB
+.
+Counter:139	Name:TLB2_ENGINES_BUSY
+Description:
+The number of Level-2 TLB translation engines busy in a cycle
+.
+Counter:140	Name:TX_C_TEND
+Description:
+A TEND instruction has completed in a constrained transactional-execution
+mode
+.
+Counter:141	Name:TX_NC_TEND
+Description:
+A TEND instruction has completed in a non-constrained
+transactional-execution mode
+.
+Counter:143	Name:L1C_TLB2_MISSES
+Description:
+Increments by one for any cycle where a level-1 cache or level-2 TLB miss
+is in progress
+.
+Counter:144	Name:L1D_ONCHIP_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an On-Chip Level-3 cache without intervention
+.
+Counter:145	Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from On-Chip memory
+.
+Counter:146	Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an On-Chip Level-3 cache with intervention
+.
+Counter:147	Name:L1D_ONCLUSTER_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from On-Cluster Level-3 cache withountervention
+.
+Counter:148	Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an On-Cluster memory
+.
+Counter:149	Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an On-Cluster Level-3 cache with intervention
+.
+Counter:150	Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an Off-Cluster Level-3 cache without
+intervention
+.
+Counter:151	Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from Off-Cluster memory
+.
+Counter:152	Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an Off-Cluster Level-3 cache with intervention
+.
+Counter:153	Name:L1D_OFFDRAWER_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an Off-Drawer Level-3 cache without
+intervention
+.
+Counter:154	Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from Off-Drawer memory
+.
+Counter:155	Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from an Off-Drawer Level-3 cache with intervention
+.
+Counter:156	Name:L1D_ONDRAWER_L4_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from On-Drawer Level-4 cache
+.
+Counter:157	Name:L1D_OFFDRAWER_L4_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from Off-Drawer Level-4 cache
+.
+Counter:158	Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO
+Description:
+A directory write to the Level-1 Data cache directory where the returned
+cache line was sourced from On-Chip L3 but a read-only invalidate was
+done to remove other copies of the cache line
+.
+Counter:162	Name:L1I_ONCHIP_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache ine was sourced from an On-Chip Level-3 cache without
+intervention
+.
+Counter:163	Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache ine was sourced from On-Chip memory
+.
+Counter:164	Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache ine was sourced from an On-Chip Level-3 cache with
+intervention
+.
+Counter:165	Name:L1I_ONCLUSTER_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from an On-Cluster Level-3 cache without
+intervention
+.
+Counter:166	Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from an On-Cluster memory
+.
+Counter:167	Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from On-Cluster Level-3 cache with
+intervention
+.
+Counter:168	Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from an Off-Cluster Level-3 cache without
+intervention
+.
+Counter:169	Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from Off-Cluster memory
+.
+Counter:170	Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from an Off-Cluster Level-3 cache with
+intervention
+.
+Counter:171	Name:L1I_OFFDRAWER_L3_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from an Off-Drawer Level-3 cache without
+intervention
+.
+Counter:172	Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from Off-Drawer memory
+.
+Counter:173	Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from an Off-Drawer Level-3 cache with
+intervention
+.
+Counter:174	Name:L1I_ONDRAWER_L4_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from On-Drawer Level-4 cache
+.
+Counter:175	Name:L1I_OFFDRAWER_L4_SOURCED_WRITES
+Description:
+A directory write to the Level-1 Instruction cache directory where the
+returned cache line was sourced from Off-Drawer Level-4 cache
+.
+Counter:224	Name:BCD_DFP_EXECUTION_SLOTS
+Description:
+Count of floating point execution slots used for finished Binary Coded
+Decimal to Decimal Floating Point conversions. Instructions: CDZT,
+CXZT, CZDT, CZXT
+.
+Counter:225	Name:VX_BCD_EXECUTION_SLOTS
+Description:
+Count of floating point execution slots used for finished vector arithmetic
+Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP,
+VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG
+.
+Counter:226	Name:DECIMAL_INSTRUCTIONS
+Description:
+Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED,
+EDMK, MP, SRP, SP, ZAP
+.
+Counter:233	Name:LAST_HOST_TRANSLATIONS
+Description:
+Last Host Translation done
+.
+Counter:243	Name:TX_NC_TABORT
+Description:
+A transaction abort has occurred in a non-constrained
+transactional-execution mode
+.
+Counter:244	Name:TX_C_TABORT_NO_SPECIAL
+Description:
+A transaction abort has occurred in a constrained transactional-execution
+mode and the CPU is not using any special logic to allow the transaction
+to complete
+.
+Counter:245	Name:TX_C_TABORT_SPECIAL
+Description:
+A transaction abort has occurred in a constrained transactional-execution
+mode and the CPU is using special logic to allow the transaction to
+complete
+.
+#
+# MT-diagnostic counter set
+# ---------------------------------------------------------------------
+Counter:448	Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
+Description:
+Cycle count with one thread active
+.
+Counter:449	Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
+Description:
+Cycle count with two threads active
+.
--- a/cpumf/data/cpum-cf-hw-counter.map
+++ b/cpumf/data/cpum-cf-hw-counter.map
@@ -14,4 +14,5 @@
 	2828		=> 'cpum-cf-extended-zEC12.ctr',
 	2964		=> 'cpum-cf-extended-z13.ctr',
 	2965		=> 'cpum-cf-extended-z13.ctr',
+	3906		=> 'cpum-cf-extended-z14.ctr',
 };

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File s390-tools-sles15sp1-01-cpumf-Add-extended-counter-defintion-files-for-IBM-z.patch of Package s390-tools (Revision dd8f1b8f8ea9a0e6172ac2aa1b32cb32)

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