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File u_mesa-9.0-i965-Make-sure-we-do-render-between-two-hiz-flushes.patch of Package Mesa (Revision 8494ace793492f93582b2b84e0ca1461)

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From 1547bb37e97c8d7069d5be4e8b9b0d34ac28f7e1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?St=C3=A9phane=20Marchesin?= <marcheu@chromium.org>
Date: Tue, 17 Apr 2012 18:17:35 -0700
Subject: [PATCH 2/2] i965: Make sure we do render between two hiz flushes

Hiz flushes touch the URB allocation, which doesn't work if you don't
draw in between. This includes on startup where the GPU hasn't been
used and we lockup. To avoid this situation make sure that some
primitives get rendered before every hiz flush.
---
 src/mesa/drivers/dri/i965/brw_context.c |    1 +
 src/mesa/drivers/dri/i965/brw_context.h |    1 +
 src/mesa/drivers/dri/i965/brw_draw.c    |   12 +++++++++---
 3 files changed, 11 insertions(+), 3 deletions(-)

Index: mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.c
===================================================================
--- mesa-9.1.98.01.orig/src/mesa/drivers/dri/i965/brw_context.c
+++ mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.c
@@ -410,6 +410,7 @@ brwCreateContext(int api,
 	 brw->urb.max_gs_entries = 256;
       }
       brw->urb.gen6_gs_previously_active = false;
+      brw->urb.prims_since_last_flush = 0;
    } else if (brw->gen == 5) {
       brw->urb.size = 1024;
       brw->max_vs_threads = 72;
Index: mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.h
===================================================================
--- mesa-9.1.98.01.orig/src/mesa/drivers/dri/i965/brw_context.h
+++ mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_context.h
@@ -1000,6 +1000,7 @@ struct brw_context
        * URB space for the GS.
        */
       bool gen6_gs_previously_active;
+      int prims_since_last_flush;
    } urb;
 
    
Index: mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_draw.c
===================================================================
--- mesa-9.1.98.01.orig/src/mesa/drivers/dri/i965/brw_draw.c
+++ mesa-9.1.98.01/src/mesa/drivers/dri/i965/brw_draw.c
@@ -294,10 +294,14 @@ static void brw_merge_inputs( struct brw
  * Resolve the depth buffer's HiZ buffer and resolve the depth buffer of each
  * enabled depth texture.
  *
+ * We don't resolve the depth buffer's HiZ if no primitives have been drawn
+ * since the last flush. This avoids a case where we lockup the GPU on boot
+ * when this is the first thing we do.
+ *
  * (In the future, this will also perform MSAA resolves).
  */
 static void
-brw_predraw_resolve_buffers(struct brw_context *brw)
+brw_predraw_resolve_buffers(struct brw_context *brw, int nr_prims)
 {
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *depth_irb;
@@ -305,9 +309,11 @@ brw_predraw_resolve_buffers(struct brw_c
 
    /* Resolve the depth buffer's HiZ buffer. */
    depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
-   if (depth_irb)
+   if (depth_irb && brw->urb.prims_since_last_flush > 0 )
       intel_renderbuffer_resolve_hiz(brw, depth_irb);
 
+   brw->urb.prims_since_last_flush = nr_prims;
+
    /* Resolve depth buffer of each enabled depth texture, and color buffer of
     * each fast-clear-enabled color texture.
     */
@@ -390,7 +396,7 @@ static bool brw_try_draw_prims( struct g
     * and finalizing textures but before setting up any hardware state for
     * this draw call.
     */
-   brw_predraw_resolve_buffers(brw);
+   brw_predraw_resolve_buffers(brw, nr_prims);
 
    /* Bind all inputs, derive varying and size information:
     */

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