File nvl436041.patch of Package libgcj43

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File nvl436041.patch of Package libgcj43

2008-10-15  Andreas Krebbel  <krebbel1@de.ibm.com>

* config/s390/s390.h: (TARGET_DFP): This requires TARGET_HARD_FLOAT.
	* config/s390/s390.md: Replace "TARGET_HARD_FLOAT &&
	TARGET_(HARD_)DFP" with only TARGET_(HARD_)DFP since this
	already implies hard float.  Also fix several insn condition
	with TARGET_DFP which shall require TARGET_HARD_DFP instead.

Index: gcc/config/s390/s390.h
===================================================================
--- gcc/config/s390/s390.h.orig	2009-11-20 13:51:33.000000000 +0100
+++ gcc/config/s390/s390.h	2009-11-20 13:52:07.000000000 +0100
@@ -89,7 +89,7 @@ extern enum processor_flags s390_arch_fl
 #define TARGET_EXTIMM \
        (TARGET_ZARCH && TARGET_CPU_EXTIMM)
 #define TARGET_DFP \
-       (TARGET_ZARCH && TARGET_CPU_DFP)
+       (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
 #define TARGET_Z10 \
        (TARGET_ZARCH && TARGET_CPU_Z10)
 
Index: gcc/config/s390/s390.md
===================================================================
--- gcc/config/s390/s390.md.orig	2009-11-20 13:51:41.000000000 +0100
+++ gcc/config/s390/s390.md	2009-11-20 13:52:07.000000000 +0100
@@ -3817,7 +3817,7 @@
 	  (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
      (clobber (match_scratch:TD 2 "=f"))])]
 
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
@@ -3849,7 +3849,7 @@
 (define_expand "fixuns_trunctddi2"
   [(set (match_operand:DI 0 "register_operand" "")
         (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
@@ -3938,7 +3938,7 @@
 (define_expand "fix_trunc<mode>di2"
   [(set (match_operand:DI 0 "register_operand" "")
         (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_64BIT && TARGET_HARD_DFP"
 {
   operands[1] = force_reg (<MODE>mode, operands[1]);
   emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
@@ -3952,7 +3952,7 @@
         (fix:DI (match_operand:DFP 1 "register_operand" "f")))
    (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_64BIT && TARGET_HARD_DFP"
   "cg<DFP:xde>tr\t%0,%h2,%1"
   [(set_attr "op_type" "RRF")
    (set_attr "type"    "ftoidfp")])
@@ -4028,7 +4028,7 @@
   [(set (match_operand:DD 0 "register_operand" "=f")
 	(float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
    (clobber (match_scratch:TD 2 "=f"))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
   [(set_attr "length"  "6")
    (set_attr "type"    "ftruncdd")])
@@ -4036,7 +4036,7 @@
 (define_insn "truncddsd2"
   [(set (match_operand:SD 0 "register_operand" "=f")
 	(float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "ledtr\t%0,0,%1,0"
   [(set_attr "op_type" "RRF")
    (set_attr "type"    "ftruncsd")])
@@ -4064,7 +4064,7 @@
 (define_insn "extendddtd2"
   [(set (match_operand:TD 0 "register_operand" "=f")
 	(float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "lxdtr\t%0,%1,0"
   [(set_attr "op_type" "RRF")
    (set_attr "type"    "fsimptf")])
@@ -4072,7 +4072,7 @@
 (define_insn "extendsddd2"
   [(set (match_operand:DD 0 "register_operand" "=f")
 	(float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
+  "TARGET_HARD_DFP"
   "ldetr\t%0,%1,0"
   [(set_attr "op_type" "RRF")
    (set_attr "type"    "fsimptf")])
@@ -4085,7 +4085,7 @@
         (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
@@ -4093,7 +4093,7 @@
         (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
@@ -4106,7 +4106,7 @@
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
         (reg:DFP_ALL FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -4127,7 +4127,7 @@
      (use (reg:SI GPR0_REGNUM))
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -4147,14 +4147,14 @@
   [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
   [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
    (use (reg:SI GPR0_REGNUM))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_HARD_DFP"
   "pfpo")
 
 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
@@ -4167,7 +4167,7 @@
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
         (reg:DFP_ALL FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -4188,7 +4188,7 @@
      (use (reg:SI GPR0_REGNUM))
      (clobber (reg:CC CC_REGNUM))])
    (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_DFP
+  "TARGET_HARD_DFP
    && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
 {
   HOST_WIDE_INT flags;
@@ -6774,7 +6774,7 @@
 (define_insn "*neg<mode>2_nocc"
   [(set (match_operand:FP 0 "register_operand"         "=f")
         (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "lcdfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6890,7 +6890,7 @@
 (define_insn "*abs<mode>2_nocc"
   [(set (match_operand:FP 0 "register_operand"         "=f")
         (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "lpdfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6999,7 +6999,7 @@
 (define_insn "*negabs<mode>2_nocc"
   [(set (match_operand:FP 0 "register_operand"                  "=f")
         (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "lndfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -7024,7 +7024,7 @@
 	(unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
 		    (match_operand:FP 2 "register_operand" "f")]
 		    UNSPEC_COPYSIGN))]
-  "TARGET_HARD_FLOAT && TARGET_DFP"
+  "TARGET_DFP"
   "cpsdr\t%0,%2,%1"
   [(set_attr "op_type"  "RRF")
    (set_attr "type"     "fsimp<mode>")])

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