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openSUSE:Evergreen:11.1:Test
xorg-x11-driver-video
xf86-video-mga-1.4.9_36ae47b.diff
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File xf86-video-mga-1.4.9_36ae47b.diff of Package xorg-x11-driver-video
diff --git a/README b/README new file mode 100644 index 0000000..b31b3c6 --- /dev/null +++ b/README @@ -0,0 +1,20 @@ +xf86-video-mga - Matrox video driver for the Xorg X server + +Please submit bugs & patches to the Xorg bugzilla: + + https://bugs.freedesktop.org/enter_bug.cgi?product=xorg + +All questions regarding this software should be directed at the +Xorg mailing list: + + http://lists.freedesktop.org/mailman/listinfo/xorg + +The master development code repository can be found at: + + git://anongit.freedesktop.org/git/xorg/driver/xf86-video-mga + + http://cgit.freedesktop.org/xorg/driver/xf86-video-mga + +For more information on the git code manager, see: + + http://wiki.x.org/wiki/GitPage diff --git a/man/mga.man b/man/mga.man index 64c54fd..3a7a9f8 100644 --- a/man/mga.man +++ b/man/mga.man @@ -170,7 +170,7 @@ option is primarily intended for testing purposes, but it could also be used on systems with a buggy or poorly function AGP implementation. Default: off. .SH "SEE ALSO" -__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) .SH AUTHORS Authors include: Radoslaw Kapitan, Mark Vojkovich, and also David Dawes, Guy Desbief, Dirk Hohndel, Doug Merritt, Andrew E. Mileski, Andrew van der Stock, diff --git a/src/mga_dacG.c b/src/mga_dacG.c index af5d1d9..88a12cb 100644 --- a/src/mga_dacG.c +++ b/src/mga_dacG.c @@ -82,7 +82,7 @@ MGAG200IPComputePLLParam(ScrnInfoPtr pScrn, long lFo, int *M, int *N, int *P) ulTestNEnd = 32; ulTestMStart = 1; ulTestMEnd = 32; - } else if (pMga->is_G200EV) { + } else { /* pMga->is_G200EV */ ulVCOMax = 550000; ulVCOMin = 150000; ulPLLFreqRef = 50000; @@ -91,15 +91,6 @@ MGAG200IPComputePLLParam(ScrnInfoPtr pScrn, long lFo, int *M, int *N, int *P) ulTestNEnd = 256; ulTestMStart = 1; ulTestMEnd = 16; - } else if (pMga->is_G200WB) { - ulVCOMax = 680000; - ulVCOMin = 150000; - ulPLLFreqRef = 48000; - ulTestPStart = 8; - ulTestNStart = 1; - ulTestNEnd = 512; - ulTestMStart = 3; - ulTestMEnd = 25; } ulFDelta = 0xFFFFFFFF; @@ -121,13 +112,69 @@ MGAG200IPComputePLLParam(ScrnInfoPtr pScrn, long lFo, int *M, int *N, int *P) if (ulFTmpDelta < ulFDelta) { ulFDelta = ulFTmpDelta; - if (pMga->is_G200WB) { - *M = (ulTestM - 1) | (((ulTestN -1) >> 1) & 0x80); - } else { - *M = ulTestM - 1; - } - *N = ulTestN - 1; - *P = ulTestP - 1; + *M = ulTestM - 1; + *N = (CARD8)(ulTestN - 1); + *P = (CARD8)(ulTestP - 1); + } + } + } + } +#if DEBUG + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "lFo=%ld n=0x%x m=0x%x p=0x%x \n", + lFo, *N, *M, *P ); +#endif +} + +static void +MGAG200WBComputePLLParam(ScrnInfoPtr pScrn, long lFo, int *M, int *N, int *P) +{ + unsigned int ulComputedFo; + unsigned int ulFDelta; + unsigned int ulFPermitedDelta; + unsigned int ulFTmpDelta; + unsigned int ulVCOMax, ulVCOMin; + unsigned int ulTestP; + unsigned int ulTestM; + unsigned int ulTestN; + unsigned int ulPLLFreqRef; + unsigned int ulTestPStart; + unsigned int ulTestNStart; + unsigned int ulTestNEnd; + unsigned int ulTestMStart; + unsigned int ulTestMEnd; + + ulVCOMax = 550000; + ulVCOMin = 150000; + ulPLLFreqRef = 48000; + ulTestPStart = 1; + ulTestNStart = 1; + ulTestNEnd = 150; + ulTestMStart = 1; + ulTestMEnd = 16; + + ulFDelta = 0xFFFFFFFF; + /* Permited delta is 0.5% as VESA Specification */ + ulFPermitedDelta = lFo * 5 / 1000; + + /* Then we need to minimize the M while staying within 0.5% */ + for (ulTestP = ulTestPStart; ulTestP < 9; ulTestP++) { + if ((lFo * ulTestP) > ulVCOMax) continue; + if ((lFo * ulTestP) < ulVCOMin) continue; + + for (ulTestM = ulTestMStart; ulTestM <= ulTestMEnd; ulTestM++) { + for (ulTestN = ulTestNStart; ulTestN <= ulTestNEnd; ulTestN++) { + ulComputedFo = (ulPLLFreqRef * ulTestN) / (ulTestM * ulTestP); + if (ulComputedFo > lFo) + ulFTmpDelta = ulComputedFo - lFo; + else + ulFTmpDelta = lFo - ulComputedFo; + + if (ulFTmpDelta < ulFDelta) { + ulFDelta = ulFTmpDelta; + *M = (CARD8)(ulTestM - 1) | (CARD8)(((ulTestN -1) >> 1) & 0x80); + *N = (CARD8)(ulTestN - 1); + *P = (CARD8)(ulTestP - 1); } } } @@ -144,12 +191,7 @@ MGAG200EVPIXPLLSET(ScrnInfoPtr pScrn, MGARegPtr mgaReg) { MGAPtr pMga = MGAPTR(pScrn); - unsigned long ulFallBackCounter; unsigned char ucTempByte, ucPixCtrl; - unsigned char ucM; - unsigned char ucN; - unsigned char ucP; - unsigned char ucS; // Set pixclkdis to 1 ucPixCtrl = inMGAdac(MGA1064_PIX_CLK_CTL); @@ -157,9 +199,9 @@ MGAG200EVPIXPLLSET(ScrnInfoPtr pScrn, MGARegPtr mgaReg) outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); // Select PLL Set C - ucTempByte = INREG8(MGAREG_MISC_READ); + ucTempByte = INREG8(MGAREG_MEM_MISC_READ); ucTempByte |= 0x3<<2; //select MGA pixel clock - OUTREG8(MGAREG_MISC_WRITE, ucTempByte); + OUTREG8(MGAREG_MEM_MISC_WRITE, ucTempByte); // Set pixlock to 0 ucTempByte = inMGAdac(MGA1064_PIX_PLL_STAT); @@ -214,99 +256,133 @@ MGAG200WBPIXPLLSET(ScrnInfoPtr pScrn, MGARegPtr mgaReg) { MGAPtr pMga = MGAPTR(pScrn); - unsigned long ulFallBackCounter; - unsigned char ucTempByte, ucPixCtrl; - unsigned char ucM; - unsigned char ucN; - unsigned char ucP; - unsigned char ucS; + unsigned long ulLoopCount, ulLockCheckIterations = 0, ulTempCount, ulVCount; + unsigned char ucTempByte, ucPixCtrl, ucPLLLocked = FALSE; - // Set pixclkdis to 1 - ucPixCtrl = inMGAdac(MGA1064_PIX_CLK_CTL); - ucPixCtrl |= MGA1064_PIX_CLK_CTL_CLK_DIS; - outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); + while(ulLockCheckIterations <= 32 && ucPLLLocked == FALSE) + { + if(ulLockCheckIterations > 0) + { + OUTREG8(MGAREG_CRTCEXT_INDEX, 0x1E); + ucTempByte = INREG8(MGAREG_CRTCEXT_DATA); + if(ucTempByte < 0xFF) + { + OUTREG8(MGAREG_CRTCEXT_DATA, ucTempByte+1); + } + } - ucTempByte = inMGAdac(MGA1064_REMHEADCTL); - ucTempByte |= MGA1064_REMHEADCTL_CLKDIS; - outMGAdac(MGA1064_REMHEADCTL, ucTempByte); + // Set pixclkdis to 1 + ucPixCtrl = inMGAdac(MGA1064_PIX_CLK_CTL); + ucPixCtrl |= MGA1064_PIX_CLK_CTL_CLK_DIS; + outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); - // Select PLL Set C - ucTempByte = INREG8(MGAREG_MISC_READ); - ucTempByte |= 0x3<<2; //select MGA pixel clock - OUTREG8(MGAREG_MISC_WRITE, ucTempByte); + ucTempByte = inMGAdac(MGA1064_REMHEADCTL); + ucTempByte |= MGA1064_REMHEADCTL_CLKDIS; + outMGAdac(MGA1064_REMHEADCTL, ucTempByte); - // Set pixlock to 0 - ucTempByte = inMGAdac(MGA1064_PIX_PLL_STAT); - outMGAdac(MGA1064_PIX_PLL_STAT, ucTempByte & ~0x40); + // Select PLL Set C + ucTempByte = INREG8(MGAREG_MEM_MISC_READ); + ucTempByte |= 0x3<<2; //select MGA pixel clock + OUTREG8(MGAREG_MEM_MISC_WRITE, ucTempByte); - ucPixCtrl |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; - outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); + // Set pixlock to 0 + ucTempByte = inMGAdac(MGA1064_PIX_PLL_STAT); + outMGAdac(MGA1064_PIX_PLL_STAT, ucTempByte & ~0x40); - // Wait 500 us - usleep(500); + ucPixCtrl |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; + outMGAdac(MGA1064_PIX_CLK_CTL, ucPixCtrl); - // Reset the PLL - // When we are varying the output frequency by more than - // 10%, we must reset the PLL. However to be prudent, we - // will reset it each time that we are changing it. - ucTempByte = inMGAdac(MGA1064_VREF_CTL); - ucTempByte &= ~0x04; - outMGAdac(MGA1064_VREF_CTL, ucTempByte ); + // Wait 500 us + usleep(500); - // Wait 50 us - usleep(50); + // Reset the PLL + // When we are varying the output frequency by more than + // 10%, we must reset the PLL. However to be prudent, we + // will reset it each time that we are changing it. + ucTempByte = inMGAdac(MGA1064_VREF_CTL); + ucTempByte &= ~0x04; + outMGAdac(MGA1064_VREF_CTL, ucTempByte ); - // Program the Pixel PLL Register - outMGAdac(MGA1064_WB_PIX_PLLC_M, mgaReg->PllM); - outMGAdac(MGA1064_WB_PIX_PLLC_N, mgaReg->PllN); - outMGAdac(MGA1064_WB_PIX_PLLC_P, mgaReg->PllP); + // Wait 50 us + usleep(50); - // Wait 50 us - usleep(50); + // Program the Pixel PLL Register + outMGAdac(MGA1064_WB_PIX_PLLC_M, mgaReg->PllM); + outMGAdac(MGA1064_WB_PIX_PLLC_N, mgaReg->PllN); + outMGAdac(MGA1064_WB_PIX_PLLC_P, mgaReg->PllP); - ucTempByte = INREG8(MGAREG_MISC_READ); - OUTREG8(MGAREG_MISC_WRITE, ucTempByte & ~0x08); + // Wait 50 us + usleep(50); - // Wait 50 us - usleep(50); + ucTempByte = INREG8(MGAREG_MEM_MISC_READ); + OUTREG8(MGAREG_MEM_MISC_WRITE, ucTempByte); - OUTREG8(MGAREG_MISC_WRITE, ucTempByte); + // Wait 50 us + usleep(50); - // Wait 500 us - usleep(500); + OUTREG8(MGAREG_MEM_MISC_WRITE, ucTempByte); - // Turning the PLL on - ucTempByte = inMGAdac(MGA1064_VREF_CTL); - ucTempByte |= 0x04; - outMGAdac(MGA1064_VREF_CTL, ucTempByte ); + // Wait 500 us + usleep(500); - // Wait 500 us - usleep(500); + // Turning the PLL on + ucTempByte = inMGAdac(MGA1064_VREF_CTL); + ucTempByte |= 0x04; + outMGAdac(MGA1064_VREF_CTL, ucTempByte ); - // Select the pixel PLL by setting pixclksel to 1 - ucTempByte = inMGAdac(MGA1064_PIX_CLK_CTL); - ucTempByte &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; - ucTempByte |= MGA1064_PIX_CLK_CTL_SEL_PLL; - outMGAdac(MGA1064_PIX_CLK_CTL, ucTempByte); + // Wait 500 us + usleep(500); - ucTempByte = inMGAdac(MGA1064_REMHEADCTL); - ucTempByte &= ~MGA1064_REMHEADCTL_CLKSL_MSK; - ucTempByte |= MGA1064_REMHEADCTL_CLKSL_PLL; - outMGAdac(MGA1064_REMHEADCTL, ucTempByte); + // Select the pixel PLL by setting pixclksel to 1 + ucTempByte = inMGAdac(MGA1064_PIX_CLK_CTL); + ucTempByte &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; + ucTempByte |= MGA1064_PIX_CLK_CTL_SEL_PLL; + outMGAdac(MGA1064_PIX_CLK_CTL, ucTempByte); - // Set pixlock to 1 - ucTempByte = inMGAdac(MGA1064_PIX_PLL_STAT); - outMGAdac(MGA1064_PIX_PLL_STAT, ucTempByte | 0x40); + ucTempByte = inMGAdac(MGA1064_REMHEADCTL); + ucTempByte &= ~MGA1064_REMHEADCTL_CLKSL_MSK; + ucTempByte |= MGA1064_REMHEADCTL_CLKSL_PLL; + outMGAdac(MGA1064_REMHEADCTL, ucTempByte); - // Reset dotclock rate bit. - OUTREG8(MGAREG_SEQ_INDEX, 1); - ucTempByte = INREG8(MGAREG_SEQ_DATA); - OUTREG8(MGAREG_SEQ_DATA, ucTempByte & ~0x8); + // Set pixlock to 1 + ucTempByte = inMGAdac(MGA1064_PIX_PLL_STAT); + outMGAdac(MGA1064_PIX_PLL_STAT, ucTempByte | 0x40); - // Set pixclkdis to 0 - ucTempByte = inMGAdac(MGA1064_PIX_CLK_CTL); - ucTempByte &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; - outMGAdac(MGA1064_PIX_CLK_CTL, ucTempByte); + // Reset dotclock rate bit. + OUTREG8(MGAREG_SEQ_INDEX, 1); + ucTempByte = INREG8(MGAREG_SEQ_DATA); + OUTREG8(MGAREG_SEQ_DATA, ucTempByte & ~0x8); + + // Set pixclkdis to 0 + ucTempByte = inMGAdac(MGA1064_PIX_CLK_CTL); + ucTempByte &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; + outMGAdac(MGA1064_PIX_CLK_CTL, ucTempByte); + + // Poll VCount. If it increments twice inside 150us, + // we assume that the PLL has locked. + ulLoopCount = 0; + ulVCount = INREG(MGAREG_VCOUNT); + + while(ulLoopCount < 30 && ucPLLLocked == FALSE) + { + ulTempCount = INREG(MGAREG_VCOUNT); + + if(ulTempCount < ulVCount) + { + ulVCount = 0; + } + if ((ucTempByte - ulVCount) > 2) + { + ucPLLLocked = TRUE; + } + else + { + usleep(5); + } + ulLoopCount++; + } + ulLockCheckIterations++; + } // Set remclkdis to 0 ucTempByte = inMGAdac(MGA1064_REMHEADCTL); @@ -537,12 +613,19 @@ MGAGSetPCLK( ScrnInfoPtr pScrn, long f_out ) pReg->DacRegs[ MGA1064_PIX_PLLC_M ] = m; pReg->DacRegs[ MGA1064_PIX_PLLC_N ] = n; pReg->DacRegs[ MGA1064_PIX_PLLC_P ] = p; - } else if (pMga->is_G200EV || pMga->is_G200WB) { + } else if (pMga->is_G200EV) { MGAG200IPComputePLLParam(pScrn, f_out, &m, &n, &p); + pReg->PllM = m; pReg->PllN = n; pReg->PllP = p; - } else { + } else if (pMga->is_G200WB) { + MGAG200WBComputePLLParam(pScrn, f_out, &m, &n, &p); + + pReg->PllM = m; + pReg->PllN = n; + pReg->PllP = p; + } else { /* Do the calculations for m, n, p and s */ MGAGCalcClock( pScrn, f_out, &m, &n, &p, &s ); @@ -1503,9 +1586,17 @@ MGAG_ddc1Read(ScrnInfoPtr pScrn) { MGAPtr pMga = MGAPTR(pScrn); unsigned char val; - + int i2c_index; + + if (pMga->is_G200SE || pMga->is_G200WB || pMga->is_G200EV) + i2c_index = 3; + else + i2c_index = 0; + + const struct mgag_i2c_private *p = & i2c_priv[i2c_index]; + /* Define the SDA as an input */ - outMGAdacmsk(MGA1064_GEN_IO_CTL, ~(DDC_P1_SCL_MASK | DDC_P1_SDA_MASK), 0); + outMGAdacmsk(MGA1064_GEN_IO_CTL, ~(p->scl_mask | p->sda_mask), 0); /* wait for Vsync */ if (pMga->is_G200SE) { @@ -1516,7 +1607,7 @@ MGAG_ddc1Read(ScrnInfoPtr pScrn) } /* Get the result */ - val = (inMGAdac(MGA1064_GEN_IO_DATA) & DDC_P1_SDA_MASK); + val = (inMGAdac(MGA1064_GEN_IO_DATA) & p->sda_mask); return val; } @@ -1592,7 +1683,6 @@ Bool MGAG_i2cInit(ScrnInfoPtr pScrn) { MGAPtr pMga = MGAPTR(pScrn); - I2CBusPtr I2CPtr; if (pMga->SecondCrtc == FALSE) { int i2c_index; diff --git a/src/mga_dh.c b/src/mga_dh.c index 6ba2945..d9c0d34 100644 --- a/src/mga_dh.c +++ b/src/mga_dh.c @@ -251,9 +251,9 @@ void MGAEnableSecondOutPut(ScrnInfoPtr pScrn, xMODEINFO *pModeInfo) /* We don't use MISC synch pol, must be 0*/ - ucByte = inMGAdreg( MGAREG_MISC_READ); + ucByte = INREG8( MGAREG_MEM_MISC_READ); - OUTREG8(MGAREG_MISC_WRITE, (CARD8)(ucByte & ~(HSYNCPOL| VSYNCPOL) )); + OUTREG8(MGAREG_MEM_MISC_WRITE, (CARD8)(ucByte & ~(HSYNCPOL| VSYNCPOL) )); diff --git a/src/mga_driver.c b/src/mga_driver.c index 6f55e63..b363437 100644 --- a/src/mga_driver.c +++ b/src/mga_driver.c @@ -427,8 +427,8 @@ static SymTabRec MGAChipsets[] = { { PCI_CHIP_MGAG200_PCI, "mgag200 PCI" }, { PCI_CHIP_MGAG200_SE_A_PCI, "mgag200 SE A PCI" }, { PCI_CHIP_MGAG200_SE_B_PCI, "mgag200 SE B PCI" }, - { PCI_CHIP_MGAG200_EV_PCI, "mgag200 Maxim" }, - { PCI_CHIP_MGAG200_WINBOND_PCI, "mgag200 Winbond" }, + { PCI_CHIP_MGAG200_EV_PCI, "mgag200 EV Maxim" }, + { PCI_CHIP_MGAG200_WINBOND_PCI, "mgag200 eW Nuvoton" }, { PCI_CHIP_MGAG400, "mgag400" }, { PCI_CHIP_MGAG550, "mgag550" }, {-1, NULL } @@ -2492,6 +2492,9 @@ MGAPreInit(ScrnInfoPtr pScrn, int flags) /* Set the min pixel clock */ pMga->MinClock = 17750; + if (pMga->is_G200WB){ + pMga->MinClock = 18750; + } xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %d MHz\n", pMga->MinClock / 1000); /* @@ -4505,11 +4508,13 @@ MGAValidMode(int scrnIndex, DisplayModePtr mode, Bool verbose, int flags) xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 256) return MODE_BANDWIDTH; } else if (pMga->is_G200WB){ + if (mode->Flags & V_DBLSCAN) + return MODE_NO_DBLESCAN; if (pMga->KVM && mode->HDisplay > 1280) return MODE_VIRTUAL_X; if (pMga->KVM && mode->VDisplay > 1024) return MODE_VIRTUAL_Y; - if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 315) + if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 318.77) return MODE_BANDWIDTH; } else if (pMga->is_G200EV && (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 327)) { diff --git a/src/mga_exa.c b/src/mga_exa.c index 9321452..f292327 100644 --- a/src/mga_exa.c +++ b/src/mga_exa.c @@ -332,6 +332,11 @@ mgaCheckSourceTexture(int tmu, PicturePtr pPict) return FALSE; } + if (pPict->repeatType != RepeatNormal) { + DEBUG_MSG(("Unsupported repeat type %d\n", pPict->repeatType)); + return FALSE; + } + if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0)) { DEBUG_MSG(("NPOT repeat unsupported (%dx%d)\n", w, h)); return FALSE; diff --git a/src/mga_storm.c b/src/mga_storm.c index aa6ad82..0d04c63 100644 --- a/src/mga_storm.c +++ b/src/mga_storm.c @@ -1138,6 +1138,20 @@ void MGAStormEngineInit( ScrnInfoPtr pScrn ) break; } + if (pMga->is_G200WB) + { + CARD32 dwgctl = MGADWG_RSTR | 0x00060000 | MGADWG_SHIFTZERO | + MGADWG_BITBLT | MGADWG_BFCOL; + WAITFIFO(7); + OUTREG(MGAREG_DWGCTL, dwgctl); + OUTREG(MGAREG_SGN, 0); + OUTREG(MGAREG_AR5, 1); + OUTREG(MGAREG_AR0, 1); + OUTREG(MGAREG_AR3, 0); + OUTREG(MGAREG_FXBNDRY, (1 << 16) | (1 & 0xffff)); + OUTREG(MGAREG_YDSTLEN + MGAREG_EXEC, (1 << 16) | 1); + } + xf86SetLastScrnFlag(pScrn->entityList[0], pScrn->scrnIndex); }
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