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libgcj43
z10-sched-fixes1
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File z10-sched-fixes1 of Package libgcj43
Index: gcc/config/s390/s390.md =================================================================== --- gcc/config/s390/s390.md.orig 2009-11-20 13:52:24.000000000 +0100 +++ gcc/config/s390/s390.md 2009-11-20 13:52:26.000000000 +0100 @@ -555,7 +555,8 @@ "@ tmh\t%0,%i1 tml\t%0,%i1" - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*tm<mode>_full" [(set (reg CC_REGNUM) @@ -563,7 +564,8 @@ (match_operand:HQI 1 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" "tml\t%0,<max_uint>" - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z10prop" "z10_super")]) ; @@ -601,7 +603,7 @@ lt<g>r\t%2,%0 lt<g>\t%2,%0" [(set_attr "op_type" "RR<E>,RXY") - (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ]) + (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_cconly_extimm" @@ -614,7 +616,7 @@ lt<g>r\t%0,%0 lt<g>\t%2,%0" [(set_attr "op_type" "RR<E>,RXY") - (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")]) + (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) (define_insn "*tstdi" [(set (reg CC_REGNUM) @@ -712,7 +714,7 @@ cliy\t%S0,0 tml\t%0,255" [(set_attr "op_type" "SI,SIY,RI") - (set_attr "z10prop" "z10_super,z10_super,*")]) + (set_attr "z10prop" "z10_super,z10_super,z10_super")]) (define_insn "*tst<mode>" [(set (reg CC_REGNUM) @@ -853,7 +855,8 @@ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" "clhrl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super")]) ; clhrl, clghrl (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" @@ -1524,7 +1527,7 @@ "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl") - (set_attr "z10prop" "z10_super_A1")]) + (set_attr "z10prop" "z10_fwd_A1")]) (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" @@ -1590,7 +1593,7 @@ z10_fr_E1, z10_fwd_A3, z10_fwd_A3, - z10_super, + z10_rec, z10_rec, *, *, @@ -1625,7 +1628,7 @@ (set_attr "z10prop" "z10_fwd_A1, z10_fr_E1, z10_fwd_A3, - z10_super, + z10_rec, *, *, *, @@ -1763,7 +1766,7 @@ z10_super_E1, z10_super_E1, z10_super_E1, - z10_super, + z10_rec, z10_rec, z10_rec, z10_super")]) @@ -1819,7 +1822,7 @@ z10_fwd_A1, z10_super_E1, z10_super_E1, - z10_super, + z10_rec, z10_rec, z10_super, z10_super")]) @@ -1846,7 +1849,7 @@ ic\t%0,%1 icy\t%0,%1" [(set_attr "op_type" "RX,RXY") - (set_attr "z10prop" "z10_super_E1,z10_super")]) + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; ; movstricthi instruction pattern(s). @@ -2164,7 +2167,7 @@ z10_fr_E1, z10_fwd_A3, z10_fwd_A3, - z10_super, + z10_rec, z10_rec")]) ; @@ -2185,7 +2188,7 @@ ly\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") (set_attr "type" "lr,*,*,store,store,load,load") - (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")]) + (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) ; ; Block move (MVC) patterns. @@ -3150,7 +3153,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "icmh\t%0,%2,%S1" - [(set_attr "op_type" "RSY")]) + [(set_attr "op_type" "RSY") + (set_attr "z10prop" "z10_super")]) (define_insn "*sethighpartdi_31" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3693,7 +3697,7 @@ [(set_attr "op_type" "RXY,RRE,RIL") (set_attr "type" "*,*,larl") (set_attr "cpu_facility" "*,*,z10") - (set_attr "z10prop" "z10_fwd_A3")]) + (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" @@ -6627,7 +6631,8 @@ (neg:DI (sign_extend:DI (match_dup 1))))] "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6635,7 +6640,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lcgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) ; lcr, lcgr (define_insn "*neg<mode>2_cc" @@ -6771,7 +6777,8 @@ (abs:DI (sign_extend:DI (match_dup 1))))] "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lpgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) (define_insn "*absdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6779,7 +6786,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lpgfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) ; lpr, lpgr (define_insn "*abs<mode>2_cc" @@ -6887,7 +6895,8 @@ (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) (define_insn "*negabsdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6896,7 +6905,8 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lngfr\t%0,%1" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_c")]) ; lnr, lngr (define_insn "*negabs<mode>2_cc" @@ -7513,7 +7523,7 @@ c<g>it%C0\t%1,%h2" [(set_attr "op_type" "RRF,RIE") (set_attr "type" "branch") - (set_attr "z10prop" "z10_c,*")]) + (set_attr "z10prop" "z10_super_c,z10_super")]) ; clrt, clgrt, clfit, clgit (define_insn "*cmp_and_trap_unsigned_int<mode>" @@ -7527,7 +7537,7 @@ cl<gf>it%C0\t%1,%x2" [(set_attr "op_type" "RRF,RIE") (set_attr "type" "branch") - (set_attr "z10prop" "z10_c,*")]) + (set_attr "z10prop" "z10_super_c,z10_super")]) ;; ;;- Loop instructions. @@ -7591,7 +7601,7 @@ [(set_attr "op_type" "RI") ; Strictly speaking, the z10 properties are valid for brct only, however, it does not ; hurt us in the (rare) case of ahi. - (set_attr "z10prop" "z10_super") + (set_attr "z10prop" "z10_super_E1") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) @@ -7633,7 +7643,7 @@ [(set_attr "op_type" "RI") ; Strictly speaking, the z10 properties are valid for brct only, however, it does not ; hurt us in the (rare) case of ahi. - (set_attr "z10prop" "z10_super") + (set_attr "z10prop" "z10_super_E1") (set_attr "type" "branch") (set (attr "length") (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) @@ -7664,7 +7674,8 @@ (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") - (set_attr "atype" "agen")]) + (set_attr "atype" "agen") + (set_attr "z10prop" "z10_cobra")]) (define_insn_and_split "doloop_di" [(set (pc) @@ -7702,7 +7713,7 @@ [(set_attr "op_type" "RI") ; Strictly speaking, the z10 properties are valid for brct only, however, it does not ; hurt us in the (rare) case of ahi. - (set_attr "z10prop" "z10_super") + (set_attr "z10prop" "z10_super_E1") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) @@ -7769,8 +7780,7 @@ (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") - (set_attr "atype" "agen") - (set_attr "z10prop" "z10_super")]) + (set_attr "atype" "agen")]) ; ; casesi instruction pattern(s). @@ -8464,7 +8474,8 @@ [(const_int 0)] "" "lr\t0,0" - [(set_attr "op_type" "RR")]) + [(set_attr "op_type" "RR") + (set_attr "z10prop" "z10_fr_E1")]) ; @@ -8526,7 +8537,7 @@ "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl") - (set_attr "z10prop" "z10_super_A1")]) + (set_attr "z10prop" "z10_fwd_A1")]) (define_insn "main_pool" [(set (match_operand 0 "register_operand" "=a") @@ -8554,7 +8565,7 @@ "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl") - (set_attr "z10prop" "z10_super_A1")]) + (set_attr "z10prop" "z10_fwd_A1")]) (define_insn "pool" [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
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