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File ovmf-Revert-MdePkg-Remove-the-macro-definitions-regarding.patch of Package ovmf (Revision 01b5fb4dd3d73ab7bd38faf23aa5a66c)

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From 083d51817e057037da5568fcc68f5d6bf449b169 Mon Sep 17 00:00:00 2001
From: "Lee, Chun-Yi" <jlee@suse.com>
Date: Tue, 23 Aug 2022 16:56:21 +0800
Subject: [PATCH 1/5] Revert "MdePkg: Remove the macro definitions regarding
 Opcode."

This reverts commit bbaa00dd01ed0df30e43a5a89fd2b0433d858b73.

Signed-off-by: Lee, Chun-Yi <jlee@suse.com>
---
 MdePkg/Include/Ia32/Nasm.inc | 26 +++++++++++++++++++++++++-
 MdePkg/Include/X64/Nasm.inc  | 26 +++++++++++++++++++++++++-
 2 files changed, 50 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc
index e92c032bd8..c794d9ece3 100644
--- a/MdePkg/Include/Ia32/Nasm.inc
+++ b/MdePkg/Include/Ia32/Nasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;
-; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Abstract:
@@ -9,6 +9,30 @@
 ;
 ;------------------------------------------------------------------------------
 
+%macro SAVEPREVSSP     0
+    DB 0xF3, 0x0F, 0x01, 0xEA
+%endmacro
+
+%macro CLRSSBSY_EAX    0
+    DB 0x67, 0xF3, 0x0F, 0xAE, 0x30
+%endmacro
+
+%macro RSTORSSP_EAX    0
+    DB 0x67, 0xF3, 0x0F, 0x01, 0x28
+%endmacro
+
+%macro SETSSBSY        0
+    DB 0xF3, 0x0F, 0x01, 0xE8
+%endmacro
+
+%macro READSSP_EAX     0
+    DB 0xF3, 0x0F, 0x1E, 0xC8
+%endmacro
+
+%macro INCSSP_EAX      0
+    DB 0xF3, 0x0F, 0xAE, 0xE8
+%endmacro
+
 ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
 ; For example, to define a structure called mytype containing a longword,
 ; a word, a byte and a string of bytes, you might code
diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
index bb77ca6c32..cfb14edc94 100644
--- a/MdePkg/Include/X64/Nasm.inc
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;
-; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Abstract:
@@ -9,6 +9,30 @@
 ;
 ;------------------------------------------------------------------------------
 
+%macro SAVEPREVSSP     0
+    DB 0xF3, 0x0F, 0x01, 0xEA
+%endmacro
+
+%macro CLRSSBSY_RAX    0
+    DB 0xF3, 0x0F, 0xAE, 0x30
+%endmacro
+
+%macro RSTORSSP_RAX    0
+    DB 0xF3, 0x0F, 0x01, 0x28
+%endmacro
+
+%macro SETSSBSY        0
+    DB 0xF3, 0x0F, 0x01, 0xE8
+%endmacro
+
+%macro READSSP_RAX     0
+    DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8
+%endmacro
+
+%macro INCSSP_RAX      0
+    DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
+%endmacro
+
 ;
 ; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.
 ; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753
-- 
2.26.2

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