File ovmf-Revert-UefiCpuPkg-Replace-Opcode-with-the-... of Package ovmf

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File ovmf-Revert-UefiCpuPkg-Replace-Opcode-with-the-correspond.patch of Package ovmf (Revision 6c236bdc86748ea993ac44ca83f161b3)

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From e8146da22109982083c12966ead99eb019a02601 Mon Sep 17 00:00:00 2001
From: "Lee, Chun-Yi" <jlee@suse.com>
Date: Tue, 23 Aug 2022 16:56:29 +0800
Subject: [PATCH 2/5] Revert "UefiCpuPkg: Replace Opcode with the corresponding
 instructions."

This reverts commit 2aa107c0aa2e1375651867c8df1b81ff64b67fce.

Signed-off-by: Lee, Chun-Yi <jlee@suse.com>
---
 UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm | 4 +--
 .../Ia32/ExceptionHandlerAsm.nasm | 11 ++++----
 .../Ia32/ExceptionTssEntryAsm.nasm | 9 ++++---
 .../X64/ExceptionHandlerAsm.nasm | 14 +++++-----
 .../X64/Xcode5ExceptionHandlerAsm.nasm | 26 +++++++++----------
 UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 ++---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm | 4 +--
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +--
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm | 4 +--
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +--
 10 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
index a894ff53ad..66f8857fc0 100644
--- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
+++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;*
-;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. 
+;* Copyright (c) 2016, Intel Corporation. All rights reserved. 
 ;* SPDX-License-Identifier: BSD-2-Clause-Patent
 ;*
 ;* CpuAsm.nasm
@@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector):
 push rcx
 lea rax, [setCodeSelectorLongJump]
 push rax
- retfq
+ o64 retf
 setCodeSelectorLongJump:
 ret
 
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
index 3fe9aed1e8..58d5312899 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2016, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -32,13 +32,12 @@ ALIGN 8
 ; exception handler stub table
 ;
 AsmIdtVectorBegin:
-%assign Vector 0
 %rep 32
- push byte %[Vector];
+ db 0x6a ; push #VectorNum
+ db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
 push eax
 mov eax, ASM_PFX(CommonInterruptEntry)
 jmp eax
-%assign Vector Vector+1
 %endrep
 AsmIdtVectorEnd:
 
@@ -288,7 +287,7 @@ ErrorCodeAndVectorOnStack:
 test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
 ; edx still contains result from CPUID above
 jz .3
- fxsave [edi]
+ db 0xf, 0xae, 0x7 ;fxsave [edi]
 .3:
 
 ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
@@ -321,7 +320,7 @@ ErrorCodeAndVectorOnStack:
 ; are supported
 test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
 jz .4
- fxrstor [esi]
+ db 0xf, 0xae, 0xe ; fxrstor [esi]
 .4:
 add esp, 512
 
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
index b63cfeac6d..dd3f74d2aa 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2017, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -79,7 +79,8 @@ AsmExceptionEntryBegin:
 DoIret%[Vector]:
 iretd
 ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
- push byte %[Vector]
+ db 0x6a ; push #VectorNum
+ db %[Vector]
 mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
 call eax
 mov esp, eax ; Restore stack top
@@ -243,7 +244,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint):
 clts
 sub esp, 512
 mov edi, esp
- fxsave [edi]
+ db 0xf, 0xae, 0x7 ;fxsave [edi]
 .3:
 
 ;; UINT32 ExceptionData;
@@ -276,7 +277,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint):
 test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
 jz .4
 mov esi, esp
- fxrstor [esi]
+ db 0xf, 0xae, 0xe ; fxrstor [esi]
 .4:
 add esp, 512
 
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index 9a806d1f86..2a5545ecfd 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -32,13 +32,12 @@ SECTION .text
 ALIGN 8
 
 AsmIdtVectorBegin:
-%assign Vector 0
 %rep 32
- push byte %[Vector]
+ db 0x6a ; push #VectorNum
+ db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
 push rax
 mov rax, ASM_PFX(CommonInterruptEntry)
 jmp rax
-%assign Vector Vector+1
 %endrep
 AsmIdtVectorEnd:
 
@@ -258,7 +257,7 @@ DrFinish:
 ;; FX_SAVE_STATE_X64 FxSaveState;
 sub rsp, 512
 mov rdi, rsp
- fxsave [rdi]
+ db 0xf, 0xae, 0x7 ;fxsave [rdi]
 
 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
 cld
@@ -285,7 +284,7 @@ DrFinish:
 ;; FX_SAVE_STATE_X64 FxSaveState;
 
 mov rsi, rsp
- fxrstor [rsi]
+ db 0xf, 0xae, 0xE ; fxrstor [rsi]
 add rsp, 512
 
 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
@@ -372,7 +371,8 @@ DoReturn:
 push qword [rax + 0x18] ; save EFLAGS in new location
 mov rax, [rax] ; restore rax
 popfq ; restore EFLAGS
- retfq
+ DB 0x48 ; prefix to composite "retq" with next "retf"
+ retf ; far return
 DoIret:
 iretq
 
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
index 9c72fa5815..84a12ddb88 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -54,13 +54,12 @@ SECTION .text
 ALIGN 8
 
 AsmIdtVectorBegin:
-%assign Vector 0
 %rep 32
- push byte %[Vector]
+ db 0x6a ; push #VectorNum
+ db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
 push rax
 mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry)
 jmp rax
-%assign Vector Vector+1
 %endrep
 AsmIdtVectorEnd:
 
@@ -281,7 +280,7 @@ DrFinish:
 ;; FX_SAVE_STATE_X64 FxSaveState;
 sub rsp, 512
 mov rdi, rsp
- fxsave [rdi]
+ db 0xf, 0xae, 0x7 ;fxsave [rdi]
 
 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
 cld
@@ -336,15 +335,15 @@ DrFinish:
 jz CetDone
 ; SSP should be 0xFC0 at this point
 mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token
- incsspq rax ; After this SSP should be 0xFE0
- saveprevssp ; now the shadow stack restore token will be created at 0xFB8
- rdsspq rax ; Read new SSP, SSP should be 0xFE8
+ INCSSP_RAX ; After this SSP should be 0xFE0
+ SAVEPREVSSP ; now the shadow stack restore token will be created at 0xFB8
+ READSSP_RAX ; Read new SSP, SSP should be 0xFE8
 sub rax, 0x10
- clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this
+ CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 after this
 sub rax, 0x20
- rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8
+ RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will be 0xFB8
 mov rax, 0x01 ; Pop off the new save token created
- incsspq rax ; SSP should be 0xFC0 now
+ INCSSP_RAX ; SSP should be 0xFC0 now
 CetDone:
 
 cli
@@ -354,7 +353,7 @@ CetDone:
 ;; FX_SAVE_STATE_X64 FxSaveState;
 
 mov rsi, rsp
- fxrstor [rsi]
+ db 0xf, 0xae, 0xE ; fxrstor [rsi]
 add rsp, 512
 
 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
@@ -441,7 +440,8 @@ DoReturn:
 push qword [rax + 0x18] ; save EFLAGS in new location
 mov rax, [rax] ; restore rax
 popfq ; restore EFLAGS
- retfq
+ DB 0x48 ; prefix to composite "retq" with next "retf"
+ retf ; far return
 DoIret:
 iretq
 
diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
index f1422fd30a..f7f2937faf 100644
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Module Name:
@@ -345,7 +345,7 @@ BITS 64
 ;
 ; Far return into 32-bit mode
 ;
- retfq
+o64 retf
 
 BITS 32
 CompatMode:
@@ -507,7 +507,7 @@ NoSevEs:
 ;
 ; Far return into 32-bit mode
 ;
- retfq
+o64 retf
 
 BITS 32
 PmEntry:
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
index 9d66b9c5da..0919d6d05f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2019, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ;-------------------------------------------------------------------------------
@@ -13,7 +13,7 @@ ASM_PFX(DisableCet):
 
 ; Skip the pushed data for call
 mov eax, 1
- incsspd eax
+ INCSSP_EAX
 
 mov eax, cr4
 btr eax, 23 ; clear CET
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 19de5f614e..167f5e14db 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved. 
 ; Copyright (c) 2020, AMD Incorporated. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
@@ -252,7 +252,7 @@ CetInterruptDone:
 mov eax, 0x668 | CR4_CET
 mov cr4, eax
 
- setssbsy
+ SETSSBSY
 
 CetDone:
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
index 8bbdbb31cc..3240f9d974 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2019, Intel Corporation. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ;-------------------------------------------------------------------------------
@@ -14,7 +14,7 @@ ASM_PFX(DisableCet):
 
 ; Skip the pushed data for call
 mov rax, 1
- incsspq rax
+ INCSSP_RAX
 
 mov rax, cr4
 btr eax, 23 ; clear CET
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index d302ca8d01..0e154e5db9 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. 
+; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved. 
 ; Copyright (c) 2020, AMD Incorporated. All rights reserved. 
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
@@ -279,7 +279,7 @@ CetInterruptDone:
 mov eax, 0x668 | CR4_CET
 mov cr4, rax
 
- setssbsy
+ SETSSBSY
 
 CetDone:
 
-- 
2.26.2

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